JPH0646397A - Picture encoding device - Google Patents

Abstract

PURPOSE:To make DCT possible provided with plural conversion widths at a conversion width fixed DCT circuit by generating the mirror images of input signals, converting the input signals into a size suitable for the DCT circuit and converting DCT coefficients outputted from the DCT circuit into the coefficients before size conversion. CONSTITUTION:The input signals whose block sizes(Bs) are 8X4, 4X8 and 4X4 are converted into the signal of Bs 8X8 by a mirror image generation circuit 11 and the DCT circuit 12 executes the DCT of Bs 8X8. Further, a thinning-out circuit 13 converts the DCT coefficients of 8X8 into the DCT coefficients of 8X4, 4X8 and 4X4 corresponding to the Bs of the input signals. Also, the DCT coefficients of the respective Bs 8X4, 4X8 and 4X4 are converted into the DCT coefficients of 8X8 by an interpolation circuit 31 and an IDCT circuit 32 executes the IDCT of 8X8. Further, the output signals of the circuit 32 are converted into the signals of Bs 8X4, 4X8 and 4X4 by a mirror image deletion circuit 33 corresponding to the Bs of the input signals. Thus, the plural conversion widths can be provided in the conversion width fixed DCT and IDCT circuits 12 and 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine transform (hereinafter referred to as DCT) device, an inverse discrete cosine transform (hereinafter referred to as IDCT) device used in a high-efficiency image coding device, and these devices. The present invention relates to an image coding apparatus using.

[0002]

2. Description of the Related Art In recent years, international standardization of image coding methods has been promoted, and image coding methods using DCT are promising as candidates for standard methods. DCT device and ID
The CT device is used in an image coding device using this DCT. As this image encoding device, a configuration shown by an MPEG encoding reference model SM3 that promotes international standardization of a moving image encoding method is known (ISO-IE).
C / JTC1 / SC2 / WG11 N0010).

A conventional coding apparatus will be described below. FIG. 7 shows the configuration of a conventional encoding device. In FIG. 7, 71 is a subtractor, 72 is a DCT circuit,
73 is a quantization circuit, 74 is an encoding circuit, and 75 is an IDCT.
Circuit, 76 is an inverse quantization circuit, 171 is an input terminal, 172
Is an output terminal.

The operation of the coding apparatus configured as above will be described below. The subtractor 71 obtains the difference between the input signal to the input terminal 171 and the output signal of the IDCT circuit 75. The DCT circuit 72 DCTs the output signal of the subtractor 71. The output signal of the DCT circuit 72 is quantized by the quantization circuit 73 and output to the encoding circuit 74 and the inverse quantization circuit 76. The encoding circuit 74 is the quantization circuit 7
The output signal of No. 3 is converted into a code and output from the output terminal 172. The inverse quantization circuit 76 inversely quantizes the output signal of the quantization circuit 73. This dequantized signal is the IDCT
After being further subjected to IDCT in the circuit 75, it is output to the subtractor 71. As an algorithm for realizing the DCT circuit and the IDCT circuit, Morikawa et al., "Fast Cosine Transform Algorithm Based on Sequential Factorization of Chebyshev Polynomial" (Journal of the Institute of Information and Communication Engineers (A), J68-A, 2, p.
p. 173-180, 1985-02) are known.

[0005]

SUMMARY OF THE INVENTION In the above conventional configuration,
The block size, which is the unit for DCT, is N × N
(Vertical × horizontal), M × N, N × M, and M × M (Z: natural number, MεZ, N = 2M), it is necessary to execute DCT of each block size. A plurality of DCT circuits corresponding to all block sizes may be provided, or only a DCT circuit having a block size of N × N may be provided, and a DCT having a block size smaller than N × N may be regarded as a missing signal being, for example, all 0s. In addition, it was necessary to convert the block size to N × N and perform DCT. When a plurality of DCT circuits are provided, it is necessary to newly create a DCT circuit corresponding to M × N, N × M, and M × M block sizes and an IDCT circuit, resulting in an increase in hardware scale. There was a problem of doing. Further, when the block size is converted, there is a problem that the result of DCT is greatly affected by the block size conversion.

The present invention solves the above-mentioned conventional problems by generating a mirror image of an input signal having a plurality of block sizes such as M × N, N × M, and M × M.
Converting to a signal of block size N × N, D of N × N
The DCT coefficient is obtained by the CT circuit, and these are calculated as M × N, N
By converting to DCT coefficients of the original lock size such as × M and M × M, the DCT of multiple block sizes can be realized by using the N × N DCT circuit without being affected by the block size conversion. DCT device and M × N, N ×
DC for multiple block sizes such as M and M × M
After converting the T coefficient into a DCT coefficient having a block size of N × N, IDCT is performed in the N × N IDCT circuit, and further converted into an output result of the IDCT of the original block size, whereby an N × N IDCT circuit is obtained. IDCT device that realizes IDCT of a plurality of block sizes by using
Image coding using a plurality of DCT / IDCTs having different block sizes is performed using the T device and the IDCT device.
An object of the present invention is to provide an image encoding device that is realized without increasing the scale of hardware.

[0007]

In order to achieve this object, a DCT device of the present invention comprises a mirror image generating circuit for converting an input signal into a block size of N × N and a DCT having a block size of N × N. DCT circuit to realize and N × N DC
D when the T coefficient is DCT with the block size at the time of input
The IDCT device of the present invention has a thinning circuit for converting into CT coefficients, and an IDCT device of the present invention converts an input DCT coefficient into a DCT coefficient in a block size of N × N, and a block size of N × N. ID that realizes IDCT
The image coding apparatus according to the present invention includes a CT circuit and a mirror image deletion circuit that converts an IDCT N × N signal into an IDCT signal having an input block size. The DCT apparatus that realizes the above and the IDCT apparatus that realizes the IDCT having a plurality of conversion widths.

[0008]

With this configuration, in the DCT device, an input signal having a block size of M × N (M = N / 2), N × M, M × M, etc. is converted into a signal having a block size of N × N by the mirror image generation circuit. , And then converted into N × N DCT coefficients by the N × N DCT circuit, and then converted into N / N DCT coefficients corresponding to the original block size such as M × N by the decimation circuit.
By using a × N DCT circuit, D of a plurality of block sizes
CT can be realized. Further, in the IDCT apparatus, the DCT coefficients of block sizes M × N, N × M, M × M, etc. are converted into DCT coefficients of N × N block size by an interpolating circuit, and this is converted into N × N IDCT circuit. IDCT at
After converting to N × N signal, M × N, N
By converting into a signal of each block size of × M and M × M, the IDCT for a plurality of block sizes can be realized by using the N × N IDCT circuit.

Further, in the image coding apparatus, this DCT
By using the device and the IDCT device, N × N,
Encoding using DCTs of a plurality of block sizes such as M × N, N × M, and M × M can be realized by using the DCT and IDCT circuits for one block size of N × N. In the image coding device, DCT devices and IDCTs that had to be installed in parallel by the number of block sizes
One device is sufficient for each, and the hardware scale can be significantly reduced.

[0010]

(Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block connection diagram of a DCT device according to a first embodiment of the present invention.

In FIG. 1, 11 is a mirror image generation circuit, and 12
Is a DCT circuit that realizes a DCT of 8 × 8 block size, 13 is a thinning circuit, 111 is an input terminal of a signal indicating the block size, 112 is an input terminal of an image signal, 113
Is an output terminal of the DCT coefficient.

The operation of the DCT device constructed as above will be described below. In the mirror image generation circuit 11,
First, a signal indicating a block size such as 8 × 4 is input to the input terminal 111, and an image signal input from the input terminal 112 based on this signal is converted into a memory space having a 4 × 4 area shown in FIG. It is arranged at a predetermined position of A, B, C and D. For example, when the block size is 8 × 8, the block size is 4 × 8 in the areas A, B, C, and D.
In the case, the image signals are arranged in the areas A and B, in the areas A and C when the block size is 8 × 4, and in the area A when the block size is 4 × 4. Next, this data is copied in the memory space to generate a mirror image of the input data and output to the DCT circuit 12. When the block size is 4 × 8, the data in the area AB is copied to the CD symmetrically with the X axis. When the block size is 8 × 4, the data in the area AC is copied to the BD symmetrically with respect to the Y axis. When the block size is 4 × 4, the data in the area A is copied to B symmetrically with respect to the X axis, and AB is further copied to CD with symmetrically with respect to the Y axis. The DCT circuit 12 is 8 ×
The 8 input signals are converted into 8 × 8 DCT coefficients. At this time, the relationship between the 8 × 4, 4 × 8, 4 × 4 DCT coefficient and the 8 × 8 DCT coefficient is as shown in (Equation 1). However, in (Equation 1), the DCT coefficient of the U row and V column of the block size N × M (vertical × horizontal) is F [N, M] (U,
V).

[0013]

[Equation 1]

In the thinning circuit 13, based on the signal indicating the block size input from the input terminal 111, (Equation 1)
Then, the DCT coefficient output from the DCT circuit 12 is thinned out and output from the output terminal 113. This operation will be described with reference to FIG. The 8 × 8 DCT coefficient is stored in the memory space ABCD shown in FIG. 2, where the upper left corner of the DC coefficient is (0,0), and B is B.
The upper right of the coefficient (0,7), which indicates the high frequency only in the lateral direction, C
The lower left of is a coefficient (7,0) that indicates high frequency only in the vertical direction, D
The lower right of is a coefficient (7,7) that indicates high frequency in both vertical and horizontal directions.
So that This DCT coefficient is set to the upper right (0,
(0) to the lower right (7, 7) are input to the thinning circuit 13 in the order of raster scanning, and when the horizontal block size is 4, thinning is performed for each column and 1 / √2 is multiplied by the multiplier. When the vertical block size is 4, each row is thinned out, multiplied by 1 / √2 by the multiplier, and output.

As described above, according to the present embodiment, the mirror image generation circuit 11 for converting the input signal of block size 8 × 4, 4 × 8, 4 × 4 into the signal of block size 8 × 8.
And a DCT that executes a DCT with a block size of 8x8
By providing the circuit 12 and the thinning circuit 13 for converting the 8 × 8 DCT coefficient into the 8 × 4, 4 × 8, 4 × 4 DCT coefficient according to the block size of the input signal, the block size can be reduced. A DCT having a block size of 8 × 4, 4 × 8, and 4 × 4 can be realized by using an 8 × 8 DCT circuit.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block connection diagram of an IDCT apparatus according to the second embodiment of the present invention.

In FIG. 3, 31 is an interpolation circuit and 32 is an I.
A DCT circuit, 33 is a mirror image erasing circuit, 131 is a signal input terminal indicating a block size, 132 is a DCT coefficient input terminal, and 133 is an output terminal.

The operation of the IDCT apparatus constructed as above will be described below. In the interpolation circuit 31, first, a signal indicating a block size such as 8 × 4 is input to the input terminal 131, and the DCT coefficient input to the input terminal 132 is interpolated based on this signal according to (Equation 1), and 8 × 8
To the DCT coefficient of When the horizontal size of the input signal is 4, the coefficient (Y, ODD) at a position where the horizontal component is an odd number (Y is a natural number 7 or less, ODD = 1,
3, 5, 7), 0 is substituted, and the coefficient (Y, EVEN) (EVEN = 0, 2, 4,) at the position where the horizontal component is even
6), the input signals (Y, X) (X = 0, 1, 2,
The signal obtained by multiplying 3) by √2 by the multiplier is EVEN = 2.
Interpolate by substituting at the position of × X. When the size in the vertical direction is 4, as in the case where the size in the horizontal direction is 4, 0 is substituted for the coefficient at the position where the vertical component is odd, and the coefficient at the position where the vertical component is even The input signal is multiplied by √
Interpolate by substituting the doubled signal. The IDCT circuit 32 outputs the DCT coefficient output from the interpolation circuit 31 to the IDCT circuit.
Then, the result is output to the mirror image deletion circuit 33. In the mirror image deletion circuit 33, the signal indicating the block size is input to the input terminal 1
A signal having a required block size is extracted from the signal input from the signal 31 and subjected to IDCT based on this signal. This extraction process will be described with reference to FIG. The mirror image deletion circuit 33
The output signal of the DCT circuit 32 is converted into the memory space A shown in FIG.
It is placed at a predetermined position on the BCD. At this time, when the block size of the input signal is 4 × 8, AB and CD are X.
In the case of 8 × 4, AC and BD are symmetrical with respect to the Y axis, and in the case of 4 × 4, AC and BD are along the X axis, and AB
And CD are symmetrical about the Y axis. Therefore, 4
In the case of × 8, AB is extracted, in the case of 8 × 4, AC is extracted, and in the case of 4 × 4, A is extracted and output from the output terminal 133.

As described above, according to this embodiment, 8 × 4,
An interpolation circuit 31 for converting the DCT coefficient for each of the 4 × 8 and 4 × 4 block sizes into an 8 × 8 DCT coefficient;
An IDCT circuit 32 for executing an IDCT of × 8, and an 8 × 8
By providing a mirror image deletion circuit 33 for converting an output signal from the IDCT into a signal having a block size of 8 × 4, 4 × 8, 4 × 4 according to the block size of the input signal, the block size is 8 ×. 8 IDCT circuits can be used to realize IDCTs having block sizes of 8 × 4, 4 × 8, and 4 × 4.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block connection diagram of an image coding apparatus according to the third embodiment of the present invention.

In FIG. 4, 40 is a subtractor, 41 is a thinning circuit, 42 is a DCT circuit, 43 is a quantization circuit, 44 is an encoding circuit, 45 is an interpolation circuit, 46 is an IDCT circuit, 4
7 is an inverse quantization circuit, 141 and 142 are input terminals, 143
Is an output terminal.

The operation of the image coding apparatus configured as described above will be described below. The subtractor 40 obtains the difference between the input signal of the input terminal 141 and the output signal of the interpolation circuit 45. The thinning circuit 41 thins the output signal of the subtractor 40 based on the signal indicating the degree of thinning input to the input terminal 142. In the DCT circuit 42, the input terminal 142
The output signal of the thinning circuit 41 based on the input signal from
T and output to the quantization circuit 43. Quantization circuit 43
Refers to the quantization table from the value of the input signal from the thinning circuit 41 and the separately determined quantization width, and the value obtained by quantizing the input signal from the thinning circuit 41 is encoded circuit 44 and inverse quantization circuit. And 47. In the encoding circuit 44,
A code is subtracted from the code table based on the value of the output signal of the quantization circuit 43, and output from the output terminal 143. The dequantization circuit 47 uses the quantization width used at the time of quantization and the quantization circuit 47.
The input signal is dequantized by referring to the dequantization table on the basis of the output signal of 1 and output to the IDCT circuit 46. IDC
In the T circuit 46, the output signal of the inverse quantization circuit 47 is IDCT based on the input signal to the input terminal 142, and the interpolation circuit 45
Output to. In the interpolation circuit 45, the output signal of the IDCT circuit 46 is interpolated based on the input signal of the input terminal 142 to be converted into an image signal having a block size of 8 × 8, and the subtractor 40
Output to.

The thinning circuit 41 and the interpolation circuit 45 will be described with reference to the drawings.

First, the thinning circuit 41 will be described.
FIG. 5 shows the configuration of the thinning circuit 41. In FIG. 5, 50 is a memory, 51 is a signal control circuit, and 52.
Is a memory calling position storage table, 53 is a delay element, and 54
Is an adder, 55 is a multiplier, 56 is a 1/2 decimation circuit, 1
Reference numeral 51 is an image signal input terminal, 152 is a signal input terminal indicating the degree of thinning, and 153 is an output terminal.

The operation of the thinning circuit configured as described above will be described below. The memory 50 stores the input signal of the input terminal 151 in a predetermined position. The signal control circuit 51 draws the data calling position from the memory calling position storage table 52 based on the signal indicating the degree of thinning input from the input terminal 152, and the memory 5
The contents of 0 are sequentially output to the delay element 53 and the adder 54. The signal delayed by one pixel in the delay element 53 is added to the output of the signal control circuit 51 in the adder 54, and the multiplier 55
Is multiplied by 0.5. After that, the pixels are thinned out every other pixel by the 1/2 thinning circuit 56 and stored in a predetermined position of the memory 50. At this time, by controlling the order of calling data from the memory 50, it is possible to perform thinning in both the vertical and horizontal directions. For example, if the block size is 8x8, you can store in the memory in this positional relationship and call the first line from left to right, then the second line from left to right, and so on until the last line. The thinning in the horizontal direction can be realized, and the thinning in the vertical direction can be realized by calling the first row from the top to the bottom and then the second row from the top to the bottom until the final row. After the decimation is completed, the signal control circuit 51 causes the 1/2 decimation circuit 56 to
Is called from the memory 50 and is output from the output terminal 153.

Next, the interpolation circuit 45 will be described. FIG. 6 shows the configuration of the interpolation circuit 45. 60
Is a memory, 61 is a signal control circuit, 62 is a memory calling position reference table, 63 and 64 are delay elements, 65 and 66 are adders, 67 is a multiplier, 161 is an image signal input terminal, 1
Reference numeral 62 is an input terminal for a signal indicating the degree of thinning, and 163 is an output terminal.

The operation of the interpolating circuit 45 constructed as above will be described below. The memory 60 stores the input signal of the input terminal 161 in a predetermined position.
The signal control circuit 61 extracts the data calling position from the memory calling position storage table 62 based on the signal indicating the degree of thinning input to the input terminal 162, and the memory 6
The contents of 0 are sequentially output to the delay element 63 and the adder 65. At this time, the signal control circuit 61 alternately outputs the signal called from the memory 60 and 0 to interpolate the input signal. The signal delayed by one pixel by the delay element 63 is output to the adder 66 and the delay element 64. 1 in delay element 64
The signal delayed by the pixel is added by the adder 65 to the signal control circuit 6
It is added to the output of 0 and multiplied by 0.5 in the multiplier 67. The output signal of the multiplier 67 is added to the output of the delay element 63 by the adder 66 and stored in a predetermined position of the memory 60. After the interpolation is completed, the signal control circuit 61 causes the multiplier 67 to
Is output from the output terminal 163. Similarly to the thinning circuit 41, the interpolating circuit 45 can realize interpolation in the vertical, horizontal, and both directions by controlling the order of calling the data in the memory.

As described above, according to this embodiment, by providing the DCT device and the IDCT device, the DCT circuit and the IDC circuit corresponding to a specific block size are used, and the DCTs in a plurality of block sizes are obtained. It becomes possible to encode using.

[0029]

As described above, according to the present invention, by providing the mirror image generating circuit and the thinning-out circuit, it is possible to realize DCTs having different block sizes by using the DCT circuit corresponding to a specific block size. , And a mirror image deletion circuit, the IDCT circuit corresponding to a specific block size is used to generate a plurality of I's having different block sizes.
DCT can be realized. By providing the DCT device and the IDCT device in the encoding device, it is possible to perform the DCT corresponding to a specific block size and the encoding using the DCT in a plurality of block sizes while using the IDCT circuit. . As a result, the DCT circuit and the IDCT circuit, which have conventionally been required to be provided in parallel by the number of block sizes to be used, can be realized by one DCT circuit and IDCT circuit, so that the hardware scale can be reduced. , Its effect is great.

[Brief description of drawings]

FIG. 1 is a block connection diagram of a DCT device according to a first embodiment of the present invention.

FIG. 2 is a layout diagram of a memory space of the DCT device according to the first embodiment.

FIG. 3 is a block connection diagram of an IDCT apparatus according to a second embodiment of the present invention.

FIG. 4 is a block connection diagram of an image coding apparatus according to a third embodiment of the present invention.

FIG. 5 is a block connection diagram of a thinning circuit which is a main part of the image coding apparatus according to the third embodiment.

FIG. 6 is a block connection diagram of an interpolation circuit which is a main part of the image coding apparatus according to the third embodiment.

FIG. 7 is a block connection diagram of a conventional image encoding device.

[Explanation of symbols]

 11 mirror image generation circuit 12 DCT circuit 13 thinning circuit 31 interpolation circuit 32 IDCT circuit 33 mirror image deletion circuit 40 subtractor 41 thinning circuit 42 DCT circuit 43 quantization circuit 44 encoding circuit 45 interpolation circuit 46 IDCT circuit 47 inverse quantization circuit 50 memory 51 signal control circuit 52 memory calling position storage table 53 delay element 54 adder 55 multiplier 56 1/2 thinning circuit 60 memory 61 signal control circuit 62 memory calling position storage table 63, 64 delay element 65, 66 adder 67 multiplier 71 Subtractor 72 DCT circuit 73 Quantization circuit 74 Encoding circuit 75 IDCT circuit 76 Inverse quantization circuit

Claims (3)

[Claims] 1. A discrete cosine transform circuit for converting a signal input with a constant block size into discrete cosine transform coefficients and outputting the discrete cosine transform coefficient, and a mirror image of the signal input with a plurality of block sizes. , A mirror image generation circuit for converting to a block size suitable for the discrete cosine transform circuit and outputting the block size, and a discrete cosine transform coefficient output from the discrete cosine transform circuit for the block size of the input signal to the mirror image generator circuit as it is. The decimation cosine transform that transforms the discrete cosine transform coefficient obtained when the discrete cosine transform is performed and outputs it, and the inverse cosine transform that outputs the discrete cosine transform coefficient signal that is input with a fixed block size Suitable for the above inverse discrete cosine transform circuit by interpolating the circuit and signals input in multiple block sizes And the output signal from the inverse discrete cosine transform circuit, which is converted to the block size and output, is converted into the signal obtained when the inverse discrete cosine transform is performed on the input signal to the interpolator with the same block size. An image encoding apparatus including a mirror image deletion circuit that outputs the image. 2. A discrete cosine transform circuit for converting a signal input with a fixed block size into a discrete cosine transform coefficient and outputting the discrete cosine transform coefficient, and a mirror image of the signal input with a plurality of block sizes. , A mirror image generation circuit for converting to a block size suitable for the discrete cosine transform circuit and outputting the block size, and a discrete cosine transform coefficient output from the discrete cosine transform circuit for the block size of the input signal to the mirror image generator circuit as it is. A discrete cosine transform device having a thinning circuit for converting and outputting discrete cosine transform coefficients obtained when discrete cosine transform is performed. 3. An inverse discrete cosine transform circuit for inverse discrete cosine transforming and outputting a discrete cosine transform coefficient signal input in a fixed block size, and a signal input in a plurality of block sizes by interpolation, An interpolator that converts the block size suitable for the inverse discrete cosine transform circuit and outputs the result, and an output signal from the inverse discrete cosine transform circuit, which is obtained by subjecting the input signal to the interpolator to the inverse discrete cosine transform with the same block size. An inverse discrete cosine transform device including a mirror image deletion circuit for converting and outputting a signal obtained at that time.