JPH0646386B2 - Microcomputer equipment - Google Patents

Description

The present invention relates to integrated semiconductor devices and apparatus, and more particularly to features used in electronic digital processing apparatus in the form of a single chip microprocessor or microcomputer.

A microprocessor device was issued to Gray W. Boone and assigned to Texas Instruments US Pat. No. 3,7.
No. 57,306, "MOS / LS
A central processing unit or CPU for a digital processor contained in a single semiconductor integrated circuit, usually assembled by "I" technology. The Boon patent shows an 8-bit CPU in a chip containing parallel ALUs, data and address registers, instruction registers, and control decoders, all interconnected using a bidirectional parallel bus. US Pat. No. 4,074,351 issued to Gray W. Boon and Michael J. Cochran and assigned to Texas Instruments is on-chip for program and data storage. 4 with ROM and RAM
1 illustrates a single chip "microcomputer" type device that includes a bit parallel ALU and its control circuitry. A microprocessor usually refers to a device that uses external memory for program and data storage, whereas a microcomputer is an on-chip R for program and data storage.
It refers to a device that includes an OM and a RAM. However, the use of both terms is compatible and is not intended to limit the present invention.

U.S. Pat. Nos. 3,757,306 and 4,074,
Since 1971, when the 351 was first filed, numerous improvements have been made to microprocessors and microcomputers to increase the speed and capability of these devices and reduce manufacturing costs, allowing more circuits to fit in smaller spaces. It was made, that is, the chip size was further reduced. Although the improved photo-etching method provides narrower linewidths and higher resolutions and higher circuit densities, improvements in circuits and devices have also contributed to the goal of improving performance in small chips. Some of these improvements to the microprocessor are disclosed in Japanese Patent Application No. 57-60848.

It is a primary object of the present invention to provide an improved microcomputer or microprocessor device adapted for widespread use yet facilitating inexpensive manufacture and minimizing programming costs. is there.

Another object is to provide a microcomputer device that is more versatile for use in a variety of programs programmed into standard chip format. In particular, one objective is to provide a microcomputer device that can change the amount of microcoding used to execute instructions without changing any mask during the manufacturing process other than the gate mask.

One embodiment of the present invention provides a microcomputer device in which a "user" ROM is combined with a "control" ROM. User ROM typically contains programs written in microcode, and control ROM typically contains microcode used to execute macrocode. This combination ROM, which contains both macrocode and microcode, is addressed in two ways: the program counter and the memory address register used to call the logical address space over the address bus first This entry ROM can be called and then the entry point circuit used to create the control ROM address can call this combination ROM. In one form, the Y decoder is isolated because the macrocode output from the combination ROM is 1
This is because the byte width is, but the microcode output is about 6 to 8 bytes or larger.
In the memory call cycle for the combined ROM address space, control is created to select either macrocode or microcode output, for example control from the current microcode output. By combining macro code and micro code into a single ROM, the amount of micro coding for a particular device is optimal for execution speed, customer programming mitigation, security,
Or selected for other factors. The amount of microcode can vary from standard microinstructions that are always set to virtually 100% microcode, ie many complex microinstructions in a significantly expanded instruction set.

The combined macrocode and microcode memory can be RAM instead of ROM, so the user can define the functionality of the device by his immediate job, from an external disk, tape or ROM, or by telephone line. Allows to download microcode along with macrocode. That is, different instruction sets are used in different parts of the job. The terminal is microprogrammed at one point to perform floating point or BCD operations and then at another point to perform duplex transfer instructions, eg, for valid data transfers.

An important feature of one embodiment of the present invention is that the microcode is called by the memory data bus in a byte wide portion for ALU operations or external transfers. That is, the microcode stored in the combination ROM is added to the ALUM temporary register or written to the external port, one byte at a time. This is extremely useful for testing purposes. Also, the only way to test the microcode is to perform all possible functions to see if you are getting the correct results.

The features of the invention believed to be novel are set forth in the appended claims. However, the invention itself, together with other features and advantages, will be best understood by reading the following detailed description of the drawings.

Referring to FIG. 1, a microcomputer chip 10 using features according to one embodiment of the present invention is shown.
Chip 10 is a standard 40-pin package mounted on one side with silicon of about 5.08 mm (200 mils) or less.
It is a MOS / LSI type semiconductor integrated circuit including a bar.
In the chip 10 is a combined user RO according to the present invention.
A digital processor with M and control ROM 11 is all included. This ROM or read-only memory 11 is used both for program storage and microcode storage. RAM or read / write memory 1
2 is used for data storage. The chip contains an arithmetic logic unit or ALU 14 and its working register 15.
And a bus 16 and a CPU 13 consisting of the control ROM output of ROM 11 which produces microinstruction or control signals on line 18. The CPU 13 along with the three lines in the control line 18 are connected to the ROM 11 and RA by three buses: a memory data bus MD, a high address bus AH, and a low address bus AL.
Call M12. In addition, the micro address bus μ
A calls ROM 11 for a microcode fetch. Communication with the chip's external devices is activated by the control circuitry invoked by the MD bus and responsive to AH and AL addresses. By 4 memory mapped 8-bit ports A, B, C and D. In this embodiment, the MD, AH and AL buses are ALU1.
4, as well as registers 15 and ports, are 8 bits wide, but of course the ideas described here can be applied to, for example, 4 bit, 16 bit or 32 bit devices.

The register 15 in the CPU 13 has an instruction register I
R, a status register ST, a shift circuit S receiving the output of the ALU 14, a register T / MAH serving as a temporary storage device for an operand and a high-order byte (memory address high) of a memory address, two 8-bits It includes a 16-bit program counter stack pointer SP which is divided into registers PCH and PCL (program counter high and low), a memory address low register MAL and the like. Address buffer 19 produces the true and complement address signals appearing on buses AH 'and AL' from address buses AH and AL. Most of the operands are temporary registers 15 that are combined with the CPU 13.
RAM acting as a register file RF, not at
Stored in 12.

Bus 16 interconnects the various registers 15, ALU 14 and MD buses, AH 'bus and AL' bus. The ALU 14 always receives the P input from the P bus and the N input from the N bus, and produces an output to the output bus, that is, the O bus via the shift circuit S. Each of these P, N and O buses 16 has a register 15 and an ALU 14
, And the call to the MD, AH, and AL buses is microcode, that is, control signal 1 from ROM 11.
Controlled by 8.

The microcomputer chip 10 operates on the basis of an 8-bit macro instruction word stored in the ROM 11 and transferred to the instruction register IR one word at a time. CPU1
1 of the many possible examples of macro instruction sets executed in 3.
Table A and Japanese Patent Application "Patent No. 57-608"
48, and Table A gives the mnemonic imperatives, also called assembly or atomic language, as well as binary machine language opcodes (which are used to represent objects in hexadecimal (Similar to code) is also given. The instruction set is published in 1981 by Texas Instruments, "8 of the TMS7000 series."
It is described in detail in a booklet entitled "Bit Microcomputer", which also describes address modes. The opcode and one or more address bytes are typically used to execute the instruction. The instruction word or opcode held in the IR is the address circuit 11 for the ROM 11.
microaddress line μA coupled to x and 11y '
Which is the input of the entry point circuit 21 for creating the 8-bit address appearing in the ROM 11 (in this embodiment).
Calling one of the 256 possible addresses for Table B and FIG. 8 or the Japanese patent application “JP 57-6-6”.
1 of the microinstructions as shown in "0848 Specification"
Create a control bit or control signal that defines one. One macroinstruction in Table A creates a set of microinstructions. Some micro-instructions (ie some of the outputs 18) are in ROM
Used to create the next μA address for the microjump address, the microjump address is fed back to the entry point circuit 21 via line and the nomination control information is fed back via line 24. That is, a set of microinstructions is made up of each macroinstruction loaded into the IR, and the sequence also depends on the status bits in the status register ST and other conditions. The address for the operand is included in the macrocode word from ROM 11 with the opcode, if necessary, and is transferred to MAL or MAH during this sequence of microcode states while the opcode remains IR. Each address applied to the combination ROM 11 is sent to the microcode output 1
8 or make a macro output to the memory data bus MD via the Y decode 11y. The CPU cannot call both macro code and micro code in the same machine state.

A map of the logical address space for the microcomputer of FIG. 1 is shown in FIG. This embodiment has 16
Since we are using an 8-bit AH address and an AL address that gives the bit address, 2 ¹⁶ or 6
5,536 bytes are available in this space (often called "64K" bytes with "K" = 1,024). The address is represented by four hexadecimal digits and extends from the first address 0000 to the final address FFFF. In this description, memory addresses are given in hexadecimal unless otherwise specified. 1 page is 2 ⁸ or 256 bytes, that is, all the addresses in a page determined by the AL, and the page is selected by the AH. Microcomputer 1
0 is a "0" page for register file RF in RAM 12 (addresses 0000 to 00FF)
For the peripheral file PF, "1" page (address 01
00 to 01FF) and F0 to FF pages (addresses F000 to FFFF) for combination programs and microcode memory ROM 11. The macro code is 8 bits wide,
Since the microcode of this example is about 8 bytes or 64 bits wide, each address for the microcode occupies 8 bytes in the map of FIG. Therefore, if 256 micro-instructions are required, this is
Occupies 8 bytes or 16K bits. In the example instruction set, micro addresses 00 to FF are used for micro code (corresponding to macro addresses F000 to F7FF), and the remaining addresses F800 to FFFF are used for macro code. Some of the space allocated for RF and ROM 11 is in ROM and RA.
Not populated by the selected size of M. 02
Other spaces, such as 00 to EFFF, are utilized for the magnifying mode as shown in Japanese Patent Application No. 57-60848.

Although not relevant to the present invention and therefore not described in detail herein, a microcomputer such as FIG.
A control circuit responsive to both AH 'and L'addresses and control bit 18 is included to define how U13 calls the peripheral file PF, which includes external port, timer / event counter, reset and interrupt functions. ing. I / O in memory location 0100 of FIG.
And the interrupt control register is loaded directly by the MD bus, which is part of the ALU / register strip, this register may include two memory mode control bits to define the memory expansion mode, along with the interrupt mask and flags. . A programmable timer and event count are also included in this peripheral control circuit.
Called by the MD bus and 8-bit wide advantageously made as part of the LU / register strip.

In this peripheral control circuit, the group decode circuit 27 and the memory control circuit 28 include AH 'and AL' address bits and three control signals (#MEM, #WR, #M).
EMCNT) to create a control that selects ROM 11 (microcode or macrocode), RAM 12, port A, B, C or D etc. for a call at a given address. Only one of the three is activated in any one cycle.

More than one interrupt input pin INT is usually provided in addition to the timer interrupt. These INT inputs are connected to an interrupt control circuit 29 which also reacts to other conditions on the chip. The reset input RST is conventionally used to zero or initialize a microcomputer that ignores any function or interrupt. Micro interrupts may be included as described below.

Peripheral control circuitry provides a selection of operating modes defined by internally loaded bits 7 and 6 of I / O control register 0100. Although the address space of Figure 2 is uniquely configured for these modes, the register file address space RF is the same for all modes. Modes include (1) single-chip computer mode of Figure 2a in which all memory is on-chip in ROM 11 and RAM 12; (2) some additional off-chip circuitry via ports B and C. Peripheral expansion mode of FIG. 2b called into PF space; or (3) If RF and ROM 11 are the same as in FIG. 2, about 61K of off-chip memory.
There are three types of bytes, the full expansion mode of Figure 2c, where the bytes are called by port B as well as port C. Other modes can be utilized as described in Japanese Patent Application No. Sho 57-60848. The various motes provide a wide variety of different functions in one basic chip format without changing the design, layout or microcode, thus significantly reducing cost. The input / output buffer 30 has a direction control register P in a certain mode.
7, P9, P11 (Fig. 2a), again group
Ports A, B, as determined by the mode controller via decode 27 and memory control circuit 28.
Connect C and D to MD bus. In the buffer 30, MD
Data registers P6, P called by the bus
8, P10 and P11 are included.

In FIG. 3, the microcomputer of FIG. 1 is shown in the form of a chip layout. Most of the area of the chip 10 is occupied by the combined ROM 11 and RAM 12 and the memory containing the respective address data. The ROM 11 is combined with a combination X address decoder 11x for microinstructions and microcode and separate Y address decoders 11y, 11y '. 12 addresses to define one of 4096 8-bit bytes in ROM 11
Since bits are used, the address of ROM 11 is MA
It requires both L and MAH registers, i.e. address bits from both AL and AH buses for microinstruction calls. In one example, the microcode call via μA is 8 bits
Only one page called by address, ie 25
Seems to require 6 locations, but additional addresses
Space is added by increasing the width of the μA address. A 9-bit μA would call 512 locations, for example. The RAM has an X address decoder 12x that selects one of the 32 rows and a 1 of the 4 columns
With the Y address decoder 12y selecting one, only 7 bits are required for RAM selection (8 bits if 256 byte RAM is used).

One major feature is that the number of microcode states can be changed without new chip design, layout, mask making and production efforts. In this example, ROM
11 has a size of 4096 × 8, that is, 32K bits. If fully populated, if the 8-bit microcode address μA is used, the number of bits in ROM 11 used for microcode will be 256 times the number of output lines 18. 64 output lines 18 are the Ath
Used in the example instruction set of the table, 256 microinstruction addresses or states are stored (but one example such as Tables B and C or Japanese Patent Application No. 57-60848). Less than 150), so the ROM microcode portion is 256
It is x64, that is, 16K bits. The rest is available for macrocode (32-16K = 16K bits or 2K bytes).

ROM 11 is next to the strip that provides microcode control 18 in the control centralized area of the ALU and register / bus connections, and address control and interlaced address lines 2
It fits next to the entry point circuit 21, which requires 3, 24. The design is directed to combinatorial ROM 11 as an overall control source, rather than using random logic for this purpose, and the layout of FIG. 3 shows that the chip area is much smaller due to RAM and combinatorial ROM and their decoding. Is dominated by a strip containing a regular array of ALU / register bits occupied by other control logic. This design method changes microcode and macrocode,
The value can be increased by changing the ratio between the microcode and the macrocode of the OM 11, and thereby the microprogramming function for transforming the microcomputer 10 particularly easily is enhanced.

The microcomputer 10 is modified in four stages and mode control. The first step is to change the macro code or program of the ROM 11, which is of course the most widely implemented variant. Macrocode is defined by a single mask in the manufacturing process, as shown, for example, in U.S. Pat. Nos. 3,541,543, 4,208,726 or 4,230,504 assigned to Texas Instruments. To be By rewriting the macro code, keeping the set of micro and macro instructions the same, a wide variety of different functions and operations are available. As a second step, the microinstruction set in Table A is supplemented (using the same microinstruction set in Table B and adding some other microinstructions) by making extensive use of the microcode storage in ROM 11. . (The microcode of the ROM 11 is a single mask during manufacturing, that is, the same mask that defines the macro code)
It is also easy to change the macro or micro instruction set structurally, as defined by But then the macro assembler and the micro assembler (computer programs used as design aids for customers) are different. The micro assembler is written for all suitable useful micro-states, at which time the only selected number (up to 256 in this example) for a given type is selected. Of course, in addition to these methods of altering the device 10, additional microcode or macrocode in ROM may be utilized to program RO to program more complex algorithms.
The size of M can be increased. However, a key feature of the present invention is that the ratio of microcode to macrocode in ROM 11 can be varied to provide a more or less complex micro / macro instruction set.

The microcomputer chip 10 operates with a basic clock frequency represented as a crystal (Xtal) in FIG. This frequency of about 5 MHz is provided by an internal oscillator 33 controlled by an external crystal coupled to the two pads labeled Xtal in FIG. 1 or 3. From the clock crystal, the clock generation circuit 33, as seen in FIG. 4, has four basic half-cycle clocks H1, H that overlap for each microinstruction cycle or state time S1, S2, etc.
Make 2, H3 and H4. Each state time is clock Xtal
Equal to two complete cycles of. H4 overlaps the two state times. Quarter cycles Q1, Q2, Q3 and Q4 are also defined within each state time.

Calls to RAM 12 occur at the same time as microcode calls from ROM 11. A short memory cycle calling RAM12 is completed in one state time, such as S1 in FIG. 4, control #MEMCNT is low and all bits on the AH bus are low for H1 and the RAM address is # A valid address appearing on the AL bus while MEM is high. Write control #WR is high for writing and low for reading. The recalled data is then valid data appearing on the MD bus during H4 at the end of the cycle over the beginning of the next cycle, so that the data is loaded into register T or IR at the end of one cycle, Is gated to the P or N bus at the beginning of the. RAM12
All memory references to the register file RF at

All other memory references (ie on-chip ROM 11 for macrocode, peripheral files PF, and references to extended memory in extended mode) require two microinstruction cycles and are as shown in FIG. Long memory cycles are required. For long cycles, the memory continue command #MEMCNT is high during the first state time and low during the second state time. Memory command #MEM must be high during H1 of both cycles and the address is AL and AL during H1 of the first cycle.
Must be valid at. For reading, the write command #WR is low from the beginning of the first cycle to H1 of the second cycle and the data is valid during the beginning of H4 at the end of the second cycle. For a long write, #WR is high and the write data is high on both the first and second cycles.
At 4 the MD bus is gated.

Within a given state time or microinstruction cycle, addresses appearing on the AH 'and AL' buses are valid during H2. This address is based on the address loaded into AH and AL during H1. In ROM 11, the array is precharged during Q1, all rows or X lines go to Vss and all columns or Y lines go to Vcc, then RO
The M X address is gated into the array from the decoder 11x at the beginning of Q2 and the ROM Y address is valid at the beginning of Q2, so the ROM output is valid with Q4, either in the microcode or the macro code.

Table A of the present specification or Japanese patent application “JP-A-57-6”
In executing the microinstruction set of "0848", 5 to 10 microcode states such as S1 and S2 are added depending on the address mode,
Usually required for instructions such as move, compare, etc., but multiplication or division requires more microcode states.

As can be seen in FIGS. 4 and 4a, the timing of microcode calls to ROM 11 is different during macrocode fetching. During all other machine cycles except short memory cycles and macro code fetches,
The GROM command is asserted (MUXCNTL is low) and the decoder for ROM 11 receives the μA address generated in entry point circuit 21 in the previous cycle. This is shown in the center of Figure 4 and in Figure 4a. The CROM command does not occur, the addresses from AH and AL do not activate the decoder 11x of the ROM 11, and the output does not reach the MD via the latch 11c. However, #MEM
When the AH address of the page from CNT and FO to FF occurs, the MUXCNTL and GROM commands are asserted and the decoders 11x and 11y are AH ', AL'.
Receive an address. This means that the microcode calls are modified as shown in the bottom of FIG. 4 and in FIG. 4a because of the long memory cycle for fetching the macrocode. The microaddress μA output from the entry point circuit 21 generated in the last cycle is valid during Q2, the state before S1, and MUXCN
ROM by GROM during Q4 when TL is low
11 produces a microcode output which appears on line 18 for execution in state S1 when gated to the decoder. The address that the macro code should fetch is Q appearing in AL and AH.
2 makes it valid and is latched in the buffer 19.
The microaddress μA to be produced by this state S1 from the lines 23, 24 is valid in S1Q1 to S2Q4 and, as seen in FIGS. 4 and 4a, GRO
Held by holding lines 23, 24 valid by latching buffer 11b due to lack of M command. This latched μA is S2 for microaddress in state S3.
It starts in Q1 and is used. During S2, ROM11 is S1
During this time, the macro code is called with the addresses created in AL and AH. Macro code data is 8 during S1
Latched by bit latch 11c, which is GR
Makes an 8-bit macrocode output to the MD bus when OM is asserted in S2Q4. The microcode executed in S2 'of the macrocode fetch cycle is in state S1.
Made in accordance with the microcode from, normally incrementing the PCH, and loading the data coming from ROM 11 via MD into IR or T, or using it in the next state S3 as the address appearing in AH or AL. For M
Leave it in D. This S2 'microcode is taken out during S1 at the same time that the microcode in S2 is taken out.

CPU 13 in microcomputer 10 in FIG.
Consists of an ALU 14, a register 15 and a bus 16 controlled by the microcode output of the ROM 11. FIG. 5 shows a detailed block diagram of the ALU and shift circuit S and the associated buses, and FIG. 6 shows the ROM 11 and its microinstruction output bit 18. The control of the ALU and the calls to the bus are fully defined by these microinstructions or bits 18 identified in FIG. 6 for the illustrative embodiment. Entry point circuit 21
The 8-bit micro address appearing on the line μA from
Line 21x going to the X decoder 11x via the multiplexing circuit 11m
2 bit Y appearing on the line 21Y which includes the 6 bit X address appearing in
Including address. The X decoder 11x of this example is a ROM
Select one of the 64 X-rays in the array of 11 ROM bits. The Y decoder 11y 'selects one of the four Y lines in each group (up to 64 groups can be used). Therefore, each 8 bits appearing on line μA
For addresses, a different "microinstruction" is the output appearing on line 18. Micro-instructions can be any number of active lines 1
8 but usually only a few lines 1
8 combinations are active for a given microinstruction. Each line 18 goes to buffer 11b to drive a higher capacitance load than the array output allowed by the Y line itself,
And clock gates and other logic as required. All microinstruction bits (control line 18) in FIG. 6 and elsewhere in the present invention are designated with a prefix "#". Some bits are active low and therefore bear a negative sign such as # -OtST. In the microinstruction bit of FIG. 6, the character "t" represents "to", so # -OtST is "O bus to ST.
"To register", ie the gate connecting the O-bus to the status register is activated by this bit.
The 8-bit jump address that appears on line 23 is #JmpAddr
While represented by (7-0), the 3-bit interlace control appearing on the line 24 used for the designated address is #JmpCntl.
It is represented by (2-0). These 11 bits are used by the entry point circuit 21 to create the next micro address μA. #OPCH to #ONE in FIG. 6
Up to tAH, a total of 20 bits 18 control the call from bus 16 to register 15. In these #
Low Write0 and #Low Write1 Pseudo micro instruction OtP
Decoded to create CL, OtMAL as well as OtSP. Bits #ONEtAL and #ONEtAH
Put a "1" on the AL or AH bus and put a B register address 0001 or PF page address 0100 (hex) in the microinstruction. The default for all 0s appearing in AL and AH is the A register address in the register file. Register 15
And the connection between bus 16 and bus 16 is described in detail below. #
The MEMCNT bit is a "memory continue" control for long memory cycles. RAM 12 is called for reading or writing in one state time, but RO
Calls to peripherals in microcode or PF from M11 use two states, so control line #M
EMCNT is active in the first state of every long memory cycle as seen in FIG. #MEM
The CNT is used to generate several other control signals and always identifies the first or second state of a long memory cycle. The #MEM bit represents a memory cycle,
It is active whenever ROM 11, RAM 12, or external memory is called. Since the #WR bit is a write command, the memory write condition exists when #MEM and #WR are active, but the memory read condition exists when #MEM is active and #WR is inactive. # -LST
The signal is a load status command for ALU operation.
The status register ST is also loaded from the O bus by the # -LST command. ALU is #ShiftCntl (3
0), #AluCntl (3-0) and 9 bits controlled by #ABL. These controls are described in detail below.

Since the microinstruction bits 18 are structurally arranged in the order in which they are used in the strip and not necessarily in the order shown in FIG. 6, the control bit 18 is generated as close as possible to the point where it is used in the strip.

As shown in FIG. 6, #P is used for microcode output.
Included are microcode # μC bits such as CHtP ', which are in the second state of macrocode fetching (fourth state).
A buffer circuit 11 for delaying one state to create the bits required for the microcode in S2 ') of FIG.
b '. These bits are from buffer 11b 'appearing on line 18b and are similar to some of bits 18. The second state of macrocode fetch is almost always one of the following three things: (1) The opcode portion of the approaching instruction is loaded into IR and PCH is incremented; (2) the address byte is in the next state. While loaded into MD for use via AH or AL and PCH is incremented; or (3) Byte called from ROM 11 via MD is loaded into T register for use in later machine state and PCH is Incremented.

To increment the PCH, the ALU and micro-carry controls are created as described below. Buffer 11
Only a few active # μC bits are required from b'because virtually all of bits 18 are 0 to define the required microcode. These operations include, for example, IAQ-0, IAQ-1 sets, and BtoPPL-0, BtoPPL-1 and ItoAA.
-0, ItoA-1, depending on the microinstruction sequence of FIG. 8 or Table C, and Japanese patent application
No. 60848 ”.

ROM output buffer 11 receiving lines 23 and 24
The portion b is latched to hold the micro address μA in one state time whenever the CROM 'command is asserted. Therefore, the next address made from lines 23, 24 in S1 is the S to be used at the beginning of S3.
Holds until the end of 2. The GROM 'command is made up of microcode bits #MEMCNT and AH' bits.

FIG. 6 also shows the 8-bit constant output #C (7-0) and the #CtN command which adds an 8-bit constant to the N bus.
This constant function is not used for the microinstructions in Table B,
It may be used instead of immediate ejection for offsets and the like.

Microinstruction control of calls to register 15, bus 16 and ALU 14 is assigned to Texas Instruments, incorporated herein by reference,
It is described in Japanese Patent Application No. 57-60848.

As an example of ALU operation, addition by zero carry (#AluCntl and #Shift Cntl are all zero)
Causes the ALU to calculate the sum of the contents of the P and N buses. To calculate the difference between the contents of the P and N buses, use #
AluCntl = 1111 and # ShiftCntl = 0001. Borrowing is not desirable, so this subtraction must carry a "1". As a complete example, the following 2
Micro-instructions read the current byte addressed by the PCL and PCH registers and write it to T /
Put in MAH register and increment PCL and PCH registers: 1st microinstruction cycle (macrocode fetch S2 of Figure 4a): Second microinstruction cycle (microcode created by the # μC bit of the microcycle before S2 'in Figure 4a): It is noted that the increment was done in the first cycle by using the ALU carry "1". The second cycle is the micro-carry bit (μ
Only if C) is "1" did the high byte of the program counter on the PCH be incremented. During the second cycle, only 6 positive bits 18 are made by # μC. Table C shows another example of details of microinstruction status.

From FIG. 7, the group decode circuit 27 and the memory control circuit 28 have the address buses AH 'and AL'.
And the three microcode bits #MEM of FIG.
A constant control signal is generated in response to #MEMCNT, #WR and a clock.

Ports A, B, C or D are selected by signals GA, GB, GC or GD in response to addresses AH 'and AL', respectively. As can be seen in Figure 2a, the data for ports A, B, C or D are located at locations 0104, 010.
Since it is at 6, 0108 and 010A (even addresses), one of these ports is activated by one of these addresses, allowing calls to the MD bus. C
Or, to set the direction of the D port, the least significant address bit-0 of AL 'is also used to call the direction register portion of port C or D (add 1 to 0108 or 010A). A "1" written to the direction register bit sets this bit of the port as an output and a "0" sets this bit as an input.

RAM12 is 0000 to 00 of AL 'and AH'
Called by a GRAM command made by the group decode 27 in response to the 01F (page 0) address, and read or write is selected by the presence or absence of a "RAM write" control WRAM made in the memory control circuit 28 by #WR microcode. To be done.

The ROM 11 has addresses AH 'and AL' of F00.
Selected for macrocode call by GROM from group decode circuit 27 whenever the first cycle of the long memory cycle, which is in the range 0 to FFFF, is shown as in FIGS. 4 and 4a. To be done. The GROM activates the latch 11c in the Y decode and output circuit 11Y to load an 8-bit microcode word from the ROM 11 onto the MD bus. The MUXCNTL command input of multiplexer 11m causes the X address decoder 11X to use the X address from the AH 'and AL' buses when it is high, and not from the μA bus when MUXCNTL is low.

The ROM 11 is used except when the conditions of MEMCNT and GROM occur, that is, addresses F000 to FFFF.
G for all machine states except during the first state (macrocode fetch) of up to 1 long memory cycle
Selected for microcode calls by ROM '. ΜA address and GRO through multiplexer 11m
X-decoder 11X, which receives M '', activates decoder / output circuit 11Y 'to provide multi-bit microinstruction output on line 18 during all machine cycles except macrocode fetch. The MUXCNTL command goes high during S2 of FIG. 4a, causing the AL 'and AH' addresses to be sent to the decoder 11x instead of .mu.A.

The circuit of FIG. 7 shows the load / address command LADDDR.
Is also created and the addresses of AH and AL are loaded into the address buffer 19. This occurs in all machine states except the second state of long memory cycles. The OtM command is created in accordance with the conditions described in Japanese Patent Application “Japanese Patent Application No. 57-60848”. Command L for latching microcode output of ROM 11 in latch 11c
ROM is made under the same conditions as GROM and MUXCNTL, but the timing is different. That is, LROM occurs during S2Q4 in FIG. 4a. In another embodiment, the "ROM write" command WROM is
It is provided if the part of the memory 11 is of the read / write type as will be described.

The microstructure of the CPU, including the entry point circuit 21 of the ROM 11 and the microcode output, is designed to nominate the various subfields of the contents of the IR, Japanese patent application "JP-A-57-60848".
Run the appropriate sequence of microcodes in Table B, as found in the logic flow diagrams of FIGS. 8a through 8j, which are similar to the logic flow diagram of FIG. FIG. 9 shows a map of typical opcodes, one example of which is Table A. Some examples of microcode states are shown in Table C.

The IR subfield is nominated by IR (for example, IAQ-
2) loaded and then done by one of the first microinstructions. The nomination is then done by a microinstruction that includes one of the following to reload the IR. IR if nomination is not required while executing the given opcode
Is used as a general purpose 8-bit register.

The control flow between microinstructions is determined by how the next microinstruction address .mu.A for the ROM 11 is created by the entry point circuit in both conditional branching and unconditional branching.

The microinstructions stored in the combination ROM 11 of the chip have the characteristic that they are microprogrammed horizontally in that each microinstruction indicates the address at which the next microinstruction should be placed. The next micro address μA is the two fields of the CROM output 18 (lines 23 and 2).
4): (1) #Jump Addr (7-0), 8-bit field indicating the base address of ROM 11; and (2) #Jmp Cntl (2-0), #Jump Addr (7-). A 3-bit code indicating one of eight nominations offset from the address of 0).

# If Jump Cntl (2-0) = "000", then # Jump Ad
The dr field is simply used directly as the address of the next microinstruction. For example, in Figure 8b, this is B
It is a continuation from to PPL-0 to B to PPL-3. #
If Jump Cntl (2-0) is non-zero, it indicates which control line replaces the low order bit of #Jump Anddr and therefore makes the next micro address μA. This method is called Nomination in Japanese Patent Application No. 57-60848 and is easily implemented in MOS technology.

In the device of this example, a maximum of 256 micro-instructions are possible, each of which is a multi-bit word (output 1
8), but less than about 150 microinstructions total to execute the instruction set of Table A of this example, thus less than 150 8-byte wide words in ROM are used. Each of these is capable of microinstruction control 64.
Although it is a 64-bit word containing eight outputs 18, there may be fewer bits actually used. Additional microcode functionality for this device (new macro instructions)
Are added by executing a subset of the standard Table A instruction set, or exchanging it entirely.
The functions performed can be extended by using more microcode in ROM 11.

Referring to FIG. 2a, the main operating mode of the microcomputer shown in FIG.
And a microcomputer mode contained in RAM 12. The device is initialized or reset by the RST to be in microcomputer mode, that is, zeros are placed in bits 7 and 6 of I / O control register 0100. In this mode, only 5 or 6 bytes of the peripheral file FF are used and the remaining 250 have no function. Peripheral file register numbers P0, P4, etc., and hexadecimal addresses for the microcomputer mode are shown in FIG. 2a. Port A is for input only and port B is for output only, while ports C and D are used for either output or input. That is, registers P9 and P11 direct the data at ports C and D, but such control registers are not needed at ports A and B because they are unconditionally inputs or outputs. The port A, B, C, D data registers are contained within the I / O buffer and are also available on the AL bus at addresses 04, 06 and 0A (hex) and
Called by the MD Bus using Page One on the H Bus, 00000001. Similarly, AL addresses 09 and 0B call the control registers contained in the buffers for port C and port D. A "0" in the control register bit sets the port for input,
"1" sets the output port. Addresses applied to AL and AH that are in unused areas do not produce significant results, so the ROM 11 program is, of course, written to avoid these addresses.

In Figure 10a, an apparatus is shown including an 8-digit display 13-1 and a keyboard matrix 31-2, which uses the device of Figure 1 in its microcomputer mode. The C port is used for the display segment and the B port output drives the columns of the display 13-1 and the columns of the keyboard matrix 13-2, which are described in, for example, U.S. Pat. No. 3,988,604.
No. 3, 921, 142 or 4, 158, 43
As shown in No. 1. A row of keyboard matrix 13-2 is added to the A port input. 8 × 8 =
64 key matrices are possible, but less than 64 are typically required. Other activators and sensors, such as those used in the microwave oven controller of Van Bavel, U.S. Pat. No. 4,158,431, assigned to Texas Instruments, have a D port as input or output. May be connected to.

In the peripheral expansion mode of the memory map of FIG. 2b, peripheral pages 0100 to 01FF, or 256 bytes, are available for off-chip calls. The C port is used as a multiple 8-bit address / data bus, and the 4 bits of the B bus are control lines ALATCH, R / W,
Dedicated as ENABLE and CLOCK OUT, these are as shown in the device of Figure 10b. This device uses the microcomputer 10 of FIG. 1 as the main processor in a scheme with two other adjunct processors. One is a video display processor 13f as described in U.S. Pat. No. 4,243,984 issued to Guttag et al., Assigned to Texas Instruments. The other is a general purpose interface bus adapter chip 13g that interfaces the chip 10 with a standard IEEE 488 bus 13h. Chip 10 creates an 8-bit address for port C which is latched in 8-bit latch 13i by address latch signal ALATCH on port B4, which address is then applied to chip 13f and when the enable signal on port B6 becomes active. It is available on the address bus 13j for 13g. Chips 13f and 13
g is synchronized with chip 10 by the clock output of port B7. The C port is then used for data in and out of chip 10, chip 13f and chip 13g, depending on the read / write control R / W of port B5.
Thus, chips 13f and 13g are made to respond to addresses 0108, 0109 and 010A to 01FF of buses AL and AH. Of course, the AH bus of FIG. 1 always contains 01 in this mode for off-chip calls. In this peripheral expansion mode,
Since the A port acts as an input and the D port acts as an input or output, other functions are performed except calling chips 13f and 13g. Actuators and sensors, as shown for example in Figure 10a, or keyboard matrices are used here as well.

The fully expanded mode of FIGS. 2c and 10c is shown in FIG.
It provides an 8-bit address output on the C port as in Figure b and another address byte on the D port that can address, for example, the memory chip 13k. Full extension mode provides a complete 64K (2 bytes-C and D ports) off-chip address range. Address 010
8 to FFFF are available for off-chip calling. As mentioned above, at address 0106, port B provides memory control and bits B4, B5, B6, B
7 clock operation. Memory chip 13k can be, for example, a 32K device, and the lower byte address from the C port is latched at 13i, while the upper byte goes directly to chip 13k by line 13m. Data bus 13n going to C port is chip 13f, 13g
And 13k. Therefore, the 10c
The device shown has a much larger program capacity than the device of FIG. 10b, but the D port is not available for other I / O. However, the keyboard matrix 13-2 has the remaining 4 bits (address 01
06, bits 0-3) and the A port.

A microcomputer 10 made in accordance with the present invention is a U.S. Pat. No. 4,158,431 issued to Van Barbell et al. Assigned to Texas Instruments.
May include self-test procedures as indicated in the issue. According to the procedure of Japanese Patent No. 4,158,431, all the display characters 13-1 and the keys 13-2 in FIG. 10 and all the I / O devices of the port D are prepared in the ROM 11
Consists of testing under the control of a series of micro-instructions. This self-test procedure proves that all the external elements of the device are working and gives some indication that the chip 10 itself is fully functional, but this is not a thorough check. However, functional tests must be performed before connecting to such devices. For example, to test the contents of ROM 11 after manufacture (before delivery to the customer, or by a custom as a receiving material inspection), the entire contents of the ROM are read one word at a time, and each word is labeled with the desired bit pattern. The comparison has been done so far. Microcomputer devices that permit such testing are all described in US Pat. No. 3,921,142 issued to John D. Bryant et al. It is disclosed and claimed in U.S. Pat. No. 4,024,386 issued to ERCaudel as well as Joseph H. Raymond. However, such tests require the test machine to store the entire ROM code, i.e. 2048 bytes or 4096 bytes, and also require a different check code for each different ROM code. In addition, this test requires at least one transfer between the test machine and the device under test for each type of ROM. These factors make the test unduly lengthy, require extensive test data or software, and can overload the test machine.
Run out of space.

As shown in Japanese Patent Application No. Sho 57-60848 assigned to Texas Instruments, the microcomputer 10 has a 2-byte macro code fixed in the ROM 11 at the time of manufacture and uses the remaining macro code for testing. The test methods described below can be used. This 2-byte code is different for each ROM code or program and represents some function of all other bytes encoded in ROM. For example it is
It could be the LSB of the sum of all the other bits in ROM, or some other function that preferably provides a multiple check of all bits. This 2-byte code is called a cyclic redundancy code or CRC and is a function of each bit of data used to create it.
It is a 6-bit value. CRC is ROM except CRC itself
Is calculated using each byte of the macro code in.

The program for this test is loaded into RAM 12 of chip 10, but chip 10 is in one of the extended modes (FIGS. 2b or 2c) depending on the sequence of move double MOVD or move MOV instructions. using this method,
All test codes are stored in RAM1, then MOV
The instruction returns the microcomputer 10 to the single chip mode of Figure 2a. All bytes in ROM are ALU
If the function is passed, the test ends. The program then defines port C as an output and outputs a code externally indicating that the computation is complete, so the test machine will have C port and D
You will be warned to look for the 2-byte result of the port. The original check code is compared with the calculated value to give a comparison output. Approximately 890,000 machine states are required by the microcomputer 10 executing this test program, all of which are internal and the test machine does not need to store a unique code and is off. Chip calls are not required for most of the test.

However, according to one embodiment of the invention, additional test equipment is available. The microcode itself is recalled one byte at a time and checked against a check code stored in ROM 11 or an externally stored representation of the microcode. For this purpose, the microcode part of the ROM 11 is written to a peripheral file, for example by a "MOV% n, Pn" instruction, or written to the A register by "MOV% n, A", which causes it to operate internally. And it is called in the decoder 11y, the latch 11c and the MD bus so as to be externally written by the "MOVP A, Pn" instruction. Fetch immediate microcode is typically used to fetch, for example, an operand address or constant, but is used to add a byte of microcode from ROM 11 to one of output ports B, C, or D. . Order "MOVP% F
F01, P6 "is the following microcode state, that is, I
AQ-0, IAQ-1, IAQ-2, ItoPPL-0,
ItoPPL-1, BtoPPL-0, BtoPPL-1, B
Performing toPPL-3, STP-0, STAL-2, and then returning to IAQ-0, this sequence can be found in FIG. 8 and in the table of Japanese Patent Application No. 57-60845. While in the ItoPPL-0 state (corresponding to S2 in FIG. 4a), FF01 (the macrocode address in FIG. 2 is one byte in one 8 bytes in the microcode state in Table B or FIG. 8). ) Microcode bytes in ALU processing, off-chip writing,
Alternatively, it is called for writing to the RAM 12. Since both the microcode and the macrocode are checked by using the above test program, the CRC is calculated in consideration of all bytes of the microcode part and the macrocode part of the ROM 11. The method operates as described above and the load instruction retrieves all bytes of ROM 11 containing the microcode.

This method of testing microcomputer chips is advantageous in development and is important in high volume manufacturing operations, which also suffer from several drawbacks. The number of external pins is limited and the data available on the pins is limited by the instruction set and internal circuitry. Therefore, in testing packaged devices, hundreds of internal nodes and signals are not available externally. Internal probing is meticulous and extremely time consuming. Therefore, it was necessary to provide a test machine that was cycled with virtually every possible operation of the device to check for defects during manufacturing. The test equipment for the LSI chips is of course controlled by a computer, but this kind of testing is not only too time consuming to execute, but also because all the different ROM codes for each customer require different test sequences. Expenses are prohibitively expensive. Exactly,
Such tests were incomplete because the execution of certain instruction sequences was data dependent and all possible combinations could never or even be imagined. In addition, time and program memory limits on the test machine impose actual constraints.

Memory 1 to replace "ROM" programmed during manufacturing
Since 1 can be of the read / write type with static RAM cells, both macrocode and microcode are loaded from outside the chip. From FIG. 6a, memory 1
No. 1 is the same as before except that it includes a "ROM write" control WROM and that the decoder 11y is an input / output circuit as well as an output circuit. Group decode circuit 27 and memory control circuit 28 produce a WROM command when a GROM AND #WR occurs. A portion of memory 11 must remain permanently programmed so that there is macro and microcode to do the task of loading the rest of memory. To this end, the reset microcode of FIG. 8e is fixed in the permanent ROM portion of memory 11 along with the microcode necessary to perform long reads from peripheral file PF and long writes to memory 11. The reset sequence is thus supplemented by adding groups of microcodes, for example reading port A and writing port A data to memory 11, until all of the read / write addresses of memory 11 have been loaded. The microcode addresses for this function and reset are varied so that they are all at the FFFF end of the array or elsewhere convenient for assembly and programming. Memory 11 is first loaded, and after the tasks of the loaded program are completed, memory 1
The entire read / write portion 11w of one will probably be reloaded with new microcode as well as macrocode, or only that portion that has been exchanged for a new task.
Permanently programmed portion 11P contains all macro and microcode that requires this update task, as well as a reset or initial loading job.

As described in Japanese Patent Application No. 57-60848, or as shown in FIGS. 8a to 8j, the execution of microinstructions is performed by the first
Macro interrupt pin INT in Figure or INT- in Figure 8e
It is interrupted by a micro-interrupt unit that participates in the functionality of the 0 through INT-5 micro-instructions and is entirely separate from it. From FIG. 6b, the micro-interrupt signal μI generated by the micro-interrupt control latch 36 causes the micro-address present in SIQ2 of FIG. 4 to be saved in the 8-bit latch 31 and also the micro-vector address (eg 60 or 01100000). Is applied to the decoder of the ROM 11 under the control of the multiplexer 32 via the line μA. The vector address begins the sequence of microinstructions as shown in Table D as follows: (a) saves all outstanding registers, addresses, and status bits (b) RF register (in this example Then, extract the value of timer 1 from R63) (c) Decrement the value of timer 1 and write it back to RF (R63) (d) If the value of timer 1 is equal to zero, interrupt flag 1
(R62, bit 0) is set. (E) If timer 2 and timer 3 are included, continue (b) to (d). (F) Return to a pending microinstruction sequence (a). Only 0 microinstructions save MD bus for PCL, PCH, AML, T / M
This is because the AH, IR, ST and SP registers are not used or changed in the sequence. Alternatively, the data on the MD bus is saved on the stack by push and hop microinstructions. status·
Register ST need not be stored by a microinstruction because the #LST bit is not claimed in Table D.

Instead of using the RF register as a flag, another bit of the status register ST is used. By the way, hardware latches are used to make macro interrupt enablement. In the above embodiment, a microinstruction must be added to the IAW sequence to test the microinterrupt flag (R62, bit 0) at the beginning of execution of each new macroinstruction before testing the macrointerrupt. A bit test is performed before IAQ-0 to check the micro interrupt flag and to perform any desired function by writing a new value to the timer register R63 etc. and using macrocode, eg, a trap routine. To be done. See IAQ-0a and IAQ-0b in Table D. If more than one timer is used, all flags will be polled.

The number of timers running during a given task can be variable. One of the RF registers may be specified to determine the number of another timer upon activation, the Dth
The table microcode is written to loop through the multiple times set by this register. further,
The interval between micro interrupts can be made variable with one or two PF registers, such as P2 and P3, which define the count chain. In this way (using two such registers), the time between microinterrupts can be varied over a range of 2 ¹⁶ under microcode control.

The effect of a micro interrupt device on an assembly level programmer writing macro code is exactly the same as a hardware timer expiring. The microprogram need only know that the CPU is time-shared to run the timer. The microinterrupt device of FIG. 6b acts as a one-level microsubroutine, and of course the timer can be used for many other purposes.

The microcomputer described in detail herein is
It is in the form of an N-channel silicon gate integrated circuit on a single silicon chip. However, the features of the present invention are of course also used in devices made by other processes such as metal gates, P-channels, CMOS, silicon-on-sapphire, and the like. Further, the combination memory 11 is a fixed program type mask programmable RO
Described as M, but of course an electrically programmed RO
M or electrically erasable ROM is used. ROM 11 is referred to as the program memory and RAM 12 is referred to as the data memory, which are the main functions in many applications. However, it goes without saying that the "data" from ROM 11 is used in some algorithm ("data" is a constant, etc.) and the device can execute macro instruction code from RAM 12 and the macro code or program block is external. It is downloaded to and executed from RAM 12 from a tape or disk drive, or from a telephone combiner, for example.
In addition, additional control lines and functions such as READY, HOLD, bus status code, etc. are used in devices featuring the present invention.

Although the invention has been described with reference to illustrative embodiments,
The explanation is not meant to be interpreted in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons of ordinary skill in the art in view of the present description. Therefore, the appended claims are intended to cover all such variations or embodiments that fall within the true scope of the invention.

In addition to the above disclosure, the following items are further disclosed.

(1) Arithmetic / logical unit, a plurality of registers for storing data and memory address, bus device for calling arithmetic / logical unit and register, and arithmetic / logical unit, register and bus device for instruction word In a microcomputer device including a semiconductor integrated circuit having a control device for generating an operation and a command for controlling its calling, the control device includes an address input device, a first multi-bit output and a second multi-bit output.
Including a combined memory device with multi-bit output,
An address device for adding a first address and a second address to the address input device, each first address starting an operation selected by a command word, and each second address at least one for defining a plurality of the commands; Creating a microcode output word of the microcomputer device.

(2) ALU that performs arithmetic / logical operations with operands supplied to its inputs under the control of microcode bits
A plurality of data and address registers, a data / address bus device for calling the ALU and registers under the control of microcode bits, a read / write microcode memory device for storing said microcode, and a device A device for loading the memory device from an external source of the device, all of the elements being formed in a single semiconductor integrated circuit, and the bus device and the register being much larger than the number of bits of the microcode word. The microcomputer device, characterized in that it includes fewer bits in

(3) A microcomputer device formed in a single semiconductor integrated circuit having an internal self-test function of microcode, which calls an ALU having a plurality of address / data registers and ALU registers and input / output. A CPU having a bus device, a controller for determining the operation of the CPU, including a device for generating a plurality of different microcode words each having a plurality of bits; A storage device in the integrated circuit for storing the inspection code representation, and the CPU for calling the plurality of microcode words with a set smaller than the set of bits, the plurality of all microcodes If an ordering operation is executed with all the bits in, and the result of such an operation corresponds to the inspection code display, An apparatus for producing one output and producing a second output if the result does not correspond to the inspection code display.

(4) Arithmetic / logical unit, a plurality of registers for storing data and memory address, bus device for calling arithmetic / logical unit and register, and arithmetic / logical unit, bus device and register according to instruction word A controller that creates a sequence of command sets that control operation,
In a microcomputer device including both a micro interrupt and a macro interrupt including a semiconductor integrated circuit having all of the above in an integrated circuit, a controller calls a sequence of command words and the sequence of command sets according to each command word. An instruction for interrupting any of the sequences of the instruction set and performing an operation by an arithmetic / logic unit not defined by an instruction while saving data in the registers and bus devices A microinterruption routine for the instruction word using the alternate sequence of the instruction set and interrupting said sequence of instruction words and executing a set of microinterruption routines to return to such a sequence. And then The microcomputer device, characterized in that it comprises a device to return to the written sequence Ri.

[Brief description of drawings]

FIGS. 1a and 1b are block diagrams of a MOS / LSI microcomputer chip that includes a CPU, ROM and RAM and utilizes the features of the present invention. FIG.
Memory map of the logical address space for the illustrated microcomputer, FIGS. 2a-2c are detailed memory maps similar to FIG. 2 for peripheral pages for microcomputer mode and extended mode, FIG. Shows the structural layout of various parts of the device
FIG. 4a is an enlarged plan view of a semiconductor chip including the microcomputer of FIG. 4, FIGS. 4-1 and 4-2 are timing diagrams showing voltage-time relationships for various events of operation of the apparatus of FIG. Is a timing diagram similar to FIG. 4 for a macrocode call cycle; FIGS. 5a and 5b are detailed electrical diagrams of a CPU including the ALU, shift circuit S, registers and buses in the microcomputer of FIG.
6-1 and 6-2, 6a-1 and 6a-
2 and 6b are detailed electrical diagrams of the combination user ROM and control ROM used in the microcomputer of FIG. 1, and FIG. 7 is an electrical diagram of the group decode circuit and memory circuit of the device of FIG. , Figures 8a through 8
Figure j is a logic flow diagram for microinstruction execution of Tables B and C in the apparatus of Figure 1, Figure 9 is a macroinstruction map for the example instruction set of Table A, Figures 10a to 10c-. FIG. 2 is an electrical diagram of the apparatus using the microcomputer of FIG. 1, and FIG. 10d is a timing diagram of the apparatus of FIGS. 10a through 10c. Explanation of symbols 10 ... Microcomputer chip, 11 ... Combination ROM, 12 ... RAM, 13 ... CPU, 14 ...
ALU, 15 ... Register, 16 ... Bus, 11x ...
Combination X decoding, 11y ... Microcode Y decoding, 11y '... Microcode Y decoding, 11b ...
… Microcode output buffer, 11c… Latch, 2
1 ... Entry point, 27 ... Group decode, 28 ... Memory control, 29 ... Interrupt control, 33 ...
… Clock generator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number 280588 (32) Priority date July 2, 1981 (33) Priority claim country United States (US) Judgment No. 4-8105 (72) Inventor Jeffrey Dee ． 8710 Neri, Houston, Texas, Berray, USA 8756 (56) Reference JP-A-56-58197 (JP, A) JP-A-53-148254 (JP, A)

Claims (1)

[Claims] 1. A microcomputer device formed in a single semiconductor integrated circuit having an internal self-test function for a microcode word, comprising external data input / output means, an arithmetic logic unit, a plurality of addresses and data. A center having a register and the input / output means, the arithmetic logic unit, and a bus means for connecting the register for data transfer, wherein the input / output means, the arithmetic logic unit, the register and the bus means have a control signal input. A processing unit and means for defining the operation of the central processing unit and for generating a plurality of different microcode words each having a plurality of control bits, controlling the input / output means, the arithmetic logic unit, the registers and the bus means. Control means connected to the signal input, and a plurality of markers to be read in order to perform the internal self-test function. A storage device for storing a check code representation of all control bits of the black code word, and a plurality of microcode words to be read in order to execute the internal self-test function according to a set of the plurality of control bits. Accessing, accumulating all control bits of the read microcode words, and outputting a first output to the external data input / output means when the accumulation result corresponds to the check code display. A device for outputting a second output when not corresponding, and