JPH0394337A - Microcomputer device - Google Patents

Abstract

PURPOSE: To simplify an internal self-testing function by calling a microcode itself by one byte, and inspecting the microcode for display stored outside a check code stored in an ROM or the microcode. CONSTITUTION: A microcomputer chip 10 is composed of a combination ROM 11, RAM 12, entry point 21, group decode circuit 27, memory control circuit 28, interruption control circuit 29, and clock generator 33. The inspection code display of all the bits of all the plural microcode words is stored in the ROM 11. Then, access to a plurality of microcode words in fewer sets than plural control bits is performed, the cumulative sequence arithmetic operation of all the control bits of all the plural microwords is operated, and when the cumulative arithmetic results are equivalent to the inspection code display, a first output is generated, and otherwise a second output is generated. Thus, the simple internal self-testing function can be obtained.

Description

[Detailed description of the invention]

This invention relates to features used in integrated semiconductor devices and apparatus, particularly electronic digital processing apparatus in the form of single-chip microprocessors or microcomputers. Microprocessor devices include rMOs, as shown in U.S. Pat. No. 3,757,306 issued to Gray W. Boone and assigned to Texas Instruments.
/LS Usually assembled by IJ technology, tit
A central processing unit, or CPU, for a digital processor included in a semiconductor integrated circuit. Boone's patent is
Parallel A, all interconnected using bidirectional parallel buses
Chip's 8-bit CPU including LU, data and address registers, instruction registers, and control decoder
It shows. Gray W. Boone and Michael J. Cochran
U.S. Pat. No. 4,074,351 issued to Texas Instruments, Inc.
1 shows a single-chip "microcomputer" type device containing a 4-bit parallel ALU and its control circuitry, with M and RAM. A microprocessor typically refers to a device that uses external memory for program and data storage, whereas a microcomputer refers to a device that includes on-chip ROM and RAM for program and data storage. However, the use of both terms is interchangeable and is not intended to be limiting on the present invention. U.S. Patent Nos. 3,757,306 and 4,074,
Since 1971, when No. 351 was originally filed, numerous improvements have been made to microprocessors and microcomputers that have increased the speed and capability of these devices, lowered their manufacturing costs, and allowed them to fit more circuitry into less space. In other words, the size of the chip has been further reduced. Improved photolithography has led to narrower linewidths and higher resolution, resulting in greater circuit density, but improvements in circuitry and equipment are also contributing to the goal of increasing performance in smaller chips. Some of these improvements in microprocessors are disclosed in Japanese Patent Application No. 1984-60848. A principal object of the present invention is to provide an improved microcomputer or microprocessor device that is adapted for widespread use, yet is made to facilitate inexpensive manufacture and minimize programming costs. be. Another object is to provide a microcomputer device that is programmed in a standard chip format and is more versatile for a variety of uses. In particular, one object is to provide a microcomputer device in which the amount of microcoding used for instruction execution can be varied without changing any masks in the manufacturing process other than the gate mask. According to one embodiment of the present invention, the "user JROM" is a microcomputer combined with the "control JROM".
Device provided. User ROM typically contains programs written in macrocode, and control ROM typically contains microcode used to execute the macrocode. This combinational ROM, which contains both macrocode and microcode, is addressed in two ways: first, the program counter and memory address register used to access the logical address space via the address bus address the combinational ROM. The combinational ROM can then be accessed by the entry point circuitry used to create the control ROM address. In one form, the Y decoder is isolated because the macrocode output from the combinational ROM is one byte wide, while the microcode output is approximately six to eight bytes or more byte wide. In memory access cycles to the combinational ROM address space, control is made to select either macrocode or microcode output, eg, control is made from the current microcode output. By combining macrocode and microcode into the 111-ROM, the amount of microcoding for a particular device is selected for optimal execution speed, customer programming reduction, security, or other factors. The amount of microcode can vary from standard microinstructions that are always set to virtually 100% microcode, ie, many compound microinstructions of a Daifuku-enhanced instruction set. The combined macrocode and microcode memory can be RAM instead of ROM, so the user can use it from an external disk, tape or ROM, or from a telephone line to define the functionality of the device according to his immediate job. This allows you to download microcode along with macrocode. That is, different sets of instructions are used in different parts of the job. The terminal is microprogrammed at one point to perform floating point or BCD operations, and then microprogrammed at another point, for example, to perform dual type transfer instructions for valid data transfers. An important feature of one embodiment of the present invention is that the microcode is called in byte-wide portions by the memory data bus for ALU operations or external transfers. That is, microcode stored in combinational ROM is added to ALU temporary registers or written to external ports one byte at a time. This is extremely useful for testing purposes. Also, the only way to test microcode is to run all possible functions to know if you are getting the correct results. The features believed to be novel of the invention are pointed out in the following claims. However, the invention itself, together with other features and advantages, will be best understood by reading the detailed description below with reference to the accompanying drawings. Referring now to FIG. 1, a microcomputer chip 10 is shown employing features according to one embodiment of the present invention. Chip 10 has approximately 5.08 mm (200 wits) on each side mounted in a standard 40 pin package.
) This is a MOS/LSI type semiconductor integrated circuit including the following silicon bars. Included within the chip 10 is a complete digital processor with a combined user ROM and control ROM 11 according to the invention. This ROM
That is, read-only memory 11 is used both for program storage and for microcode storage. RAM or read/write memory 12 is used for data storage. The chip includes an arithmetic logic unit or ALU 14 and its working registers 15 and bus 16, as well as microinstructions. i.e. ROM1 1 which produces a control signal on line 18
It includes a CPU 13 consisting of control ROM outputs. CPU 13 addresses ROMI 1 and RAMi 2 by three lines in control line 18, as well as by three buses: memory data bus MD, high address bus AH, and low address bus AL. Additionally, microaddress bus μA calls ROM11 for microcode fetches. The chip's communication with external devices is activated by a control circuit called by the MD bus and responsive to the AH and AL addresses. 4 memory mapped 8-bit ports A, BSC and D. In this example, the MD%AH and AL buses are 8 bits wide, as are ALU 14, registers 15, and ports, but of course the ideas described here can be applied to 4-bit, 16-bit, or 32-bit devices, for example. Applicable. The register 15 in the CPU 13 includes an instruction register IR.
, Status ◆Register T/MAR, two 8-bit
It includes a 16-bit program counter divided into registers PCH and PCL (program counter high and low), stack pointer SP1 and memory address low register MAL, etc. The address buffer 19 is . Address - Generates true and complement address signals appearing on buses AH' and AL' from buses AH and AL. Operands are mostly temporary registers 15 combined with CPU 13
Acts as a register file RF (RAM
1 2 is stored. Bus 16 interconnects the various registers 15, ALU 14 and the MD, AH' and AL' buses. The ALU 14 always receives a P input from the P bus and an N input from the N bus, and produces an output via a shift circuit S to an output bus, that is, an O bus. A register 15 and an ALU 14 are connected to each of these P, N, and O buses 16.
In addition, calls to the MDSAH and AL buses are controlled by control signals 1 from the microcode, ie, ROM 11.
8. The microcomputer chip 10 is R O M11
It operates on 8-bit macro instruction words which are stored in the instruction register IR and transferred one word at a time to the instruction register IR. C.P.
One of the many possible examples of macroinstruction sets executed in U13 is shown in Table A and in the Japanese patent application ``Patent No. 57-6
No. 0848, Table A provides binary machine language instruction words, also known as assembly language or atomic language, as well as binary machine language opcodes (which have an object expressed in hexadecimal). In addition, it also gives a code (similar to an objective code). The instruction set is described in detail in a booklet published by Texas Instruments in 1981 entitled "TMS7000 Series of 8-Bit Microcomputers," which also describes the addressing modes. The obcode and one or more address bytes are typically
Used to execute instructions. The instruction word or obcode held in the IR is stored in the address circuit 1 for the ROM 11.
Microaddress line μ coupled to 1x and 11y'
It is the input of the entry point circuit 21 that creates the 8-bit address appearing in A, and (in this embodiment) ROM1
1 by calling one of the 256 possible addresses for
Table B and Figure 8 or Japanese patent application “Patent 1983-
A control bit or control signal is created that defines one of the microinstructions, such as those shown in '60848'. One macroinstruction in Table A creates a set of microinstructions. A portion of each microinstruction (i.e. a portion of output 18) is used to create the next μA address for the ROM, the microjump address is fed back to the entry point circuit 21 via a line, and the designated control information is It is fed back via line 24. That is, a set of microinstructions is created from each macroinstruction loaded into the IR, and the sequence also depends on the status bits in the status register ST and other conditions. The address for the operand, if required, is included in the macrocode word from ROM 11 with the opcode and transferred to MAL or MAR while the opcode is kept in the IR during this sequence of microcode states. Each address applied to combinational ROM 1 1 produces a microcode output 18 via Y-decode 11y' or a memory data bus M via Y-decode 11y.
Create macro output leading to D. It is not possible for the CPU to call both macrocode and microcode in the same machine state. A map of the logical address space for the microcomputer of FIG. 1 is shown in FIG. This example uses 8 bits of A to give a 16 bit address.
Since H address and AL address are used, 2
16 or 65,536 bytes are obtained in this space (often referred to as "KJ-1,024 r 6 4
KJ byte). Addresses are indicated by four hexadecimal digits, from the first address oooo to the final address F.
It spans FFF. In this description, memory addresses are given in hexadecimal unless otherwise specified. A page is 28 or 256 bytes, ie all addresses in a page are defined by AL and the page is selected by AH. The microcomputer 10 has a page “0” (address ooo) for the register file RF in the RAM 12.
o to OOFF) to "1" for the peripheral file PF.
page (address 0100 to OIFF), as well as combinational program and microcode memory ROM.
From FO page to FF page for 11 (address FO
OO to FFFF). Macro code is 8
In terms of bit width, the microcode in this example is approximately 8 bytes or 64 bits wide, so each address for the microcode occupies 8 bytes in the map of FIG. Therefore, if 256 microinstructions are requested, this will occupy 2048 bytes or 16K bits of ROM11. In the example instruction set, micro address 00 to FF is for microcode (macro address F0
(equivalent to OO to F7FF), remaining address F80
0 to FFFF are used for macro codes. R
The space allocated for F and ROM11 may not be populated depending on the selected sizes of ROM and RAM. Other spaces such as 0200 to EFFF are included in the Japanese patent application “Patent No. 57-6
It is used for enlargement mode as shown in ``Meishu-sho No. 0848''. Although not related to the present invention and therefore not explained in detail here, a microcomputer as shown in FIG.
A control circuit responsive to both AH' and L' addresses and control bit 18 is included to determine how U13 calls the peripheral file PF, which includes external ports, timer/event counters, reset and interrupt functions. ing. I/O at storage location 0100 in Figure 2
and interrupt control registers are loaded directly by the MD bus, which is part of the ALU/register strip, and this register, along with interrupt masks and flags, may contain two memory mode control bits to define memory expansion modes. . Programmable timers and event counters are also included within this peripheral control circuit and are accessed by an MD bus and an 8-bit width advantageously made part of the ALU/register strip. In this peripheral control circuit, a group decode circuit 27 and a memory control circuit 28 input AH' and AL' address bits and three control signals (#MEM, #WR, #
MEMCNT), a control is created to select RO to 111 (microcode or macrocode), RAM 12, ports A, B, C, or D, etc. for calling by the given address. Only one of the three or any one cycle is activated. Two or more interrupt input pins INT are typically provided in addition to the timer interrupt. These INT inputs are connected to interrupt control lines 29 which are also responsive to other conditions on the chip. The reset input RST is used to reset or initialize the microcomputer, which ignores any functions or interrupts. Micro interrupts are
May be included as described below. The peripheral control path provides a selection of operating modes defined by internally loaded bits 7 and 6 of I/O control register 0100. Although the address space of FIG. 2 is configured in a unique way for these modes, the register file address I-space RF is the same for all modes. The modes include (1) the single-chip computer mode of Figure 2a where all memory is on-chip in ROM11 and RAM12; (2) some additional off-chip circuitry or ports B and C. The second called into PF space via
Peripheral expansion mode in figure b: or (3) RF and ROM
11 or the same as in FIG. 2, there is a 3tI class of full expansion mode in FIG. 2C, in which approximately 61 Kbytes of off-chip memory is accessed by port B as well as port C. Other modes are as follows:
It can be used as described in "Specification No. 48". The various modes allow a wide range of functions to be implemented in one integrated chip format without changing the configuration, layout or microcode, thus significantly reducing cost. In some modes, the human output buffer 30 is controlled by direction control registers P7, P9, P11 (Figure 2a).
Also, group decoding 27 and memory control circuit 28
Connect ports A, B, C, D to the MD bus as determined by the mode controller via the MD bus. buffer 3
0 includes data registers P6, P8, P10 and P11 that are called by the MD bus. In FIG. 3, the microcomputer of FIG. 1 is shown in chip layout form. Most of the area of chip 10 is occupied by memory, including combinational ROM 11 and RAMI 2 and their respective address data. ROM 11 has a combinatorial X address decoder 11x for microinstructions and microcode.
Rahini separable Y address decoder Ily, 11y'
It is combined with 409 in ROMI 1
Since 12 address bits are used to define one of six 8-bit bytes, the address of ROMI1 requires both the MAL and MAR registers,
That is, it requires address bits from both the AL and AH buses for microinstruction calls. In one example, a microcode call through the μA would require only one page, or 256 locations, called by the 8-bit address, but the additional address space adds up to the width of the μA address. It is added by A 9-bit μA would call 512 locations, for example. The RAM has an X address decoder 12x that selects one of the 32 rows of lines, and a Y address decoder 12y that selects one of the 4 column lines, so it takes only a few minutes to select the RAM. Only 7 bits are required (8 bits if 256 bytes of RAM are used). One main feature is that the number of microcode states can be changed without new chip design, layout, mask-making and production efforts. In this example, ROM
11 has a size of 4096×8, or 32K bits. If fully populated, the number of bits in ROMi 1 used for microcode will be 256 times the number of output lines 18 if an 8-bit microcode address μA is used. Sixty-four output glands 18 are used for the example instruction set in Table A, and 256 microinstruction addresses or states are saved (but not in Tables B and C or in the Japanese Patent Application No. 57-60848).
In one example, less than 150 pieces are required), so the microcode portion of the ROM is 2
It is 56x64 or 16K bits. The remainder is available for macro code (32-16K-16K bits or 2K bytes). ROMII is located next to the strip providing microcode control 18 in the control concentration area of the ALU and register/bus connections, as well as address control and interlaced address lines 2.
It fits right next to the entry point circuit 21 which requires 3,24. The design is directed towards combinational ROM 11 as the entire control source, rather than using random logic for this purpose, and the layout of Figure 3 reduces the chip area to even smaller space due to the RAM and combinational ROM and their decoding. is dominated by a strip containing a regular array of ALU/register bits, occupied by other control logic. This design method requires changing the microcode and macrocode, and
You can increase the value by changing the ratio of microcode and macrocode in OM11, and
This increases the microprogramming capability, which makes the microcomputer 10 particularly easy to modify. The microcomputer 10 is modified with four stages and mode control. The first step is to change the macro code or program in ROM11, which is of course the most widely implemented variation. The macro code is defined by a single mask in the manufacturing process, as shown, for example, in U.S. Pat. . By keeping the microinstruction and macroinstruction sets the same and rewriting the macro code, a wide range of hole-in-the-wall functionality and operations are available. As a second step, the microinstruction set of Table A is supplemented (while retaining the same microinstruction set of Table B and adding some other microinstructions) by making greater use of the microcode storage in ROM 11. . The microcode of ROM1 1 is a single mask under manufacture,
Structurally, it is equally easy to change the macro-instruction set or the micro-instruction set, since it is defined by the same mask that defines the macrocode (i.e. the same mask that defines the macrocode). But then macro assemblers and micro assemblers (computer programs used as design aids for customers) are different. The micro-assembler is written for all suitable useful micro-states, then only a selected number (within 256 in this example) is selected for a given type. Of course, in addition to these methods of modifying device 10, additional microcode or macrocode in the ROM can be utilized to increase the size of the ROM to allow more complex algorithms to be programmed. However, the main feature of the invention is that the ratio of microcode to macrocode in ROM 11 can be varied to provide a more or less composite micro/macro instruction set. Microcomputer chip 10 operates with a fundamental clock frequency represented as crystal (Xtal) in FIG. This frequency of approximately 5 MHz is provided by an internal oscillator 33 controlled by an external crystal coupled to the two pads labeled Xtal in FIG. 1 or FIG. CLOCK From the crystal, the clock generation circuit 33 generates each microinstruction cycle or state time S1, 82, as seen in FIG.
Create four basic half-cycle clocks H1, H2, H3 and H4, overlapping for etc. Each state time is equal to two complete cycles of clock Xtal. H4
overlaps the two state times. l/4 cycle Q1, Q2
, Q3 and Q4 are also defined within each state time. A call to RAM12 occurs simultaneously with a microcode call from ROM11. A short memory cycle calling RAM 12 is completed in one state time such as 81 in Figure 4, control #MEMCNT is low and all bits on the AH bus are low during H1, and the RAM address is A valid address that appears on the AL bus while #MEM is high. Write control #WR is high for writing and low for reading. The recalled data is then valid data that appears on the MD bus during H4 at the end of the cycle over the beginning of the next cycle, so the data can be loaded into register T or IR at the end of one cycle or is gated to the P bus or N bus at the beginning of . RAM
All memory references to register file RF in 12 use this short cycle. All other memory references (i.e. references to on-chip ROMI for macro code, peripheral file PF1 and extended memory in extended mode) require two microinstruction cycles and are requires long memory cycles. For long cycles, the memory continuation command #MEMCNT is high during the first state time and low during the second state time. Memory command #MEM must be high during H1 of both cycles, and the address must be high during H1 of the first cycle.
must be reasonable. For reading, write command #WR is low from the beginning of the first cycle to H1 of the second cycle, and the data is valid during the beginning of H4 at the end of the second cycle. For long writes, #WR is high and the write data is gated on the MD bus at H4 in both the first and second cycles. Within a given state time or microinstruction cycle, the addresses appearing on the AH' and AL' buses are valid during H2. This address is based on the address loaded into AH and AL during Hl. In ROM1 1, the array is precharged during Q1, all rows or X lines go to Vss and all columns or Y lines go to Vec, then the ROMX address is transferred from decoder 11X to the array at the beginning of Q2. and the ROM Y address is valid at the beginning of Q2, so the ROM output is valid at either the microcode or the macrocode by Q4. Table A of this specification or the Japanese patent application “Patent No. 57-6
In executing the microinstruction set of '0848 Specification,' 5 to 10 microcode states such as S1, 82, etc. are added depending on the address mode.
Although normally required for instructions such as move, compare, etc., multiplication or division requires more microcode state. As seen in FIGS. 4 and 4a, the timing of microcode calls to ROM 11 is different during macrocode retrieval. During short memory cycles and all other machine cycles except macro code retrieval,
The G R OM command is asserted (MUXCNTL is low) and the decoder for ROM 11 receives the μA address generated on entry point path 21 in the previous cycle. This is shown in the middle of Figure 4 and in Figure 4a. G
The R OM command does not occur, the address from AHSAL does not activate decoder 11X of ROMI 1, and the output does not pass through latch 11C to MD. However, if #MEMCNT and the AH address of the page from FO to FF are generated, MUXCNTL and G
When the R OM command is asserted, decoders 11x and 11y receive AH' and AL' addresses L/s. This results in a long memory cycle for fetching the macrocode, so the microcode call is at the bottom of Figure 4 and in Figure 4a.
It means that it is transformed as shown in the figure. The microphone address μA output from the encoder 1 point same path 21 generated in the last cycle is Q2 in the state before S1.
Q4 is valid when MUXCNTL is low.
ROM11 is gated by GROM to the decoder of ROM11, producing a microcode output appearing on line 18 to operate in state S1. The address that the macro code should retrieve is made valid by Q2 appearing in AL and AH,
One buffer is latched. From lines 23 and 24, the microaddress μA to be created by this state S1 is S
IQ1 to S2Q4 is reasonable, and Figures 4 and 4
As seen in Figure a, the latching of buffer 1lb due to the lack of a GROM command is maintained by keeping lines 23, 24 valid. This latched μA is in state S
It is used starting with S2Q1 for microaddress 3. During S2, RO~111 is called for the macro code at the address created in ALSAH during S1. Macro code data is 8 bit latch 11C during S1
The latch produces an 8-bit macrocode output to the MD bus when GROM is asserted in S2Q4. The microcode executed at 82' of the macrocode fetch cycle is created in response to the microcode from state S1, typically increments PCI, and
Load the data from 1 through the MD into IR or T, or leave it in the MD for use in the next state S3 as an address appearing on AH or AL. This 52' microcode is retrieved during S1 at the same time as the microcode is retrieved in S2. The CPU 13 in the microcomputer 10 of FIG. 1 is comprised of an ALU 14, a register 15, and a bus 16 controlled by the microcode output of the ROM 11. FIG. 5 shows a more detailed block diagram of the ALU and shift circuit S and associated buses, and FIG. 6 shows the ROM 11 and its microinstruction code bit 18. Control of the ALU and calls to the bus are completely defined by these microinstructions, bit 18, identified in FIG. 6 for the illustrative embodiment. The 8-bit microaddress appearing on line μA from the entry point circuit 21 passes through the multiplexer 1, -1m to the X decoder 11X on line 21.
Contains the 6-bit X address appearing in x and Y
It also includes the 2-bit Y address appearing on line 21Y going to decoder 11y'. The X decoder 11x in this example is RO
M1 Selects one of the 64 X-rays in the array of 1 ROM bits. The Y decoder 11y' selects one of the four Y lines in each group (up to 641!$ available). Therefore, for each 8-bit address appearing on line μA, a different "microinstruction"
is the output appearing on line 18. A microinstruction may operate any number of active lines 18, but typically only two
The combination of ~3 lines 18 is unique for a given microinstruction. Each line 18 goes to buffer 1lb to drive a higher capacitance load than the array output allows on its own, and to clock the gates and other logic as required. All microinstruction bits (control lines 18) in FIG. 6 and elsewhere in the invention are designated with the prefix "#". Some bits are active low and are therefore marked with a negative sign, such as #-O t ST. In the microinstruction bits of Figure 6, the character “

Since [] stands for "toJ", #-OtST means "O bus to ST register", ie the gate connecting the O bus to the status register is activated by this bit. The 8-bit interlaced address appearing on line 23 is represented by #J IIIpAddr (7 -0), while the 3 bit appearing on line 24 used for the designated address
Bit skip control is represented by #JmpCntl (2-0). These 11 bits are used by entry point circuit 21 to create the next microaddress μA. A total of 20 bits 18 from #OtPCH to #ONEtAH in FIG. 6 are from bus 16 to register 15.
Control calls to . #LovWr among these
itcO and #LowWritc1 are decoded to create pseudo-microinstructions OtPCL, OtMAL and otsp. Bits #ONEtAL and #ONEtAH place a ``1'' on the AL or AH bus and place the microinstruction with B register address 000l or PF page address 0100 (hex). A
The default for all zeros appearing on L and AH is the A register address in the register file. The connections between register 15 and bus 16 are explained in detail below. The #~IEMCNT bit is a "memory continuation" control on long memory cycles. Since RAM12 is called for reading or writing in one state time, a call from ROM11 to the microcode or peripheral in PF uses two states, so the control line #MEMCN
T is active in the first state of every long memory cycle as seen in FIG. #MEMCNT
is used to generate several other control signals, necessarily identifying the first or second state of a long memory cycle. #MEM bit represents memory cycle, ROM
11, RAM 12, or external memory is always active when called. The #WR bit is a write command, so if #MEM and #WR are active, there are 7 memory write conditions, but if #MEM is active and #WR is inactive, there is a memory read condition rI. .#-LST signal is a load status command for ALUM calculation.Status register ST is output by #-LST command.
The bus gave me a swipe. ALU is #ShjrtCnt
l (3-0), #AIuCntl (3-0), and 9 bits labeled by #ABL. These controls are explained in detail below. Since the microinstruction bits 18 are arranged in the order in which they are used in the strip, and not necessarily in the order shown in FIG. 6, the control bits 18 are generated as close as possible to the point at which they are used in the strip. As seen in Figure 6, the microcode output has #P
Microcode #μC bits such as CHtP' are included, and these are buffers that delay one state to make the bits needed by the microcode in the second state of macrocode fetch (82' in Figure 4a). circuit 1
1b'. These bits come from buffer 11b' appearing on line 18b and are the same as some of bits 18. The second state of macrocode fetching is almost always one of three things: (1) the opcode portion of the approaching instruction is loaded into the IR and the PCI is incremented; (2) the address byte of the next state is between AH or AL
or (3) a byte recalled from ROM 11 via the MD is loaded into the T register for use in a later machine state and the PCI is incremented. . To increment the PCH, the ALU and microcarry controls are created as described below. Only a few active #μC bits are required from buffer 11b' because virtually all of bits 18 are zero to define the required microcode. These operations are e.g. IAQ-0, IAQ-
1 set, and BLoPPL-0, Bto, PPL-
1 and I LoA-0, I toA-1, as described in the microinstruction sequence of FIG. ROM output buffer 71l receiving lines 23 and 24
Part b is latched to hold microaddress μA for one state time whenever the CROM' command is asserted. Therefore, the next address made from lines 23, 24 in S1 is the S
It is held until the end of 2. The GROM' command is made from microcode bits #MEMCNT and the AH' bit. FIG. 6 also shows the 8-bit constant output #C (7-0) and the #CtN command that adds an 8-bit constant to the N bus. This constant function is not used for Table B microinstructions and may be used in place of immediate fetch for offsets, etc. Microinstruction control of calls to registers 15, bus 16 and ALU 14 is assigned to Texas Instruments, Inc., incorporated herein by reference.
It is described in the Japanese patent application "Japanese Patent No. 57-60848". Examples of ALU operations include addition with zero carry (#A luc ntl and #Shif't
Cntl is all zero) causes the ALU to calculate the sum of the contents of the P bus and the N bus. To calculate the difference between the contents of the P bus and the N bus: #AIuCntl - 1l11 and #Shil'LCntl - 0 0 0 1. Since borrowing is undesirable, the "1" must be carried in this subtraction. As a complete example, the following two microinstructions read the current byte addressed by the PCL and PCI registers and send it to the T/MA
H register and increment PCL and PCH registers: First microinstruction cycle (macrocode fetch S2 in Figure 4a): Bit operation #PCLtP. #PAL ...Place PCL on AL bus via P bus RPCIltAI+ ...Place PCI on AH bus
(default)...Place all 0s on the N bus #AIuCntl・0000, ...Increment PCL by one #ShlftCntl-0001
Carry up to add P and N.#LowWrite=10(OtPCL) =-A
The L U output returns to PC L without shifting via the 0 bus #MEMCNT. SMEM...Long reading first
Cycle #μC bit ... ltJump Addr XXXXXXX - This micro address #Jump Cntl XXXXX selected to create the second cycle microcode
is latched in 1lb for use in the third microinstruction S3. Second microinstruction cycle (32' in Figure 4a; microcode created by #μC bit of previous microcycle): Bit No operation (don't care...in AH and AL buses)
All. All) The contents are $PCIItP latched in the buffer 19 in the first cycle...Place the contents of the PCH register on the P bus...Place all 0s on the N bus.No case of N (default) 1: AluCntl-0000. $ShiftCntl-0010 110tPcH tIMEM tlMDtT - Add the micro carry μC from the PCL increment in the first cycle. ...The ALU output via the 0 bus (no movement) returns to the PCH register...Continue reading memory...Place the read byte in the T/MAR register via the MD bus. It is noted that the increment was done in the first cycle by using an ALU carry '1'. The second cycle is
Micro carry bit (μC) created in the first cycle
The high byte of the program counter in the PCH was incremented only if . During the second cycle, only 6 positive bits 18 are produced by #μC. Table C provides other examples of microinstruction state details. From FIG. 7, group decode circuit 27 and memory control circuit 28 are connected to address buses AH' and AL'.
and the three microcodes in Figure 4 ◆Bit #MEM,
A constant control signal is generated in response to #MEMCNT, #WR, and the clock. Ports A, B, C or D output signals GASGB, GC or GD depending on addresses AH' and AL', respectively.
selected by As seen in Figure 2a, the data for port ASB, C or D is located at location 0104, 010.
6, 0108 and 010A (even addresses), one of these ports is activated by one of these addresses, allowing calls to the MD bus. C
Or to set the direction of the D port, the least significant address bit 10 of AL' is also used to call the direction register portion of boat C or D (add 1 to 0108 or 010A). An ``l'' written to the direction register bit sets this bit of the boat as an output, and a ``0'' sets this bit as an input. RAM12 is AL' and AH' 0000 to OO
It is called by the GRAM command made by the group decode 27 according to the OIF (page O) address, and reading or writing is selected depending on the presence or absence of the rRAM write control 11 WRAM made in the memory control circuit 28 by the #WR microcode. Ru. In ROM11, the address of AH' and AL' is F00.
Whenever the first cycle of a long memory cycle in the range from 0 to FFFF is shown in FIGS. be done. GROM activates latch 11c in Y decode and output circuit 11Y to load the 8-bit microcode word from ROM11 onto the MD bus. The MUXCNTL command input of multiplexer 11m causes X address decoder 11X to use the X address from the AH' and AL' buses when it is high,
Anything from the μA bus when L is low is not allowed to be used. ROM1l is stored from address FOOO to FFFF, except when the MEMCNT and GROM conditions occur.
Long memory up to ◆G
Selected for microcode recall by ROM'. μA address and GR via multiple plexer 11m
X decoder 11X, which receives OM', activates decoder/output circuit 11Y' to provide a multi-bit microinstruction output on line 18 during all machine cycles except macrocode fetches. MUXCNTL directive is 4a
It goes high during 82 in the figure, causing the AL' and AH' addresses to be sent to decoder 11x instead of μA. Also, the circuit in Figure 7 is the load address command LDADDR.
is also created and the addresses of AH and AL are loaded into the address buffer 19. This occurs in all machine states except the second state of long memory cycles. The OtM directive is created according to the conditions described in the Japanese patent application "Specification of Japanese Patent No. 57-60848." Command LR to latch the microcode output of ROM11 to latch 11c
OM is created using the same conditions that create GROM and MUXCNTL, but the timing is different. That is, LROM occurs during S2Q4 in Figure 4a. One more
In one embodiment, the write FROM command WROM is provided if the portion of memory 11 is of the read/write type as described. The microstructure of the CPU, including the entry point circuit 21 of ROM11 and the microcode output, is designed to name various subfields of the contents of the IR, as described in Japanese Patent Application No. 1984-60848. The appropriate sequence of microcode in Table B is executed, as seen in the logic flow diagrams of FIGS. 8a through 8j, which resemble logic flow diagrams. FIG. 9 shows a typical opcode map, one example of which is Table A. Some examples of microcode states are shown in Table C. The designation of the IR subfield is based on the IR (e.g. IAQ-
2) and then executed by one of the first microinstructions. The appointment is then done by a microinstruction that includes one of the following to reload the IR: If no nomination is required while executing a given obcode, the IR
is used as a general purpose 8-bit register. Control flow between microinstructions is determined by how the next microinstruction address μA to ROM 11 is created in the entry point circuitry for both conditional and unconditional branches. The microinstructions stored in the chip's combinational ROM 11 are horizontally microprogrammed in that each microinstruction indicates an address at which to place the next microinstruction to be executed. The next micro address μA is defined by two fields (vA23 and 24) of CROM output 18: (1) #Jump Addr (7-0), ROM
8-bit field indicating the base address of I1; and (2) #JmpCntl (2-0), #J
A 3-bit code indicating one of the eight nominations offset from the address of ump Addr (7-0). If #Jump Cntl (2-0) = r000J, the #Jump Addr field is simply used directly as the address of the next microinstruction. For example, in Figure 8b, this is from BtoPPL-0 to BL
This is a continuation of oPPL-3. # Jump C
If ntl(2-0) is non-zero, it indicates which control line replaces the low bit of #Jun+p Addr and thus makes the next microaddress μA. This method ci,
0848 and is easily implemented in MOS technology. In the device of this example, a maximum of 256 microinstructions are possible, and each microinstruction is a multi-bit word (output 1
8), but a total of less than about 150 microinstructions are required to execute the Table A instruction set of this example, thus using less than 150 8-byte wide words of ROM. Each of these is a 64-bit word containing 64 microinstruction-controlled outputs 18, although fewer bits may actually be used. Additional microcode features (new macro instructions) for this device include:
execute a subset of the standard Schedule A instruction set,
Added by replacing it entirely. The functions performed can be expanded by using more microcode in ROM 11. Referring to FIG. 2a, in the main operating mode of the microcomputer in FIG.
and a microcomputer mode contained in RAM12. The device is first set or reset by RST to be in microcomputer mode, ie zeros are placed in bits 7 and 6 of I/O control register 0100. In this mode, only 5 or 6 bytes of the peripheral file FF are used, and the remaining 250 have no function. Peripheral file register numbers PO, P4, etc. and hexadecimal address for microcomputer mode are 2a.
As shown in the figure. Port A is for input only, port B is for output only, but port C and port D can be used for either output or input. That is, registers P9 and P11 direct the data at ports C and D, but such control registers are not needed for ports A and B since they are unconditionally inputs or outputs. Ports A, B, CSD data registers are contained within the input/output huffer and are called by the MD bus using addresses 04, 06 and OA (hex) on the AL bus and page one or 00000001 on the AH bus. . Similarly, AL address 09 and OB call the control registers contained in the buffers for port C and port D. rOJ in the 1 and 1j control register bits sets the input port, and "1" sets the output port. The ROM 11 program is of course written to avoid addresses added to AL and AH that are in unused area, as these addresses will not produce significant results. In FIG. 10a, an apparatus is shown including an eight digit display 13-1 and a keyboard matrix 31-2, using the device of FIG. 1 in its microcomputer mode. The C port is used for segments of the display, and the B port outputs drive the digits of the display 13-1 and the columns of the keyboard matrix 13-2, as described, for example, in U.S. Pat. , No. 921,142 or No. 4,158,431
It is as shown in the number. Row of keyboard matrix 13-2 is applied to the A port input. 8X8-6
A key matrix of 4 is possible, but fewer than 64 are typically required. Van Bavel U.S. Patent No. 4,158, assigned to Texas Instruments.
Other activators and sensors, such as those used in the microwave oven controller of , 431, may be connected to the D port as inputs or outputs. In the peripheral expansion mode of the memory map of FIG. 2b, peripheral pages 0100 through OIFF, or 256 bytes, are available for off-chip calls. The C port is used as a multiplexed 8-bit address/data bus, and the 4 bits of the B bus are connected to control lines ALATCH, R/W,
ENABLE and CLOCK OUT, as shown in the apparatus of FIG. 10b. This system uses the microcomputer 10 of FIG. 1 as the main processor in a manner that uses two other attached processors. One is a video display processor 13f, as described in US Pat. No. 4,243.984, issued to Gu*tag et al., assigned to Texas Instruments. The other is a general purpose interface bus adapter chip 13g that interfaces chip 10 with a standard IEEE 488 bus 13h. Chip 10 is set to 8 by the address latch signal ALATCH on port B4.
Bit 1...Latch 13l. 8 of the C port latched to
Create a bit address, then that address is
6 enable signals are available on address bus 13j for chips 13f and 13g when activated. Chips 13f and 13g are synchronized with chip 10 by the clock output of port B7. Next, the C port is controlled by the chip 10 depending on the read/write control R/W of port B5.
, used for data entering and exiting chip 13f and chip 13g. Thus chips 13f and 13g
is the address 0108, 0 1 of bus AL and AH
09, . . , and from OIOA to OIFF. Of course, the AH bus in Figure 1 is
Always contains 01 in this mode for off-chip calls. In this peripheral expansion mode, the A port is used as an input, and the D
Since the ports serve as inputs or outputs, other functions are performed except for calling chips 13f and 13g. Actuators and sensors, such as those shown in FIG. 10a, or a keyboard matrix are used here as well. The fully expanded mode of Figures 2c and 10c is
It provides an 8-bit address output of the C port as shown in FIG. b and another address byte of the D port which may address, for example, memory chip 13k. Full expansion mode is full 64K (2 bytes to C and D ports)
gives the off-chip address range of Address 01
08 through FFFF are available for off-chip calls. As mentioned above, at address 0106 port B provides memory control and bits B4, B5, B6,
Gives B7's Kura Kunk movement. memory chip 13
k can be a 32K device, for example, and the lower byte address from the C port is latched at 131, but the upper byte goes directly to chip 13k by line 13m. The data bus 13n going to the C port is connected to the chip 13f,
Shared by 13g and 13k. Therefore, although the device of FIG. 10c has a much larger program capacity than the device of FIG. 10b, the D port is
not available. But keyboard matrix 13
-2 is connected to the remaining 4 bits of the B boat (address 0106, bits 0-3) and the A boat as shown. A microcomputer 10 made in accordance with the present invention is disclosed in U.S. Pat. No. 4,158.431 issued to Van Barbel et al., assigned to Texas Instruments.
may include self-testing procedures such as those shown in this issue. The procedure of Patent No. 4,158.431 converts all of the display characters 13-1 and keys 13-2 in FIG.
1 from testing under the control of a series of microinstructions. Although this self-test procedure establishes that all of the external elements of the device are working and provides some indication that the chip 10 itself is fully functional, it is not an exhaustive check. However, before connecting to such equipment, a functional test must be carried out. For example, to test the contents of the ROM 11 after manufacturing (before delivery to the customer or by the customer as a receiving material inspection), the entire contents of the ROM may be read out one word at a time;
Comparing each word to a desired bit pattern has previously been performed. Microcomputer devices that permit such testing are disclosed in U.S. Pat. No. 3,921,142 issued to John D. Bryant et al. E.R.
E. R. Caudel and Joseph H. Ray
U.S. Patent No. 4. '02
No. 4,386. However, such a test
It requires the test machine to store the entire ROM code, ie 2048 bytes or 4096 bytes, and also requires a separate check code for each different ROM code. ．． Additionally, this test requires at least one transfer between the test machine and the device under test for each type of ROM. These elements make the test unduly long, require extensive test data or software, and consume a modest amount of program space on the test machine. As shown in the Japanese patent application "Patent No. 57-60848" assigned to Texas Instruments, the microcomputer 10 has a 2-byte macro code fixed in the ROM 1 1 at the time of manufacture, and the remaining macro code is tested. Any test method that is commonly used can be used. This two-byte code is different for each ROM code or program and represents some function of all other bytes encoded within the ROM. For example, it is
It may be the LSB of the sum of all other bits in the ROM, or it may be some other function that provides multiple testing of possibly all bits. This two-byte code is called a cyclic redundancy code, or CRC, and is a function of each bit of data used to create it.
It is a 6-bit value. CRC is ROM except for CRC itself.
It is calculated using each byte of macro code in . The program for this test is loaded into RAMi2 of chip 10, while chip 10 is in one of the extended modes (FIG. 2b or FIG. 2C) by a sequence of move double MOVD or move MOV instructions. using this method,
All of the test codes are stored in RAMI 2, then M
The OV instruction returns microcomputer 10 to the single chip mode of Figure 2a. All bytes in ROM are A
If the LU function is passed, the exam ends. The program then sets port C as an output and outputs a code indicating to the outside world that the calculation is finished, so the test machine is alerted to look for the two byte results on the C and D boats. The original check code is compared with the calculated value to produce a comparison output. Approximately 890,000 machine states are required by the microcomputer 10 running this test program, but these are all internal; the test machine does not have to store any unique code and can - Chip recall is not required for the majority of tests. However, one embodiment of the present invention allows for additional testing equipment to be utilized. The microcode itself is recalled one byte at a time and checked against a check code stored in ROM 1'l or an externally stored representation of the microcode. For this purpose, the microcode portion of ROM 11 is written to a peripheral file by the rMOV%n,PnJ instruction, for example, or to the A register by rMOV%n,AJ, which causes it to be activated internally.rMOVP A, It is called by the decoder 11y1 latch 11c and the MD bus to be written externally by the PnJ instruction. Fetch-immediate microcode, typically used to fetch operand addresses or constants, for example, is used to add a byte of microcode from ROM 11 to one of the output bauds B, C, or D. . Instruction rMOVP %
FFOI, P6J are in the following microcode states: IAQ-0, IAQ-1, IAQ-2, ItOPPL-
0, ILoPPL-1, BLoPPL-0, BtoPP
L-1, BtoPPL-3, STP-0, STAL-2
and then returns to IAQ-0, this sequence can be seen in FIG. 8 and in the table of Japanese Patent Application No. 1984-60845. The state of ItoPPL-0! (corresponds to 82 in Figure 4a)
During this period, the byte of microcode in FFO1 (macrocode address in Figure 2), which is 1 byte of 8 bytes of the microcode state in Table B or Figure 8, is processed by the ALU, Chip writing or RA
Called for MI 2 write. Since the above test program is used to test both the microcode and the ./crocode, the CRC is calculated taking into account all bytes of the microcode and macrocode portions of the ROM 11. The method operates as described above, with the load instruction retrieving all bytes of ROMI 1 containing the microcode. Microcomputer ◆ This method of chip testing is advantageous in development and is also important in mass production activities, which have some problems. The number of external bins is limited and the data available to the pins is limited by the instruction set and internal circuitry. Therefore, when testing a packaged device, hundreds of internal nodes and signals are not available externally. Internal blobbing is delicate and extremely time consuming. Therefore, there was a need to provide a tester that could be cycled through virtually every possible operation of the device to check for manufacturing defects. Test equipment for LSI chips is of course controlled by computers, but this type of testing still not only takes too long to run, but also requires software, since all different ROM codes for each customer require different test sequences. The cost becomes prohibitively high. Indeed, such tests were incomplete because the execution of certain instruction sequences was data dependent and all possible combinations could never be executed or even imagined. Additionally, time and program storage limitations on test machines impose real constraints. Memory 1 to replace rROMJ programmed during manufacturing
1 can be of the read/write type with static RAM cells, so both macrocode and microcode are loaded from outside the chip. From Figure 6a, memory 1
1 is the same as before except that it includes a "ROM write" control WROM and the decoder 11y is not only an output circuit but also an input/output circuit. Group decode circuit 27 and memory control circuit 28 create a WROM command when GROM AND #WR occurs. A portion of memory 11 must remain permanently programmed so that there is enough macrocode and microcode to perform the task of loading the rest of the memory. To this end, the reset microcode of FIG. 8e is fixed in the permanent ROM part of the memory 11, together with the microcode necessary to perform long reads from the peripheral file PF and long writes to the memory 11. Therefore, the reset sequence is supplemented by adding a group of microcodes that, for example, read port A and write port A data to memory 11 until all of the read/write addresses of memory 11 are loaded. The microcode address for this function and reset is
Everything can be changed to be at the FFFF end of the array or anywhere else convenient from an assembly and programming standpoint. When the memory 11 is first loaded and the task of the loaded program is completed, the entire read/write portion 11W of the memory 11 is filled with new microcode as well as macrocode, or only the part of it that has been replaced for the new task. will probably be redone. Permanently programmed portion 11P contains all the macrocode and microcode that requires this update task in addition to the reset or initial loading task. As explained in the Japanese Patent Application No. 57-60848 or shown in FIGS. 8a to 8j, the execution of microinstructions is performed in the first
Macro interrupt pin INT in the figure or INT- in Figure 8e
Interrupted by a microinterrupt device that is in addition to and completely separate from the functionality of the 0 to INT-5 microinstructions. From FIG. 6b, it can be seen that due to the microinterrupt signal μI produced by the microinterrupt control latch 36, the microaddress present in SIQ2 of FIG. is applied to the decoder of ROM 11 via line μA under the control of multiplexer 32. The vector address initiates a sequence of microinstructions as shown in Table D: (a) saves all pending registers, addresses, and status bits; (b) saves the RF register (in this example (c) Decrement the value of timer 1 and write it back to RF (R63). (d) If the value of timer 1 is equal to zero, interrupt flag 1 (R62, bit 0 ) (e) Timer 2
, timer 3, etc., (1+) or (d
) Continue (1') Return to pending microinstruction sequence In (a), only the μINT-0 microinstruction saves the MD bus: PCLSPCH, AML, T/MAH,
This is because the IR, ST and sp registers are not used or changed in sequence. Alternatively, M
D-bus data is saved on the stack by push and hop microinstructions. Status register ST has #LS. Since the T bit is not asserted in Table D, it does not need to be stored by the microinstruction. Instead of using the RF register as a flag, another bit of the status register ST is used. By the way, hardware latches are used to enable macro interrupts. In the above embodiment, the microinstruction must be added to the IAW sequence to test the microinterrupt flag (R62, bit 0) at the beginning of execution of each new macroinstruction before testing for macrointerrupts. The bit test is performed by IAQ in order to check the micro-interrupt flag and to perform any desired function by writing new values to timer register R63 etc. and using macro code, e.g. by a trap routine.
- Executed before 0. IAQ-Oa and I in Table D
AQ-Ob reference 4B One may be specified to determine the number of different timers upon activation;
The microcode in the table is written to loop over the number of times set by this register. moreover,
The interval between micro-interrupts can be made variable using one or two of the PF registers, such as P2 and P3, which define the count chain. In this way (using two such registers), the time between microinterrupts can vary over a range of 216 under microcode control. The effect of a micro interrupt device on an assembly level programmer writing macro code is exactly the same as a hardware timer expiring. The microprogram requires j, for the CPU to run the timer.
All you need to know is that +71ijl will be shared. Chapter 6b
The micro-interrupt device shown acts as a one-level micro-subroutine, and of course the timer can be used for many other purposes as well. The microcomputer detailed herein is
It takes the form of an N-channel silicon gate integrated circuit on a single silicon chip. However, the features of the present invention may also be used in devices made by other processes such as metal gate, P-channel, CMOS, silicon-on-sapphire, etc. In addition, the combination memory 11 is a fixed program type mask programmable RO
Although it was described as M, it is of course electrically programmable RO.
M or electrically erasable ROM is used. ROM1 1 is called program memory, and RAM1
2 are referred to as data memories, and these are the main functions in many applications. However, it goes without saying that the "data" from ROM 11 can be used in some algorithm (where the "data" is a constant, etc.), the device can execute macro instruction code from RAM 12, and the macro code or program block can be transferred externally. R from a tape or disk drive or from a telephone coupler, for example.
It is downloaded to AM12 and executed from RA to f12. Additionally, additional control lines and functions such as READY, HOLD, bus status codes, etc. may be used in devices with features of the present invention. Although the invention has been described in terms of illustrative embodiments,
The descriptions are not meant to be construed in a limiting sense. Various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reading this description. It is therefore intended that the appended claims cover all such modifications or embodiments that fall within the true scope of the invention. Ta C. ) [-I ← Country] Toω■＜ωRoroω-RoNωside's ΦToω■Pe's oOω
Gift! Self-coro lolo loco ω ω (4)0- (4)
-4 Yama et al. Low et al. Mu-Cs. ．． In addition to the above disclosures, we further disclose the following. A bus device that calls the arithmetic/logic unit and registers, and a command that controls the operations of the arithmetic/logic unit, registers, and bus device and their calls in response to instruction words. A microcomputer device including a semiconductor integrated circuit having a control device and a control device all within an integrated circuit, the control device including an address input device and a combinational memory device having a first multi-bit output and a second multi-bit output, an address device for applying a first address and a second address to said address input device, each first address initiating an operation selected by a command word;
The microcomputer device characterized in that the address produces at least one microcode output word defining a plurality of said commands. (2) an ALU that performs arithmetic/logical operations with operands provided to its inputs under the control of microcode bits;
a data/address bus device that accesses the ALU and registers under control of the microcode bits; and a read/write microcode memory device that stores the microcode. , an apparatus for loading said memory device from a source external to the device, and wherein all of said elements are formed on a single semiconductor integrated circuit, and said bus device and registers are larger in number than the number of bits in a microcode word. Said microcomputer device, characterized in that it also contains far fewer bits. (3) A microcomputer device formed on a single semiconductor integrated circuit with an internal self-test function of the microcode, which calls an ALU having multiple address/data registers, registers for the ALU, and input/output. a control device for determining the operation of the CPU including a CPU having a bus device; and a device for generating a plurality of different microcode words each having a plurality of b bits; a storage device in an integrated circuit for storing a test code representation of the plurality of bits; an apparatus for performing a sequential operation on all bits located in a block, producing a first output if the result of such operation corresponds to said test code representation, and producing a second output if such result does not correspond to said test code representation; The microcomputer is characterized by comprising:
device. (4) An arithmetic/logic unit, multiple registers that store data and memory addresses, a bus device that calls the arithmetic/logic unit and registers, and In a microcomputer device that has both micro-interrupts and macro-interrupts, including a semiconductor integrated circuit that has a controller that creates a sequence of command sets that control the operation, and a controller that creates a sequence of commands that control the and a device for invoking a sequence of instructions and making one of said sequences of the instruction set in response to each instruction word, the control device interrupting any of said sequences of the instruction set while saving data in said registers and bus device. and operations not specified by the instruction/
the controller includes a device for executing a micro-interrupt routine of a set of instructions that performs an operation by the logic unit and then returning to such sequence; 1. A microcomputer device as described above, comprising: a device for executing a micro-interrupt routine of an instruction word using a micro-interrupt routine and then returning to the interrupted sequence of instruction words.

[Brief explanation of drawings]

Figures 1a and 1b are CPU ROM and RA
MOS/LS that includes M and utilizes the features of the present invention
I Block Diagram of a Microcomputer Chip FIG. 2 is a memory map of the logical address space for the microcomputer of FIG. 1; FIGS. A detailed memory map similar to Figure 2; Figure 3 is an enlarged plan view of the semiconductor chip containing the microcomputer of Figure 1 showing the structural layout of various parts of the device; Figures 4-1 and 4-2; 4a is a timing diagram similar to FIG. 4 for a macrocode call cycle; FIGS. 5a and 5b; FIG.
The figures are detailed electrical diagrams of the CPU including the ALU, shift circuit S1 register and bus in the microcomputer shown in Figure 1, Figures 6-1 and 6-2, Figures 6a-1 and 6a-2. and FIG. 6b shows a combination user ROM and control ROM used in the microcomputer of FIG.
A detailed electrical diagram of M, Figure 7 shows the group of equipment in Figure 1.
Electrical diagrams of the decoding and memory circuits; Figures 8a to 8j are logic flow diagrams for the execution of the microinstructions in Tables B and C in the device of Figure 1; Figure 9 is a diagram of the example instruction set in Table A; 10a to 10c-2 are electrical diagrams of an apparatus using the microcomputer of FIG. 1, and FIG. 10d is a timing diagram of the apparatus of FIGS. 108 to 10c. . Explanation of symbols 10'--Microcomputer chip, 11...
・Combination ROM, 12...RAM, 13...CPU
, 14...ALU, 15...Register, 16...
Bus, 11X...Combination X decoding, 11y...Microcode Y decoding, 1 1 y. '... Microcode Y decode, 1lb... Microcode output buffer, 11C... Latch, 21... Entry point, 27... Group decode, 28...
-Memory control, 29... Interrupt control, 33... Clock generator.

Claims (1)

[Claims] (1) A microcomputer device formed on a single semiconductor integrated circuit with an internal self-test function of a microcode word, comprising an arithmetic logic unit with data input/output and a plurality of arithmetic logic units with data input/output. address/data registers, and bus means for accessing data inputs/outputs of the arithmetic and logic units and registers for data transfer;
a central processing unit, wherein said arithmetic logic unit, register and bus means have control signal inputs; and means for defining the operation of said central processing unit and generating a plurality of microcode words each having a plurality of control bits. control means connected to control signals of said arithmetic and logic unit, registers and bus means; a storage device for storing a check code representation of all bits of all of said plurality of microcode words; and less than said plurality of control bits. accessing the plurality of microcode words of the set, performing a cumulative sequential operation on all control bits of all the plurality of microwords, and generating a first output if the cumulative operation result corresponds to the check code representation;
A microcomputer device comprising: means for generating a second output when the second output does not correspond.