JPH0645965A - Decoder - Google Patents

Abstract

PURPOSE:To reduce the frequency of danger of failing decoding due to a failed estimation of communication line characteristics in a decoder for a digital communication system for estimating the communication line characteristics by using a training signal. CONSTITUTION:A communication line characteristic estimating unit 3 estimates the communication line characteristics based upon a demodulation signal corresponding to a training signal out of plural demodulation signals stored in a RAM 2 and outputs 1st and 2nd estimated results 14, 15. Equalizers 4, 5 decode the demodulation signals stored in the RAM 2 based upon the 1st and 2nd estimated results 14, 15 and store the 1st and 2nd decoded data 16, 17 in RAMs 6, 7. Bit error counters 8, 9 count the number of bit errors in the decoded data 16, 17 and output the 1st and 2nd bit error numbers 18, 19. A comparator 10 mutually compares the 1st and 2nd bit error numbers 18, 19 and allows a selector 11 to select decoded data having the smaller number of bit errors out of the 1st and 2nd decoded data 16, 17 stored in the RAMs 6, 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder, and more particularly to a decoder in a digital communication system using a training signal for estimating channel characteristics.

[0002]

2. Description of the Related Art In a digital communication system using a training signal for estimating a channel characteristic, a decoder as shown in FIG. 4 has been conventionally used.

The decoder shown in FIG. 4 has an input terminal 41.
RAM for storing the demodulated signal applied from the demodulator via the
42 and a demodulation signal obtained by demodulating a modulation signal that is modulated by a training signal of the demodulation signals stored in the RAM 42, that is, a demodulation signal corresponding to the training signal, using the communication path characteristics as an impulse response. The channel characteristic estimator 43 for estimating, an equalizer 44 for decoding a demodulated signal using a set of estimation results output from the channel characteristic estimator 43, and an output terminal 45.

As described above, in the decoder that estimates the channel characteristics and decodes them by the equalizer 44 based on the estimation result, if the channel characteristics are perfectly estimated, all the channel characteristics are estimated. In principle, it is possible to improve the characteristics up to the theoretical limit determined by the channel characteristics and noise. However, since the configuration of the equalizer 44 becomes very complicated for a communication path in which a delayed wave with a very long delay time is generated, it is possible to equalize even a delayed wave with a certain delay time. It is common to use a different equalizer 44.

FIG. 5 is a block diagram showing an example of the configuration of a receiving system connected to the front stage of the decoder shown in FIG. 4, in which a signal sent via a communication path is received by a receiver 51, It is demodulated by the demodulator 52 and converted into a digital value by the A / D converter 53 at a sample rate equal to the symbol rate.

FIG. 6 is a block diagram showing an example of the configuration of the demodulator 52, and is for the case where the received signal of the receiver 51 is a two-phase phase modulated signal.

The received signal of the receiver 51 is frequency-mixed by mixers 63 and 64 by a local signal from an oscillator 61 and a signal obtained by shifting the local signal by a π / 2 phase shifter 62, and passes through low-pass filters 65 and 66. , Is output as a complex signal. In the following description, it is assumed that the demodulated signal is a complex signal.

FIG. 7 is a diagram showing an example of a training signal, showing a training signal composed of a sequence of 26 symbols.

FIG. 8 shows the center 1 of the training signal of FIG.
It is a figure showing the correlation coefficient of a reference signal and a training signal when 6 bits are made into a reference signal, and is in the shape of an impulse over -5T- + 5T. In this way, the channel characteristics can be estimated by using the sequence whose correlation coefficient is impulse.

FIG. 9 is a block diagram showing a configuration example of the communication path characteristic estimator 43 in the case where the training signal is that shown in FIG. 7. The input terminal 90 and the multiplier 91-
1 to 91-16, an adder 92, an output terminal 93, a register 94 for storing the center 16 symbols of the training signal, and a shift register 95.

The demodulated signal input to the input terminal 90 is shifted by the shift register 95, and the 1 of the shift register 95 is shifted.
Output from 6 taps. The output of each tap of the shift register 95 is multiplied by the reference signal, that is, the central 16 symbols of the training signal stored in the register 94, by the multipliers 91-1 to 91-16.

The adder 92 starts the training signal 25 (the last bit in FIG. 7) from the time when the demodulation signal corresponding to the training signal 0 (the first bit in FIG. 7) is output from the tap 97 of the shift register 95. ) Until the demodulated signal corresponding to () is output from the tap 96 of the shift register 95, each multiplier 91-1
The outputs of ˜91-16 are added.

As a result, eleven correlation values h (-5) to h (+5) are obtained at the output terminal 93, and these values h
(-5) to h (+5) are regarded as estimated values of the channel impulse response over approximately -5T to + 5T.

Here, assuming that the equalizer 44 can equalize the intersymbol interference caused by the channel impulse response up to the length 5, the channel characteristic estimator 43 estimates the channel impulse response estimated value h ( Among -5) to h (+5), the channel impulse response h (j) to h of length 5 that can equalize the sum of squares of five consecutive absolute values by the equalizer 44. Select as (j + 4). h
(J) to h (j + 4) satisfy the following expression (1)

[0015]

[Equation 1]

Of the demodulated signal, the portion corresponding to the training signal is roughly known, but when it is not accurately known, a wide range of demodulation expected to include the demodulated signal corresponding to the training signal is demodulated. The correlation value between the signal and the central 16 symbols, which is the reference signal, is obtained, and the one having the maximum sum of squares of five consecutive absolute values is selected from the correlation values.

[0017]

Since the above-mentioned conventional decoder decodes the demodulated signal using the set of estimation results output from the channel characteristic estimator, if the channel characteristic estimation fails. Has the problem that no correct decoding is done.

The reason why the estimation of the channel characteristics fails is as follows.

When a correlation value between a demodulated signal in a wide range expected to include a decoded signal corresponding to the training signal and 16 symbols which is the center of the reference signal is obtained and a set of estimation results is obtained from the correlation value, the training is performed. The correlation value between the demodulated signal that does not correspond to the signal and the reference signal may increase.Furthermore, if noise is added, the channel characteristic estimation result may be obtained from other than the correlation value between the demodulated signal and the reference signal that correspond to the training signal. May be chosen.

Further, even when the demodulated signal corresponding to the training signal is accurately known, when a large amount of noise is added to the demodulated signal, the optimum channel characteristic estimation result can be obtained from the obtained impulse responses. May not be.

An object of the present invention is to provide a decoder capable of reducing the risk that decoding cannot be performed due to failure in estimating channel characteristics.

[0022]

In order to achieve the above object, the present invention communicates using a first RAM for storing a demodulation signal and a demodulation signal corresponding to a training signal stored in the first RAM. A channel characteristic estimator that estimates a channel characteristic and outputs first and second estimation results, and the first RAM using the first and second estimation results output from the channel characteristic estimator Decode the demodulated signal stored in
An equalizer for outputting the second decoded data, second and third RAMs for storing the first and second decoded data output from the equalizer, and the first and second decoded data A bit error counter that counts the number of bit errors, a comparator that compares the number of bit errors of the first and second decoded data counted by the bit error counter, and the comparator based on the comparison result of the comparator. A selector for selecting and outputting one of the first and second decoded data stored in the second and third RAMs is provided.

[0023]

The channel characteristic estimator estimates the channel characteristic using the demodulated signal corresponding to the training signal stored in the first RAM, and outputs the first and second estimation results.

The equalizer decodes the demodulated signal stored in the first RAM by using the first and second estimation results output from the channel characteristic estimator, and decodes the first and second decoded data. Is output. The first and second decoded data are the second and third R
Stored in AM.

The bit error counter counts the number of bit errors of the first and second decoded data, for example, by comparing the training signal with the portion corresponding to the training of the first and second decoded data.

The comparator compares the bit error numbers of the first and second decoded data counted by the bit error counter, and the selector stores them in the second and third RAMs based on the comparison result of the comparator. One of the first and second decoded data that has been selected is selected and output.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a first RAM 2 connected to an input terminal 1, a channel characteristic estimator 3 connected to the first RAM 2, and a first RAM 2 are shown. R
First and second connected to AM2 and channel characteristic estimator 3
Equalizers 4 and 5, second and third RAMs 6 and 7 connected to the first and second equalizers 4 and 5, and second and third RAMs.
First and second bit error counters 8, 6 connected to 6,
9, a comparator 10 connected to the first and second bit error counters 8 and 9, a selector 11 connected to the second and third RAMs 6 and 7 and the comparator 10, and a selector 11 And an output terminal 12 connected to. Incidentally, such a configuration can be realized by using a digital signal processor. Further, in the present embodiment, the first and second equalizers 4 and 5 are assumed to be capable of equalizing the intersymbol interference caused by the channel impulse response up to the length 5. Further, in the present embodiment, the training signal shown in FIG.
It is assumed that the sequence of 26 symbols shown in is used and the central 16 symbols are used as a reference signal.

The input terminal 1 receives the demodulated signal 13 demodulated by the demodulator 52 shown in FIG. 5 and converted into a digital value by the A / D converter 53. The demodulated signal 13 is the first R signal.
It is stored in AM2.

The channel characteristic estimator 3 extracts the demodulated signal corresponding to the training signal from the first RAM 2 in which the demodulated signal is stored, and the correlation value h () between the demodulated signal corresponding to the extracted training signal and the reference signal. −
5) to h (+5) to obtain -5T to + 5T
Calculate the estimated value of the impulse response over the channel. Furthermore, the channel characteristic estimator 3 uses the correlation values h (−5) to h
Of (+5), a set of correlation values satisfying the above-mentioned equation (1), that is, a set of five consecutive correlation values among correlation values h (−5) to h (+5), The set that maximizes the sum of squared absolute values is output to the first equalizer 4 as the first estimation result 14, and the set of correlation values that becomes the next largest is the second estimation result 1.
5 and outputs to the second equalizer 5.

The first and second equalizers 4 and 5 use the first RAM based on the first and second estimation results 14 and 15, respectively.
The bit deviation is corrected by decoding the demodulated signal stored in No. 2, and the correlation coefficient between the decoded data and the known training signal is maximized, and the bit deviation is corrected. 1, second decoded data 16, 1
7 is output.

The first and second decoded data 16 and 17 output from the first and second equalizers 4 and 5 are the second and third RAs.
Stored in M6,7.

When all the first and second decoded data 16 and 17 are stored in the second and third RAMs 6 and 7, the first and second RAMs are stored.
Bit error coefficient units 8 and 9 of the second and third RAMs 6 and 7
By comparing the decoded data corresponding to the training signal stored in the first and second decoded data 16 and 17 with each other.
The second bit error numbers 18 and 19 are obtained.

The comparator 10 has a first and second bit error number 1 added from the first and second bit error counters 8 and 9.
8 and 19 are compared, and if the first bit error number 18 is smaller, a selection signal for instructing the selection of the second RAM 6 is output to the selector 11, and the second bit error number 19 is detected. When the number is smaller, a selection signal for instructing selection of the third RAM 7 is output, and when both are equal, the second and third RAMs are output.
Of 6 and 7, a selection signal for instructing the selection of a predetermined RAM is output.

The selector 11 selects the comparator 10 out of the decoded data 16 and 17 stored in the second and third RAMs 6 and 7.
The decoded data stored in the RAM selected by the selection signal from is output to the output terminal 12.

In the above-described embodiment, after all the decoded data 16 and 17 are stored in the second and third RAMs 6 and 7, the first and second bit error counters 8 and 9 are used. Although the bit error numbers 18 and 19 are obtained, the bit error numbers 18 and 19 are immediately obtained after the decoded data necessary for obtaining the bit error numbers 18 and 19, that is, the decoded data corresponding to the training signal is obtained. It is also possible to ask.

FIG. 2 is a block diagram of another embodiment of the present invention.

In this embodiment, the first and second estimation results 14,1
Channel characteristic estimator 3a that sequentially outputs 5 and the first RA
The demodulated signal stored in M2 is decoded based on the first and second estimation results 14 and 15, and the first and second decoded data 16 and 17 are stored in the second and third RAMs 6 and 7, etc. By providing the equalizer 21, it is possible to use only one equalizer, which was required in the embodiment of FIG. In FIG. 2, the same symbols as those in FIG. 1 represent the same parts.

FIG. 3 is a block diagram of another embodiment of the present invention.

In this embodiment, after the bit error number 18 of the decoded data stored in the second RAM 6 is calculated, the third R
Bit error number of decoded data stored in AM7 19
By providing the bit error counter 22 for obtaining the above, it is possible to use only one equalizer, which was required in the embodiment of FIG. 1, and two equalizers are needed in the embodiments of FIGS. 1 and 2. Only one bit error counter is required. In FIG. 2, the same symbols as those in FIG. 1 represent the same parts.

In the embodiment shown in FIGS. 1 to 3, two sets of decoded data are generated using the two sets of estimation results, and the decoded data having the smaller number of bit errors is selected. Of course, it is possible to generate three or more sets of decoded data using three or more sets of estimation results and select the decoded data with the smallest number of bit errors among them.

[0042]

As described above, the decoder of the present invention is provided with the channel characteristic estimator for obtaining the estimation result of the first and second channel characteristics, and the decoding is performed using the first estimation result. Of the first decoded data and the second decoded data decoded using the second estimation result, the one having the smaller number of bit errors is used as the decoded data. Even when the corresponding part is not accurately known or when a large amount of noise is added to the demodulated signal, the risk of failing to estimate the channel characteristics and preventing correct decoding as in the conventional example is reduced. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional decoder.

FIG. 5 is a block diagram showing a configuration example of a reception system connected to the preceding stage of the decoder.

FIG. 6 is a block diagram showing a configuration example of a demodulator 52.

FIG. 7 is a diagram showing an example of a training signal.

FIG. 8 is a diagram showing a correlation coefficient between a reference signal and a training signal when the center 16 bits of the training signal is used as a reference signal.

FIG. 9 is a block diagram showing a configuration example of a channel characteristic estimator 43.

[Explanation of symbols]

 1, 41, 90 ... Input terminals 2, 6, 7, 42 ... RAM 3, 3a, 43 ... Channel characteristic estimator 4,5, 21, 44 ... Equalizer 8, 9, 22 ... Bit error counter 10 Comparator 11 ... Selector 12, 45, 93 ... Output terminal 51 ... Receiver 52 ... Demodulator 53 ... A / D converter 61 ... Oscillator 62 ... .pi. / 2 phase shifter 63, 64 ... Mixer 65, 66 ... Low-pass filters 91-1 to 91-16 ... Multiplier 92 ... Adder 94 ... Register 95 ... Shift register 96, 97 ... Tap

Claims (2)

[Claims] 1. A first RAM for storing a demodulation signal, and a demodulation signal corresponding to a training signal stored in the first RAM for estimating communication channel characteristics, and first and second estimation results. And a demodulation signal stored in the first RAM using the first and second estimation results output from the communication channel characteristic estimator, An equalizer for outputting the second decoded data, second and third RAMs for storing the first and second decoded data output from the equalizer, and the first and second decoded data A bit error counter for counting the number of bit errors, a comparator for comparing the number of bit errors of the first and second decoded data counted by the bit error counter, and the comparator based on the comparison result of the comparator. Second and third RAM
And a selector that selects and outputs one of the first and second decoded data stored in the decoder. 2. The bit error counter comprises the first and second bit error counters.
By comparing the portion of the decoded data corresponding to the training signal with the training signal,
The decoder according to claim 1, wherein the number of bit errors of the second decoded data is counted.