JPH0645583A - Manufacturing method of semiconductor device and solid image pick-up device - Google Patents

Abstract

PURPOSE:To reduce the interface level density while suppressing the level of defects caused by implantation. CONSTITUTION:An insulating film 22 is formed on a P-type silicon substrate 21. Later, a resist pattern 23 is formed on the insulating film 22. Next, phosphorus ions 24 are implanted using the resist pattern 23 as a mask. Later, the resist pattern 23 is formed again on the insulating film 22 to be doped with boron ions for the formation of a channel stopper region 26 and then another insulating film 27 is formed again. Later, a deposited oxide film 28 is formed on the region excluding the region to form a photodiode 25 thereon. Next, the whole surface is doped with boron ions 29 using the deposited oxide film 28 as a mask. Finally, the whole surface of the silicon substrate 21 is continuously doped with fluorine ion beams 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, a solid-state image pickup device and a method of manufacturing the same for improving a leakage current of a photodiode formed in a silicon VLSI.

[0002]

2. Description of the Related Art Photodiodes are commonly used to convert light into electrical signals. In the photodiode formed on the silicon substrate, a signal converted into an electric signal leaks through the silicon substrate. This leaked signal is called dark current. If the dark current increases, a signal component of an abnormal level that does not correspond to the amount of light is generated when used in a low light amount, and it cannot be used as a normal element.
It is considered that the cause of the dark current is the interface state density of the silicon surface and process-induced defects. Therefore, in order to suppress this dark current, it is necessary to prevent the effects of interface state density and crystal defects on the surface of the silicon substrate. Therefore, an impurity layer having a conductivity type opposite to that of the photodiode is formed on the surface of the photodiode. This prevents the depletion region extending from the photodiode from extending to the surface side when a voltage is applied to the device.

This conventional method will be described with reference to FIGS. 14 and 15. A silicon oxide film or an oxide film 2 containing silicon nitride is formed on a P-type silicon substrate 1. A mask 3 is formed on the oxide film 2. After opening the mask 3 at a predetermined position, the phosphorus ion beam 4 is selectively implanted. Then, by heat treatment, phosphorus ions are diffused to a depth according to the characteristics. By this phosphorus ion implantation, a relatively thin N-type diffusion layer to be the photodiode 5 is formed.

Further, as shown in FIG. 15, a P-type diffusion layer 6 is formed on the surface by implanting a boron ion beam 7.

Further, an oxide film, an electrode, and a metal wiring are formed thereon to form an element having a desired structure. As an example of this element, FIG. 16 shows a cross-sectional structure of a photodiode and a readout section of a CCD (charge coupled device) type solid-state imaging element. A P-type well 11 is formed on a silicon substrate 10, and a photodiode 12 and a transfer channel 13 are formed therein. A gate insulating film 14 is formed on the silicon substrate 10.
Are formed. A transfer gate electrode 15 is formed on the transfer channel 13 via a gate insulating film 14.
An insulating film 16 is formed on the transfer gate electrode 15.
Metal wiring 17 is formed thereon. Further, a flattening film 18 is formed thereon. Then, a color filter 19 is formed on it, and a microlens 2 made of a resin material is formed on the color filter 19.
Form 0.

With such a structure, the light condensed by the microlens 20 accumulates electrons in the photodiode 12 and applies a voltage for reading to the transfer gate electrode 13. As a result, electrons are read out from the photodiode 12 to the transfer channel 13. An image can be formed by arranging a plurality of the photodiodes 12 vertically and horizontally. At this time, the P-type diffusion layer 21 is formed on the surface of the photodiode 12. When the photodiode 12 of the N-type diffusion layer is formed in contact with the interface between the silicon substrate 10 and the gate insulating film 14, a leak current occurs due to the effect of the interface state existing at the interface. This causes deterioration of the characteristics of the solid-state image sensor. However, if an attempt is made to introduce the impurity concentration of the P-type diffusion layer 21 by a normal ion implantation method, the ion implantation causes an implantation defect on the surface of the silicon substrate 10,
It causes a leak current. As a result, a sufficient improvement effect cannot be obtained despite the attempt to prevent the generation of leak current. In order to prevent the occurrence of implantation defects due to such ion implantation, a method of performing hydrogen annealing is effective. However, the silicon substrate 1
Regarding the hydrogen atoms introduced into the hydrogen atom 0, the hydrogen atoms escape from the interface between the silicon and the gate insulating film 14 when heat or light is applied to the silicon substrate 10. For this reason, the stability of the device deteriorates. As a result, there arises a problem in the reliability of the manufactured device after being left for a long time.

As another method for reducing the interface state density, a method of introducing a fluorine atom has been proposed. For example, the Japanese Journal of Applied
Physics 1989 Vol. 28, No. 6, page 1041 (Japanese Jounal of Appl. Physics vol.28, no.
6, 1989 p.1041). Also solid
State Electronics Vol. 34, No. 8, pp. 889 (Sol
id-State Electronics vol.34, no.8, p.889) by GS Virdi et al. According to it, it is reported that the interface state density can be reduced by implanting fluorine atoms. In this case, for the implantation of fluorine, BF ₂ and BF ions, which are fluorine molecular ions of boron, are used as ion species, so that fluorine atoms are simultaneously introduced into the silicon substrate 1 together with the boron atoms. For example, ion implantation is performed with BF ₂ at an acceleration energy of 155 keV and a dose amount of 1 × 10 ¹⁴ cm ⁻² . The depth distribution of the impurity concentration of boron and fluorine at this time is 35 ke when boron is ion-implanted alone.
The value is equivalent to the acceleration energy of V, and fluorine is 60 ke
It corresponds to the acceleration energy of V.

[0008]

However, in the structure of the conventional technique, the defect layer due to fluorine is formed to a depth almost equal to the profile of boron. After this,
For example, even if the region where boron is ion-implanted is expanded by heat treatment, the defect layer introduced by fluorine ion-implantation exists at a deeper position. Therefore, a voltage is applied to the N-type diffusion layer of the photodiode 12,
The depletion layer of the N-type diffusion layer extends and reaches the defect layer due to this fluorine. When the depletion layer reaches the defect layer, a leak current is generated from the depletion layer and the device characteristics are significantly deteriorated. In an element in which the leakage current is not a serious problem, ion implantation using BF ₂ can be performed without any problem, but a slight leakage current in a solid-state image sensor, which handles minute electric charges, is dark in the image. It becomes an electric current, which causes a phenomenon that sudden white defects occur in the reproduced image. For this reason, when an image of a low light amount is taken, it becomes a white flaw, and it is not possible to realize a solid-state image sensor that can be used practically. The problem of defects is also observed in the characteristic deterioration due to junction leakage of ordinary bipolar devices and MOS devices, but since it rarely appears as slight unevenness in the image like a solid-state image sensor, the influence of crystal defects on the surface is small. It does not appear directly. That is, the influence of the injection defect in the solid-state imaging device is particularly large as compared with other devices.

As described above, in order to suppress the leak current generated in the photodiode, the interface state density is reduced and the level of injection defects is suppressed. It is necessary to satisfy two problems at the same time.

[0010]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a photodiode of one conductivity type on a semiconductor substrate, and a surface of the semiconductor substrate of the photodiode. And at least a step of forming an impurity layer having a conductivity type opposite to that of the photodiode, and a step of introducing fluorine ions into the impurity layer.

In order to solve the above-mentioned problems, the solid-state image pickup device of the present invention has a semiconductor substrate, a photodiode of one conductivity type formed on the semiconductor substrate, and a predetermined interval with respect to the photodiode. A transfer channel provided and formed on the semiconductor substrate, a transfer gate electrode formed on the semiconductor substrate via a gate insulating film, an interlayer film formed on the transfer gate electrode, and the transfer channel shielded from light. A light-shielding film formed on the interlayer film to form, an interlayer insulating film is formed on the light-shielding film, and a first diffusion layer of a conductivity type opposite to that of the photodiode is formed on the surface of the photodiode. Further, a second diffusion layer containing fluorine as an impurity is formed on the surface of the diffusion layer.

In order to solve the above-mentioned problems, a method of manufacturing a solid-state image pickup device according to the present invention comprises a step of forming a photodiode of one conductivity type on a semiconductor substrate, and a predetermined step for the photodiode on the semiconductor substrate. Forming a transfer channel with a space between them, forming a gate insulating film on the semiconductor substrate, forming a transfer gate electrode on the transfer channel via the gate insulating film, A step of forming an interlayer film on the gate electrode,
Steps of forming an impurity diffusion layer and an impurity of opposite conductivity type to the photodiode at the same time or alternately from the interlayer film to form respective diffusion layers, and forming a light shielding film for shielding the transfer channel. I have it.

[0013]

The N-type impurity is introduced into the P-type substrate or P-well for forming the photodiode. Fluorine ions are introduced under the condition that the influence on the boron-implanted region to be formed later is reduced, that is, under the condition that the portion near the surface of silicon or almost the fluorine remains in the oxide film formed on the surface. That is, the implantation energy is selected such that the projection range of the fluorine is sufficiently smaller than that of the boron implantation to implant the fluorine and the boron. The order of implanting boron and fluorine is not particularly limited, and similar effects can be obtained.

[0014]

1 to 3 are process sectional views in an embodiment of the present invention.

In FIG. 1, a film thickness of 10 is formed on a P-type silicon substrate 21 or a silicon substrate 21 having a P-type well.
An insulating film 22 which is a 0 nm oxide film is formed. After this,
A resist is applied on the insulating film 22, exposed, and developed to form a predetermined resist pattern 23. A phosphorus ion beam 24 is implanted using this resist pattern 23 as a mask. The ion implantation conditions were an acceleration energy of 150 keV and a dose amount of 2 × 10 ¹² cm ^-2 (FIG. 1).

After that, the resist pattern 23 is removed,
Heat treatment is performed. The heat treatment is a phosphorus ion silicon substrate 21.
In order to increase the diffusion distance inside, it is performed at a temperature of 1200 ° C. for about 2 hours. By this heat treatment, the photodiode 25 is formed to a depth of about 1 μm. Here, as another method of forming the photodiode 25, ion implantation may be introduced with a high acceleration energy of about 500 keV. In this case, the heat treatment time can be shortened or the heat treatment temperature can be lowered. The diffusion depth of the photodiode 25 needs to be adjusted according to the sensitivity to the wavelength of the light incident on the photodiode 25. For example, the diffusion depth of the photodiode 25 is about 1 to 2 μm for visible light, and about 3 to 4 μm for infrared light. The depth of the light that penetrates into the silicon substrate 21 and is absorbed differs depending on the wavelength of light. Therefore, in order to increase the sensitivity of the photodiode 25, it is necessary to adjust the depth of the photodiode 25 with light having a desired wavelength.

Next, a resist is applied again on the insulating film 22, exposed and developed to form a predetermined resist pattern (not shown). Boron is ion-implanted using this resist pattern as a mask. In this way, the channel stopper region 26 is formed. After that, the resist pattern is removed. The channel stopper region 26 is formed so as to be electrically separated from an adjacent element. This impurity concentration is set to about 10 ¹⁸ cm ^{-3 in} order to prevent surface inversion. Further, its diffusion depth is about 0.6 μm. The ion implantation conditions at this time are acceleration energy of 40
The keV and dose amount were set to 1 to 3 × 10 ¹³ cm ^-2 . Then, the insulating film 22 is removed. After this, again silicon substrate 2
An insulating film 27, which is an oxide film having a thickness of about 100 nm, is formed on the first insulating film 27. After this, the photodiode 2 on the insulating film 27
A resist pattern or deposited oxide film 28 is formed in a region other than the region where 5 is to be formed. The thickness of the deposited oxide film 28 is about 200 nm. However, as the deposited oxide film 28, C
Not only the oxide film formed by the VD method or the sputtering method but also an oxide film formed by forming a polysilicon film on the silicon substrate 21 and oxidizing the surface thereof may be used. After that, a boron ion beam 29 is ion-implanted using the deposited oxide film 28 as a mask. The ion implantation conditions at this time were an acceleration energy of 50 keV and a dose amount of 1 × 10 ¹⁴ cm ⁻² . Under such conditions, the surface of the photodiode 25 is not exposed to the photodiode 2.
5, a P-type diffusion layer 30 having a conductivity type opposite to that of No. 5 is formed, and the leak current in the photodiode 25 is reduced (FIG. 2). P
The mold diffusion layer 30 is formed by performing a heat treatment at a temperature of 900 ° C. for 30 minutes after the ion implantation. The P-type diffusion layer 30 has a depth of 0.4 μm.

Next, the fluorine ion beam 31 is continuously ion-implanted over the entire surface of the silicon substrate 21. The ion implantation conditions were an acceleration energy of about 20 to 40 keV and a dose amount of about 3 × 10 ^{13 to} 3 × 10 ¹⁴ cm ⁻² . BF ₂ gas is used to inject this fluorine ion beam 31. Thus, on the surface of the photodiode 25 and the surface of the P-type diffusion layer 30, the diffusion layer 32 of fluorine is formed.
To provide. Here, the reason why the fluorine ion implantation is performed under such implantation conditions is to evaluate the leak current dependency on the fluorine implantation amount (FIG. 3).

Here, the acceleration energy is 20 to 40 ke
The reason why V is set is that the amount of defects caused by the ion implantation of fluorine is sufficiently lower in this range than the amount of defects caused by the ion implantation of boron in the previous step. Therefore, the degree of reduction of leakage current due to fluorine can be examined by implanting fluorine ions into a sample that has been ion-implanted under such conditions. In the above case, the boron ion implantation is performed after the fluorine ion implantation. However, even if the order of the fluorine and boron ion implantation is reversed, no problem will occur. .

As another method of independently implanting boron and fluorine as described above, fluorine atoms can be introduced by using molecular ions such as BF ₂ . However, in this method, twice the amount of boron is introduced, and the acceleration energy is inevitably limited to 19/11 times as high as the acceleration energy of boron. For this reason, the degree of freedom in setting the ion implantation amount and the acceleration energy is remarkably lowered, and it becomes difficult to realize the optimum condition for reducing the leak current.

Here, the acceleration energy of boron is 19 /
It is 11 times because the acceleration energy is proportionally distributed according to the mass of each ion. The mass number of fluorine (m _F ) is 19 and that of boron (m _B ) is 11.
When the set acceleration energy is E, the fluorine acceleration energy E _F is given by the following equation.

E _F = (m _F × E) / (2 m _F + m _B ) In the case of using the molecular ions as described above and in the case of independently implanting boron and fluorine, the above-mentioned handling is performed. Difference occurs.

That is, when BF ₂ or BF ion which is a molecular ion is used as an ion species for fluorine ion implantation,
Fluorine atoms are simultaneously introduced into the silicon substrate 1 together with boron atoms. For example, BF ₂ has an acceleration energy of 155
Ion implantation is performed with keV and a dose amount of 1 × 10 ¹⁴ cm ⁻² . At this time, the depth distribution of the impurity concentration of boron and fluorine corresponds to the acceleration energy of 35 keV when boron is ion-implanted alone, and corresponds to the acceleration energy of 60 keV in the case of fluorine. Therefore, fluorine is introduced to a depth almost equal to the impurity concentration distribution of boron, and at the same time, defects due to ion implantation occur deep in the silicon substrate. After that, even if the boron ion-implanted region diffuses and spreads by the heat treatment, the defects introduced by the fluorine ion implantation exist at deeper positions. Therefore, when a voltage is applied to the photodiode 25, a depletion layer is formed in the photodiode 25 and the depletion layer extends. As a result, the depletion layer reaches the defects generated by the fluorine ion implantation. When the depletion layer reaches this defect, a leak current is generated from the depletion layer and the device characteristics are significantly deteriorated. Ion implantation using BF ₂ may be performed in an element in which leak current is hardly a problem, but in a solid-state image sensor, which handles minute charges, for example, the slight leak current causes dark leakage in the image. It becomes an electric current and sudden white scratches occur. For this reason,
It is easier to use the method of separately implanting boron and fluorine. As shown in FIG.
It is indispensable to form the P type diffusion layer 30 on the surface of the above in order to prevent the depletion layer from electrically extending to the surface side as described above.

The lateral diffusion width of the N-type diffusion layer, which is the photodiode 25, in the vicinity of the surface of the silicon substrate 21 and that of the P-type diffusion layer 30 indicate that both ends of the lateral diffusion region in the drawing. Both diffusion layers match, but they do not necessarily have to match. As long as the P-type diffusion layer 30 formed on the surface of the silicon substrate 21 can cover the N-type diffusion layer, which is the photodiode 25, so that the dark portion of the N-type diffusion layer does not exist on the surface, depletion occurs. The layer does not extend to the surface, so that problems do not occur. If the depletion layer extends to the surface, the leak current will increase due to the interface state existing on the surface of the silicon substrate 21.

The leakage current characteristics of the diode formed by the above method were evaluated. The result is shown in Figure 4.
Shown in. The vertical axis represents the leak current, and the horizontal axis represents the acceleration energy during fluorine ion implantation. Fluorine ion implantation was not performed on the comparative sample in the figure.

From the above, it was confirmed that the leakage current of the diode was remarkably reduced in the sample in which fluorine ions were implanted. A sample having a high dose amount and a high acceleration energy in fluorine ion implantation has a large leak current as compared with a sample having an acceleration energy of 20 keV or 30 keV. However, in the sample in which the dose amount was reduced to 3 × 10 ¹³ cm ⁻² , the effect of reducing the leak current was recognized even at 40 keV.

The reason for this will be described with reference to FIGS. 5 and 6. In FIG. 5, the horizontal axis represents the depth from the silicon substrate, and the vertical axis represents the impurity concentration. In FIG. 6, the horizontal axis represents the depth from the silicon substrate, and the vertical axis represents the defect amount. In both cases, an oxide film having a thickness of about 0.1 μm is deposited on the silicon substrate.

When the acceleration energy is 20 keV or less,
Most of the ion-implanted fluorine is introduced into the oxide film on the silicon substrate, and almost none reaches the silicon substrate. Therefore, the leakage current cannot be reduced with an acceleration energy of 20 keV or less. However, when the thickness of the oxide film that is the surface insulating film becomes thin, fluorine is introduced into the silicon substrate even with this acceleration energy. For example, if the film thickness of the oxide film is 30 nm, it is possible to reduce the leak current at that time even when the acceleration energy is about 15 keV.

In FIG. 5, the acceleration energy is 50 keV and the dose is 3 × 10 ¹⁴ c through the oxide film having a thickness of 0.1 μm.
The distribution of each impurity is shown when boron is ion-implanted at m ⁻² and fluorine is further ion-implanted at an acceleration energy of 30 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . From this figure, in FIG. 2 above, the P-type diffusion layer 3 is formed on the surface of the silicon substrate 21.
It can be seen that the fluorine diffusion layer 32 is shallowly formed on the surface of the silicon substrate 21 with respect to the distribution of boron ion-implanted to form 0.

FIG. 6 shows acceleration energies of 40 keV and 20 k.
The results obtained by calculating the defect amount when ion-implanting fluorine with a dose amount of 1 × 10 ¹⁴ cm ⁻² at eV by using a Monte Carlo simulation method are shown. With the acceleration energy of 40 keV, many defects are formed not only in the oxide film but also in the silicon substrate. The defects formed here can be recovered to some extent by a heat treatment that is subsequently performed after the ion implantation. However, the amount of residual defects that cannot be recovered by the heat treatment is proportional to the amount of primary defects generated during ion implantation. Therefore, the lower the primary defect is, the less the generation of secondary defects that causes it is, and as a result, the increase in leak current can be prevented. In FIG. 6, it can be seen that the defect amount is reduced by about two digits when the acceleration energy is lowered from 40 keV to 20 keV.
Therefore, it is necessary to prevent defects caused by fluorine ion implantation from being introduced into the silicon substrate as much as possible. In particular, it is necessary that the defects generated by the ion implantation of fluorine be introduced to the extent that they do not affect the defects generated by the ion implantation of boron. The amount of defects in the silicon substrate is the sum of defects caused by fluorine ion implantation and defects caused by boron ion implantation.
In this case, in order to make the amount of defects caused by the ion implantation of fluorine particularly negligible without causing an increase in the leak current, the amount of fluorine to be implanted is smaller than the amount of boron by one digit or more.

From this result, it is considered that since fluorine is introduced into the shallow portion of the silicon substrate, it does not affect the junction of the P type diffusion layer 30 formed on the surface of the photodiode 25 as shown in FIG. To be

However, when it is used for a solid-state image pickup device, there is a problem that minute residual defects which are not measured in FIG. 2 exist. If it is at the junction of the P-type diffusion layer 30, the depletion layer of the photodiode comes into contact with the defect when driving the solid-state imaging device, and the leak current increases. For this reason, the leakage current causes white scratches. Thus, it is important to form the defects caused by the ion implantation in a portion as shallow as possible from the substrate surface. However, it is when the depletion layer comes into contact with the defect that the defect has an adverse effect. Therefore, the defect caused by the fluorine ion implantation is caused by the P-type diffusion layer 3
It does not have to be formed simply away from the position of the 0 joint.

Hereinafter, FIG. 7 shows a C manufactured using the above technique.
It is sectional drawing of a CD solid-state imaging device. In particular, CCD (char
1 is a cross-sectional structure of a photodiode and a readout section of a solid-state imaging device of a ge coupled device) type.

First, the N-type semiconductor substrate 41 has a plane orientation (10
0) and the impurity concentration is about 10 ¹⁴ cm ⁻³ . A first P-type diffusion layer 42 is formed on the N-type semiconductor substrate 41. The depth of the first P-type diffusion layer 42 is about 5 μm. The impurity concentration of the first P-type diffusion layer 42 is about 10 ¹⁵ cm.
^-3 . The first P-type diffusion layer 42 is the photodiode 4
It is provided for discharging unnecessary electric charges at 3. That is, the photodiode 43 is formed on the N-type semiconductor substrate 41 as an N-type diffusion layer. In the photodiode 43, an electric charge (photocarrier) is formed by the light incident from the outside and is temporarily stored inside. When the charge is generated in a large amount and becomes larger than the charge amount that can be accumulated in the photodiode 43, the charge flows from the photodiode 43 to another region. Such charges cause blooming when they enter the transfer channel 44 formed of the N-type diffusion layer. The occurrence of such blooming can be prevented by forming the first P-type diffusion layer 42. The first P-type diffusion layer 42 is fixed to zero volt. Therefore, in the potential distribution formed in these regions, the charges generated in the photodiode 43 pass through the first P-type diffusion layer 42 and are discharged to the N-type semiconductor substrate 41. When the impurity concentration of the first P-type diffusion layer 42 is set to the above value, the photodiode 43 can be easily depleted when the solid-state imaging device operates, and the photoelectric conversion signal amount can be increased. You can The depth of the first P-type diffusion layer 42 is determined by the depth of the photodiode 43 and the breakdown voltage between them. Photodiode 43
The depth of about 2 μm is required to obtain sufficient photoelectric conversion efficiency when light in the visible light region is incident.

An N-type diffusion layer, which is a photodiode 43, is formed on the first P-type diffusion layer 42. When light is incident on the photodiode 43, electron pairs of electrons and holes are generated in the depletion layer of the photodiode 43. The electrons become signal charges through the adjacent transfer channels 44. The holes are taken out of the N-type semiconductor substrate 41 through the first P-type diffusion layer 42. In this way
The photodiode 43 converts incident light into signal charge. A second P-type diffusion layer 45 is formed on the surface of the photodiode 43. The reason for forming the second P-type diffusion layer 45 is that when the photodiode 43 of the N-type diffusion layer is formed in contact with the interface between the semiconductor substrate 41 and the gate insulating film 50, the interface state existing at the interface is present. A current is generated under the influence of, and the characteristics of the element are deteriorated. The second P-type diffusion layer 45 having a relatively high concentration is formed so that the depletion layer does not reach the interface between the silicon and the insulating film. The second P-type diffusion layer 45 needs boron with an impurity concentration exceeding 10 ¹⁷ cm ^-3 . If it is attempted to introduce such an impurity concentration by a normal ion implantation method, the ion implantation causes an implantation defect on the surface of the semiconductor substrate 41, which causes a leak current. As a result, a sufficient improvement effect cannot be obtained despite the attempt to prevent the generation of dark current. There is a method of performing hydrogen annealing in order to prevent the generation of implantation defects due to such ion implantation. But,
The hydrogen atoms introduced into the semiconductor substrate 41 by hydrogen annealing have no effect because the hydrogen atoms escape from the interface between the silicon substrate and the oxide film when heat or light is applied to the semiconductor substrate 41, resulting in poor stability. Therefore, there arises a problem in the reliability of the device manufactured using this after being left for a long time. Further, a fluorine diffusion layer 46 is formed on the surfaces of the second P-type diffusion layer 45 and the photodiode 43. The fluorine diffusion layer 46 can reduce an increase in leak current due to a defect generated in the second P-type diffusion layer 45.

A third P-type diffusion layer 47 is formed in the first P-type diffusion layer 42. Third P-type diffusion layer 4
7 has a function of preventing charges, which become noise, of signals generated in the N-type semiconductor substrate 41 from diffusing into the transfer channel 44. Here, the diffusion depth of the third P-type diffusion layer 47 is about 1 μm. The impurity concentration of the third P-type diffusion layer 47 is 10 ¹⁶ cm ^-3 .

The third P-type diffusion layer 47 is used to surround the transfer channel 44 formed of the N-type diffusion layer. Generally, such a structure is called a Hi-C structure. Third P-type diffusion layer 47
When the diffusion depth of is deepened by heat treatment, the diffusion in the lateral direction simultaneously proceeds. Therefore, the third P-type diffusion layer 47 reaches the N-type diffusion layer of the photodiode 43. If the third P-type diffusion layer 47 enters the photodiode 43, the photoelectric conversion output will decrease. Transfer channel 4
Reference numeral 4 is a transfer area for transferring the signal charge formed by the photodiode 43 to a predetermined area.

Here, the diffusion depth of the transfer channel 44 is about 0.5 μm. The impurity concentration of the transfer channel 44 is 10 ¹⁶ to 10 ¹⁷ cm ⁻³ .

In order to realize the above Hi-C structure, it is necessary to make the third P-type diffusion layer 47 wider than the transfer channel 44.

When the signal charge generated in the photodiode 43 is read out to the transfer channel 44, the potential of the transfer channel 44 is made lower than the potential of the photodiode 43. Further, when the signal charge carried to the transfer channel 44 flows back to the photodiode 43 or the signal charge exists in the transfer channel 44, the signal charge formed by the photodiode 43 is transferred to the transfer channel 44. It is necessary to prevent it from flowing. Therefore, the fourth P-type diffusion layer 48 for controlling the potential at the time of reading is formed between the photodiode 43 and the transfer channel 44. When the signal charge is transferred from the photodiode 43 to the transfer channel 44, the potential in the fourth P-type diffusion layer 48 is lower than the potential of the photodiode 43 and is the same as or slightly higher than the potential of the transfer channel 44. Is controlled. When the signal charge is accumulated in the transfer channel 44, the potential of the fourth P-type diffusion layer 48 is higher than the potential of the photodiode 43 and the potential of the transfer channel 44 is set so that the signal charge does not flow back to the photodiode 43. Controlled to be higher.

Here, the diffusion layer depth of the fourth P-type diffusion layer 48 is about 1 μm. The surface concentration of the fourth P type diffusion layer 48 on the surface of the silicon substrate 41 is 10 ¹⁶ to 10 ¹⁷ cm ^−3.
Is. When the voltage of the driving pulse for operating the solid-state imaging device is 0 V or 15 V, it is possible to prevent the electric charge from flowing backward from the transfer channel 44 to the photodiode 43, or
Alternatively, it is necessary that the charges flow from the photodiode 43 into the transfer channel 44. Therefore, the diffusion layer depth and the impurity concentration of the fourth P-type diffusion layer 48 are set so that the threshold voltage can have the optimum potential distribution in each state. The width of the fourth P-type diffusion layer 48 is preferably about 1 μm or less. If the width of the fourth P-type diffusion layer 48 is larger than 1 μm, the gm characteristic of the transistor deteriorates. If the gm characteristic deteriorates, it becomes impossible to completely read out the signal charges accumulated in the photodiode 43. On the contrary, when the width of the fourth P-type diffusion layer 48 is narrower than about 1 μm, the short channel effect occurs. Due to the short channel effect, punch through easily occurs, and as a result, the photodiode 43
The photoelectric conversion output value of becomes small.

In the solid-state image pickup device, the photodiode 43 and the transfer channel 44 are paired and are formed in a matrix. A fifth P-type diffusion layer 49 is formed to electrically separate this pair from the adjacent pair. The fifth P-type diffusion layer 49 is formed by ion implantation. Here, the depth of the fifth P-type diffusion layer 49 is about 1 μm.
Is. The surface concentration of the fifth P-type diffusion layer 49 is 10
^{It is 17} to 10 ¹⁸ cm ^-3 .

The surface concentration of the fifth P-type diffusion layer 49 needs to be set within the above range in order to prevent the signal charges accumulated in the adjacent photodiodes 43 from flowing in. When the surface concentration is less than 10 ¹⁷ cm ⁻³ , the signal charges of the adjacent photodiodes 43 flow in. When the surface concentration is higher than 10 ¹⁸ cm ^-3 ,
The narrow channel effect occurs in the adjacent transfer channel 44. Transfer channel 4 when the narrow channel effect occurs
The transfer capacity of No. 4 is reduced. For this reason, the dynamic range of the solid-state imaging device becomes small, and the transfer efficiency deteriorates.

The width of the fifth P-type diffusion layer 49 is preferably about 1 μm or less. If the width of the fifth P-type diffusion layer 49 is 1
If it is wider than μm, the transfer area of the transfer channel 44 is reduced. That is, it becomes impossible to completely read out the signal charges accumulated in the photodiode 43. On the contrary, when the width of the fifth P-type diffusion layer 49 is narrower than 1 μm, the short channel effect occurs. Adjacent photodiodes 43 due to the short channel effect
Punch-through easily occurs between the transfer channel 44 and the transfer channel 44. As a result, the information of the adjacent photodiodes 43 is read and the resolution is lowered. Furthermore, the output of the photodiode 43 is reduced.

A gate insulating film 50 is grown on the N-type semiconductor substrate 41 by a silicon oxide film. The gate insulating film 50 is formed by a pyro oxidation method. Gate insulating film 5
The film thickness of 0 is about 50 nm or more. The film thickness of the gate insulating film 50 is preferably set to 50 nm or more in order to enhance transfer efficiency by utilizing the fringing effect.

The transfer gate electrode 51 is formed by patterning polysilicon grown by the low pressure CVD method. The sheet resistance of the transfer gate electrode 51 is several tens Ω. The film thickness of the transfer gate electrode 51 is about 500 nm. The transfer gate electrode 51 is used as an electrode for applying a drive pulse for reading out and transferring the signal charge formed by the photodiode 43 to the transfer channel 44. As described above, it is desirable that the transfer gate electrode 51 has a resistance as low as possible. However, if the phosphorus doping amount is increased for the purpose of lowering the resistance, the breakdown voltage of the interlayer film 52 formed by oxidizing the surface of the transfer gate electrode 51 is deteriorated, so the phosphorus doping amount is preferably set to the above value. An interlayer film 52 made of a polysilicon oxide film is grown on the surface of the transfer gate electrode 51.

The interlayer film 52 is grown by oxidizing the surface of the transfer gate electrode 51 by a pyrooxidation method. Interlayer film 5
The film thickness of 2 is about 200 nm. The interlayer film 52 is formed to secure the breakdown voltage of the interlayer film. Further, due to the etching residue of the polysilicon film generated by the etching when forming the transfer gate electrode 51, a leak occurs through the etching residue of the polysilicon film when a drive voltage is applied. Leakage can be prevented by burning off the polysilicon etching residue when forming the interlayer film 52. Since the four-phase drive pulse applied to the transfer gate electrode 51 changes the level of -7V, 0V, and + 15V, the interlayer film 52 has a breakdown voltage of 22V or more of the maximum voltage difference.

An interlayer film 53 is formed of a silicon oxide film on the surface of the interlayer film 52. The film thickness of the interlayer film 53 is about 100 nm. The interlayer film 53 is formed by the CVD method. The interlayer film 53 is formed to prevent the breakdown voltage from locally weakening due to the presence of pinholes or the like in the polysilicon oxide film forming the interlayer film 52.

A light shielding film 54 is formed in order to prevent light from entering the transfer channel 44 and becoming a smear component. The interlayer film 5 is formed on the light-shielding film 54 and in the opening region of the light-shielding film 54.
An interlayer insulating film 55 is provided on the upper side. The film thickness of the interlayer insulating film 55 is 200 nm.

8 to 13 are sectional views of manufacturing steps when the above-described technique is applied to a CCD solid-state image pickup device.

First, a thermal oxide film 62 of about 100 nm is formed on the main surface of N type semiconductor substrate 61. A photoresist is applied on the N-type semiconductor substrate 61 (not shown), and the first P-type diffusion layer 63 region is exposed and developed to form a resist pattern. Boron ions are implanted using this resist pattern as a mask. The ion implantation conditions at this time were an accelerating voltage of 100 keV and an implantation dose of about 10 ¹² cm ^-2 . After that, heat treatment is performed in an N ₂ atmosphere at a temperature of 1100 ° C. or higher for several hours to diffuse the implanted boron into the N-type semiconductor substrate 61 to a depth of about 5 μm to form a first P-type diffusion layer 63. . At the same time, this heat treatment activates the ion-implanted boron (FIG. 8).

Next, a photoresist is applied on the N-type semiconductor substrate 61 (not shown), and a region where the photodiode 64 is to be formed is exposed and developed to form a resist pattern. Phosphorus ions are implanted using this resist pattern as a mask. The ion implantation condition at this time is that the acceleration voltage is several tens.
The injection amount was set to 0 keV and the injection amount was set to about 10 ¹² cm ^-2 . After this, N
₂ Heat treatment at a temperature of 1000 ° C. or higher in an atmosphere. As a result, the implantation depth of the photodiode 64 becomes about 2 μm. In this way, the photodiode 64 is formed in the predetermined region of the first P-type diffusion layer 63.

Next, the resist on the N-type semiconductor substrate 61 is removed, and a photoresist is applied again on the N-type semiconductor substrate 61 (not shown). A region of the third P-type diffusion layer 65 is exposed and developed to form a resist pattern. Boron ions are implanted using this resist pattern as a mask. The ion implantation conditions at this time were an accelerating voltage of about 100 keV and an implanting amount of 10 ¹² cm ^-2 . As a result, the diffusion depth of the third P-type diffusion layer 65 finally becomes about 1 μm. Thus, the first P-type diffusion layer 63, which is a P-type well,
The third P-type diffusion layer 6 for preventing the electric charge that becomes noise generated in the N-type semiconductor substrate 61 from diffusing into the transfer channel.
5 is formed.

Further, the resist pattern on the N-type semiconductor substrate 61 is removed, and a photoresist is applied on the N-type semiconductor substrate 61 (not shown). The transfer channel 66 area is exposed and developed to form a resist pattern. Phosphorus ions are implanted using this resist pattern as a mask. The ion implantation condition at this time is that the acceleration voltage is about 100 keV,
The injection amount was 10 ¹² cm ^-2 . As a result, the diffusion depth of the transfer channel 66 becomes about 0.5 μm. In this way, the transfer channel 66 is formed.

Next, the photoresist on the N-type semiconductor substrate 61 is removed and the N-type semiconductor substrate 61 is again coated with the photoresist (not shown). The region of the fourth P-type diffusion layer 67 is exposed and developed to form a resist pattern. Boron ions are implanted using this resist pattern as a mask. The conditions for ion implantation at this time are that the acceleration voltage is several tens keV,
The injection amount was 10 ¹² cm ^-2 . As a result, the implantation depth of the fourth P-type diffusion layer 67 becomes about 1 μm. By injecting under such conditions, the threshold voltage between the photodiode 64 and the transfer channel 66 can be controlled. In this way, the fourth P-type diffusion layer 67 for controlling the potential for reading out photocarriers from the photodiode 64 to the transfer channel 66 is formed between the photodiode 64 and the transfer channel 66.

Next, the photoresist on the N-type semiconductor substrate 61 is removed, and the photoresist is applied again on the N-type semiconductor substrate 61 (not shown). A region of the fifth P-type diffusion layer 68 is exposed and developed to form a resist pattern. Boron ions are implanted into this resist pattern. The ion implantation conditions at this time were an accelerating voltage of several tens keV and an implantation amount of about 10 ¹³ cm ^-2 . As a result, the implantation depth of the fifth P-type diffusion layer 68 becomes about 1 μm. Since the fifth P-type diffusion layer 68 separates from the adjacent element, the threshold voltage is raised so as not to conduct with the voltage applied during operation. For this purpose, the impurity concentration of the fifth P type diffusion layer 68 is set relatively high. In particular, the fourth P-type diffusion layer 67
It should be higher than the impurity concentration of (FIG. 9).

Next, a silicon oxide film as the gate insulating film 69 is grown to a thickness of about 50 nm by the pyro oxidation method. A polysilicon film is grown on it by about 600 nm by a low pressure CVD method, and its sheet resistance is about 10 Ω by phosphorus doping.
To A photoresist is applied on this polysilicon film, and exposure and development are performed to form a resist pattern of the transfer gate electrode 70. Using this resist pattern as a mask, the polysilicon film is subjected to reactive ion etching in a mixed atmosphere of a fluorine-based gas and a chlorofluorocarbon-based gas to form a transfer gate electrode 60.

After that, the resist pattern is removed and an interlayer film 71 having a film thickness of about 300 nm is grown. From above, a second P-type diffusion layer 73 having a high surface concentration is formed by the boron ion beam 72. At this time, both the interlayer film 71 formed by oxidizing the polysilicon of the transfer gate electrode 70 and the transfer gate electrode 70 are used as masks to inject into the openings (FIG. 10).

Then, a fluorine diffusion layer 75 is formed by implanting with a fluorine ion beam 74 using the same mask.
After that, the third P-type diffusion layer 73 is thermally diffused by heat treatment.

The implantation of boron at this time was performed under the conditions shown above. Regarding the fluorine ion implantation, the acceleration energy is 30 keV and the dose is 3 × 10 ¹³ cm.
^-2 (Fig. 11).

Next, an interlayer film 76 which is a silicon oxide film is grown on the entire surface, and an aluminum film which is a light shielding film 77 is further grown. The light shielding film 77 is deposited by the sputtering method. A photoresist is applied onto the aluminum film thus grown (not shown), and the light-shielding film 7 is exposed and developed.
A resist pattern of No. 7 is formed. Using this resist pattern as a mask, reactive ion etching is performed in a mixed atmosphere of a fluorine-based gas and a chlorofluorocarbon-based gas to form a light shielding film 77 (FIG. 12).

Next, by an atmospheric pressure CVD method using a mixed gas of silane gas, phosphine gas and diborane gas,
A BPSG film to be the interlayer insulating film 78 is formed. The mixing ratio of the silane gas, the phosphine gas, and the diborane gas was set so that the concentrations of boron and phosphorus in the BPSG film were about 3 wt% and about 6 wt%, respectively.
The film thickness of this BPSG film is about 600 nm. Then N
In addition to a heat treatment of 900 ° C. in a ₂ atmosphere to cause a flow in the BPSG film, to planarize the top surface of the interlayer insulating film 78. When the heat treatment is performed at a temperature of 900 ° C. or more, the impurity concentration distribution of the diffusion layer formed on the N-type semiconductor substrate 51 changes so far, and the read characteristics and the saturation output value of the solid-state imaging device are reduced.

Next, the color filter 7 is formed on the interlayer insulating film 78.
9 is formed, and the micro lens 80 is further formed on the uppermost part (FIG. 13).

The number of white scratches generated with and without applying fluorine ion implantation to such a CCD solid-state imaging device is
It was confirmed that the amount of fluorine introduced was 1/3 that of the comparative product in which no fluorine was introduced. Also, 1 × 1
The effect was recognized even at a dose of 0 ¹⁴ cm ^-2 . However,
It was confirmed that with an acceleration energy of 40 keV, white scratches increased when the dose amount of 1 × 10 ¹⁴ cm ⁻² was exceeded.

[0065]

According to the present invention, by injecting fluorine into the boron depletion layer without the influence of injection defects, it is possible to reduce the leak current by reducing the interface state.

[Brief description of drawings]

1A to 1C are cross-sectional views in order of steps, illustrating a method for manufacturing a semiconductor device of the present invention.

2A to 2C are cross-sectional views in order of the processes, for illustrating a method for manufacturing a semiconductor device of the present invention.

3A to 3D are cross-sectional views in order of the processes, for illustrating the method for manufacturing the semiconductor device of the present invention.

FIG. 4 is a diagram showing a relationship between fluorine implantation energy and leakage current.

FIG. 5 is a diagram showing an impurity concentration distribution in a silicon substrate when boron and fluorine ions are implanted.

FIG. 6 is a diagram showing the distribution of defects in the depth direction in fluorine ion implantation.

FIG. 7 is an element cross-sectional view for explaining the solid-state imaging device of the present invention.

8A to 8C are cross-sectional views in order of the steps, for explaining the method for manufacturing the solid-state imaging device of the present invention.

9A to 9C are sectional views in order of the processes, for explaining the method for manufacturing the solid-state imaging device of the present invention.

10A to 10C are cross-sectional views in order of the processes, for illustrating the method for manufacturing the solid-state imaging device of the present invention.

11A to 11C are cross-sectional views in order of the processes, for explaining the method for manufacturing the solid-state imaging device of the present invention.

FIG. 12 is a cross-sectional view in order of the steps, for explaining the method for manufacturing the solid-state imaging device of the present invention.

13A to 13C are cross-sectional views in order of the steps, for illustrating the method for manufacturing the solid-state imaging device of the present invention.

FIG. 14 is a cross-sectional view in order of the processes, illustrating a conventional method for manufacturing a semiconductor device.

FIG. 15 is a cross-sectional view in order of the steps, illustrating a conventional method for manufacturing a semiconductor device.

FIG. 16 is an element cross-sectional view for explaining a conventional solid-state imaging device.

[Explanation of symbols]

 21 Silicon Substrate 22 Insulating Film 23 Resist Pattern 24 Phosphorus Ion Beam 25 Photodiode 26 Channel Stopper Region 27 Insulating Film 28 Deposited Oxide Film 29 Boron Ion Beam 30 P-Type Diffusion Layer 31 Fluorine Ion Beam 32 Diffusion Layer

Claims (13)

[Claims] 1. A step of forming a photodiode of one conductivity type on a semiconductor substrate, a step of forming a diffusion layer of a conductivity type opposite to that of the photodiode on the surface of the semiconductor substrate of the photodiode, and a step of forming a diffusion layer in the diffusion layer. A method of manufacturing a semiconductor device, comprising at least a step of introducing fluorine ions. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the introduction of the fluorine ions does not deteriorate the electrical characteristics of the photodiode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of introducing the fluorine ions and the step of forming the diffusion layer are continuously performed without a high temperature heat treatment. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the fluorine ions are introduced into the surface of the semiconductor substrate in the diffusion layer. 5. The introduction of the fluorine ions is carried out by ion implantation through an insulating film formed on the semiconductor substrate, and at least the maximum value of the implantation amount of the fluorine ions by the ion implantation is within the insulating film. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the acceleration energy at the position of is used. 6. The semiconductor device according to claim 2, wherein the amount of defects generated in the semiconductor substrate by the ion implantation is sufficiently smaller than the amount of defects generated when the diffusion layer is formed. Manufacturing method. 7. A semiconductor substrate, a photodiode of one conductivity type formed on the semiconductor substrate, a transfer channel formed on the semiconductor substrate at a predetermined distance from the photodiode, and the semiconductor substrate. A transfer gate electrode formed over the gate insulating film, an interlayer film formed on the transfer gate electrode, a light shielding film formed on the interlayer film for shielding the transfer channel, and the light shielding film An interlayer insulating film is formed thereon, a first diffusion layer having a conductivity type opposite to that of the photodiode is formed on the surface of the photodiode, and a second diffusion layer having fluorine as an impurity is formed on the surface of the diffusion layer. A solid-state image pickup device, comprising: 8. The voltage applied to the transfer gate electrode is 4
The solid-state imaging device according to claim 7, wherein the solid-state imaging device operates with a phase drive pulse. 9. The solid-state image pickup device according to claim 7, wherein the P-type diffusion layer is provided so as to surround the transfer channel and has a Hi-C structure. 10. A step of forming a photodiode of one conductivity type on a semiconductor substrate, a step of forming a transfer channel on the semiconductor substrate with a predetermined distance from the photodiode, and a gate on the semiconductor substrate. Forming an insulating film; forming a transfer gate electrode on the transfer channel via the gate insulating film; forming an interlayer film on the transfer gate electrode; The present invention is characterized by including a step of forming a diffusion layer by ion-implanting an impurity of opposite conductivity type with a diode and fluorine at the same time or alternately, and a step of forming a light-shielding film that shields the transfer channel. Manufacturing method of solid-state imaging device. 11. The method of manufacturing a solid-state image pickup device according to claim 10, wherein electrical characteristics of the photodiode are not deteriorated by the fluorine ion implantation. 12. The method of manufacturing a solid-state image pickup device according to claim 10, wherein the depth of the diffusion layer formed by ion implantation of fluorine is shallower than that of the diffusion layer formed by ion implantation of impurities of the opposite conductivity type. . 13. The solid according to claim 10, wherein at least the position of the maximum value of the ion implantation amount of fluorine by the ion implantation of fluorine is at an acceleration energy that is a position in the gate insulating film. Manufacturing method of imaging device.