JPH06342798A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device which is less deteriorated in electrical properties due to that heavy metal present close to a surface is gettered by a gettering layer and crystal defects generated in an electrically active region. CONSTITUTION:A first P-type well 11 is formed on an N-type Si substrate 10. A gettering layer 17 is formed by implanting ions through a resist mask in a region deeper than a channel stop region 5 which is used for isolating a photodiode 13 from a vertical CCD 14 formed inside the first P-type well, wherein the resist mask concerned is used for the formation of the channel stop region 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of gettering a semiconductor silicon substrate.

[0002]

2. Description of the Related Art The structure and manufacturing method of a general silicon LSI is based on a MOS in which an isolation region is formed using a LOCOS film.
The structure will be described as an example with reference to the drawings. Figure 1
1 and 12 show a conventional method for manufacturing a semiconductor device having a MOS structure.

First, as shown in FIG. 11, an oxide film 2 is formed on a p-type silicon (hereinafter referred to as Si) substrate 1, and a nitride film 3 is further formed on the oxide film 2 by a low pressure CVD method. To form. Next, the nitride film 3 in the isolation region is removed by dry etching using the resist mask 4, and the channel stop region 5 is formed by boron implantation using the resist mask 4.

Next, as shown in FIG. 12, after removing the resist mask 4, the region where the nitride film 3 is removed is oxidized to form a LOCOS film 6. Then, the nitride film 3 and the oxide film 2 are removed by the wet etching method to form the gate oxide film 7. Next, a polysilicon film 8 is formed on the gate oxide film 7, electrodes are formed on the polysilicon film 8 by a dry etching method, and then source / drain regions 9 are formed by arsenic implantation.

FIG. 12 manufactured using such a method.
The structure of the semiconductor device shown in (1) becomes the element cross-sectional structure of the semiconductor device having the conventional MOS structure.

Next, a conventional structure and manufacturing method of a solid-state image pickup device will be described below with reference to the drawings. 13 to 1
Photodiode and vertical charge transfer unit (hereinafter vertical CC
Sectional drawing in order of the process of the conventional manufacturing method of part D) is shown.

First, as shown in FIG. 13, a first p-type well 11 is formed in an n-type Si substrate 10 by using boron implantation, and then a heat treatment is performed at a temperature of 1100 ° C. or higher. Then, the second p-type well 12 is formed by boron implantation. Then, the n-type region which is the photodiode 13 is formed by phosphorus implantation. After forming the photodiode 13, a vertical C is formed in the second p-type well 12.
Form CD 14.

Thereafter, as shown in FIG. 14, the vertical CCD 1
4 and the photodiode 13 and a channel stop region 5 for separating between the adjacent photodiodes 13 are formed by boron implantation, and a channel dope region 15 for controlling the threshold voltage (Vt) of the read region.
Are formed by boron implantation.

Next, as shown in FIG. 15, the gate oxide film 7 is formed.
Then, a polysilicon film 8 is formed on the gate oxide film 7, an electrode is formed on the polysilicon film 8 by a dry etching method, and charges of the photodiode 13 are vertically CC
The structure is such that the data is read to the D section. Thereafter, as a countermeasure against dark current, a buried photodiode p ⁺ layer 16 is formed by boron implantation at the interface between the photodiode 13 and the gate oxide film 7.

FIG. 15 manufactured by using such a method.
The structure of the semiconductor device shown in (1) becomes the element cross-sectional structure of the conventional solid-state imaging device.

Here, as a method for performing gettering, the 1991 Spring Applied Physics Related Technology Lecture 31a-X
As reported in -8, there is a method of forming a gettering layer on the entire surface of a semiconductor substrate by using high energy implantation. However, this gettering method is directly applied to the conventional method for manufacturing a MOS structure or a solid-state imaging device. When applied, the gettering ability of the heavy metal is enhanced, but a gettering layer due to a crystal defect is formed in the electrically active region of the semiconductor device, so that the crystal defect causes a leak current (dark current in the case of a solid-state imaging device). And the electrical characteristics of the semiconductor device are deteriorated.

[0012]

In the conventional method, the gettering layer is formed on the entire surface, and the gettering layer in the electrically active region rather deteriorates the electrical characteristics.

The present invention solves the above-mentioned conventional problems by forming a gettering layer of a heavy metal near the surface in a region deeper than a channel stop region which is an electrically inactive region. An object of the present invention is to provide a semiconductor device in which deterioration of electric characteristics due to gettering of heavy metal near the surface is reduced and deterioration of electric characteristics due to crystal defects formed in an electrically active region is eliminated.

[0014]

In order to achieve this object, a semiconductor device of the present invention has an element isolation region formed on a semiconductor substrate and a gettering layer formed immediately below the element isolation region. An electrically active region is formed immediately below the element isolation region, and the gettering layer is formed at a position deeper than the electrically active region.

In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a plurality of photodiode parts and a plurality of charge transfer part parts in an array on a semiconductor substrate, Forming a channel stop region between the charge transfer portion and the photodiode and between the photodiode and a photodiode adjacent thereto; forming a gettering layer at a position deeper than the channel stop region; And a step of forming an element isolation region in the channel stop region. Further, in the step of forming the channel stop region and the gettering layer, they are formed by ion implantation using the same resist mask.

After the photodiodes and the charge transfer portions are formed in an array, a resist mask is formed between the charge transfer portions and the photodiodes and between the photodiodes and the photodiodes adjacent to the photodiodes to stop the channel. A region is formed by ion implantation, and a gettering layer is formed in a region deeper than the channel stop region by continuing the resist mask as a mask.

[0017]

With the above structure, the gettering layer of heavy metal near the surface is formed in a region deeper than the channel stop region which is an electrically inactive region.
Deterioration of electrical characteristics due to crystal defects can be eliminated, and deterioration of electrical characteristics can be suppressed by heavy metal gettering by the gettering layer.

[0018]

1 is a cross-sectional view of an element of a structure of a semiconductor device having a MOS structure to which the present invention is applied. An oxide film 2 is formed on a p-type Si substrate 1, and a nitride film 3 is further formed on the oxide film 2 by a low pressure CVD method. Next, the nitride film 3 in the isolation region is removed by dry etching using the resist mask 4, and the channel stop region 5 is accelerated by the resist mask 4 at an acceleration energy of 50 to 100 ke.
V is formed by boron implantation with an implantation amount of about 10 ¹³ cm ^-2 . Next, after removing the resist mask 4, the region where the nitride film 3 is removed is oxidized to form a LOCOS film 6. Then, the nitride film 3 and the oxide film 2 are removed by the wet etching method to form the gate oxide film 7. Next, a polysilicon film 8 is formed on the gate oxide film 7, and an electrode is formed on the polysilicon film 8 by a dry etching method.
It is formed by arsenic implantation of 0 to 50 keV and an implantation dose of about 10 ¹⁵ cm ^-2 . Furthermore, the gettering layer 17
Is located immediately below the channel stop region 5 for element isolation located under the LOCOS film 6, and is not formed under the MOS gate (under the polysilicon film 8) or the source / drain region 9. Gettering layer 1 due to this structure
The injection defect in 7 is located in the electrically inactive region, and the generation of leak current due to the injection defect can be suppressed.

Next, a method of manufacturing a semiconductor device having a structure as shown in FIG. 1 will be described with reference to the drawings.

2 to 4 show a MOS according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view in order of the steps of a method for manufacturing a semiconductor device having a structure.

First, as shown in FIG. 2, a p-type Si substrate 1
The oxide film 2 is formed on the oxide film 2, and the nitride film 3 is further formed on the oxide film 2.
Are formed by using the low pressure CVD method. Next, the nitride film 3 in the isolation region is removed by dry etching using the resist mask 4, and the channel stop region 5 is accelerated by the resist mask 4 at an acceleration energy of 50 to 100 ke.
V is formed by boron implantation with an implantation amount of about 10 ¹³ cm ^-2 .

Next, as shown in FIG. 3, using the resist mask 4 having the channel stop region 5 formed as it is, the acceleration energy of the implantation for separation 10 which is higher than the acceleration energy 10 is used.
The gettering layer 17 is formed in a region deeper than the channel stop region 5 by using ion implantation using acceleration energy of 0 to 500 keV. At this time, when boron is implanted to form the gettering layer 17, the gettering capability is dramatically improved by setting the implantation amount to 2 × 10 ¹⁴ cm ⁻² or more in order to enhance the gettering effect. Further, the film thickness of the resist mask 4 must be about 3.5 μm or more so that high-acceleration boron implantation does not penetrate.

In the following steps, the same processes as those in the conventional method for manufacturing a semiconductor device having a MOS structure are performed. FIG. 4 shows the structure of a MOS semiconductor device having a gettering layer.

A gettering layer 17 formed by ion implantation in a region deeper than the channel stop region 5.
Has a high gettering ability of the heavy metal near the surface, and can reduce the leak current generated by the heavy metal contamination.

Further, since the gettering layer 17 does not enter the electrically active region, other basic characteristics are not changed and only the leak current can be suppressed.

Next, an element cross-sectional view of the structure of the solid-state image pickup device to which the present invention is applied is shown. FIG. 5 is an element cross-sectional view of the structure of a solid-state image pickup device to which the present invention is applied.

As shown in FIG. 5, the gettering layer 17 is formed.
Is located immediately below the channel stop region 5 for separating the vertical CCD 14 from the photodiode 13 and between adjacent photodiodes 13, and is not formed in other photodiodes or vertical CCDs. Due to this structure, the injection defects in the gettering layer 17 are located in the electrically inactive region, and it is possible to suppress the dark current due to the injection defects and the occurrence of white scratches due to the injection defects.

Next, an embodiment in which the present invention is applied to a method for manufacturing a solid-state image pickup device will be described. 6 to 10 are sectional views in order of the steps of the method for manufacturing the solid-state imaging device according to the embodiment of the present invention.

First, as shown in FIG. 6, an n-type Si substrate 1
0 to the first p-type well 11 with an acceleration energy of 100 ke
V to 2 MeV, injection amount about 10¹¹cm^-2Injecting boron
After heat treatment, heat treatment at 1100 ° C or higher
To achieve. After that, the second p-type well 12 is accelerated with energy.
-100keV-300keV, injection amount about 10¹²cm ^-2
Formed by boron implantation. And photodio
The photodiode 13 that is the n-type region of the
Lugie 200 keV to 1 MeV, injection amount about 10 ¹²cm^-2
Is formed by implanting phosphorus. Photodiode 13 type
After formation, a vertical CCD 14 is formed in the second p-type well 12.
To achieve. Then, as shown in FIG.
Photodiode 13 and adjacent photodiode 13
Accelerate the channel stop area 5 to separate the spaces
Energy 50 to 200 keV, injection amount about 10¹³cm^-2
It is formed by implanting boron to a certain degree.

Next, as shown in FIG. 8, the resist mask 4 having the channel stop region 5 formed is used as it is, and the acceleration energy of the implantation for separation 1 is higher than 1
The gettering layer 17 is formed by using ion implantation in a region deeper than the channel stop region 5 with an acceleration energy of 00 to 500 keV. At this time, when boron is implanted to form the gettering layer 17, the gettering ability is dramatically improved by setting the implantation amount to 2 × 10 ¹⁴ cm ⁻² or more in order to enhance the gettering effect. Further, the film thickness of the resist mask 4 must be about 3.5 μm or more so that high-acceleration boron implantation does not penetrate.

After that, as shown in FIG. 9, after removing the resist mask 4, the channel dope region 15 for controlling the threshold voltage (Vt) of the read region is accelerated with an energy of 50 to 200 keV and an implantation amount of 10 ¹¹ to 10 10. ^It is formed by implanting boron of about ¹² cm ^-2 .

Next, as shown in FIG. 10, the gate oxide film 7 is formed.
After the formation of the polysilicon film, a polysilicon film 8 is formed on the gate oxide film 7, and the polysilicon film 8 is formed into an electrode by using a dry etching method to charge the photodiode portion with a vertical CCD.
The structure is such that it is read out to the department. Thereafter, as a countermeasure against dark current, a buried photodiode p ⁺ layer 16 is formed at the interface between the photodiode 13 and the gate oxide film 7 by implanting boron with an acceleration energy of 10 to 50 keV and an implantation dose of 10 ¹⁴ cm ^-2 .

The gettering layer 17 formed by ion implantation in a region deeper than the channel stop region 5 for separating the vertical CCD 14 from the photodiode 13 and between adjacent photodiodes 13 has a gettering ability of heavy metals near the surface. It is possible to reduce the dark current of the photodiode section and the CCD section caused by heavy metal contamination, and also to suppress the occurrence of white scratches.

At this time, the gettering layer 17 is CC
Since it does not enter the electrically active region during the D operation, characteristics such as dark current can be improved without changing other basic characteristics such as reading characteristics.

When a similar gettering layer 17 is formed by using carbon ions which are electrically neutral and have a high gettering ability for heavy metals, a lower gettering layer 17 than that of boron is obtained.
^An equivalent dark current reduction effect can be obtained with an implantation amount of about ¹² cm ^-2 .

[0036]

According to the present invention, a gettering layer of heavy metal near the surface is formed in a region deeper than a channel stop region which is an electrically inactive region, so that only one step is added to the gettering layer. The present invention realizes a semiconductor device in which deterioration of electrical characteristics due to gettering of heavy metal near the surface due to the above is reduced and deterioration of electrical characteristics due to crystal defects formed in an electrically active region is eliminated.

[Brief description of drawings]

FIG. 1 is a sectional view of an element structure showing one embodiment of the structure of a semiconductor device of the present invention.

FIG. 2 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a sectional view of an element structure showing an embodiment of the structure of the solid-state imaging device of the present invention.

FIG. 6 is a process sectional view showing an embodiment of the method for manufacturing the solid-state imaging device of the present invention.

FIG. 7 is a process sectional view showing an embodiment of a method for manufacturing a solid-state imaging device of the present invention.

FIG. 8 is a process sectional view showing an embodiment of the method for manufacturing the solid-state imaging device of the present invention.

FIG. 9 is a process sectional view showing an embodiment of the method for manufacturing the solid-state imaging device of the present invention.

FIG. 10 is a process sectional view showing an embodiment of the method for manufacturing the solid-state imaging device of the present invention.

FIG. 11 is an element cross-sectional view showing an example of a conventional method of manufacturing a semiconductor device.

FIG. 12 is a process sectional view showing an example of a conventional method for manufacturing a semiconductor device.

FIG. 13 is a process sectional view showing an example of a conventional method for manufacturing a solid-state imaging device.

FIG. 14 is a process sectional view showing an example of a conventional method for manufacturing a solid-state imaging device.

FIG. 15 is a process sectional view showing an example of a conventional method for manufacturing a solid-state imaging device.

[Explanation of Codes] 1 Si substrate 2 Oxide film 3 Nitride film 4 Resist mask 5 Channel stop region 6 LOCOS film 7 Gate oxide film 8 Polysilicon film 9 Source / drain region 10 n-type Si substrate 11 First p-type well 12 Second p-type well 13 Photodiode 14 Vertical CCD 15 Channel dope region 16 Photodiode p ⁺ layer 17 Gettering layer

Front page continuation (72) Inventor Hiroyuki Okada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.

Claims (5)

[Claims] 1. An element isolation region formed on a semiconductor substrate,
A semiconductor device having a gettering layer formed directly under the element isolation region. 2. The electrically active region is formed immediately below the element isolation region, and the gettering layer is formed at a position deeper than the electrically active region. Semiconductor device. 3. A step of forming a plurality of photodiode parts and a plurality of charge transfer part parts in an array on a semiconductor substrate, the charge transfer part, the photodiode, and the photodiode and a photodiode adjacent thereto. A step of forming a channel stop region between the channel stop region, a step of forming a gettering layer at a position deeper than the channel stop region, and a step of forming an element isolation region in the channel stop region. And a method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the channel stop region and the gettering layer, the formation is performed by ion implantation with the same resist mask. 5. A channel stop is formed by forming a photodiode and a charge transfer section in an array form, and then forming a resist mask between the charge transfer section and the photodiode and between the photodiode and a photodiode adjacent thereto. A method of manufacturing a semiconductor device, wherein a region is formed by ion implantation, and a gettering layer is formed in a region deeper than the channel stop region, continuously with the resist mask as a mask.