JPH0645523A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent internal circuit damage clue to abnormal voltage like static electricity and improve protective function, for both the part between an I/O signal terminal and an earth electrode and the part between the I/O signal terminal and a power supply electrode (semiconductor substrate), without increasing the occupied area of a protective element. CONSTITUTION:A P-type well part 3 under a collector region 6 of one bipolar transistor type protective element constituted of a base region 4, an emitter region 5, and a collector region 6 is shallowly formed, and the other bipolar transistor type protective element wherein the shallow part is made the base region is constituted. The collector region 6 is connected with an I/O signal terminal 10, and an N-type semiconductor substrate 1 is connected with a power supply terminal 9. Thereby the internal circuit 8 is protected from an abnormal voltage due to static electricity or the like generated between the I/O terminal 10 and the power supply terminal 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a protective element in a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 8 is a sectional structural view and a partial schematic circuit diagram of an internal circuit protection element using a conventional bipolar transistor, and FIG. 9 is an equivalent circuit diagram thereof.

A signal input / output terminal 1 is formed on an N-type semiconductor substrate 1.
0, an internal circuit 8, and an internal circuit protection element 12 using a bipolar transistor (punch through transistor).

The protective element 12 includes an N ⁺ collector region 6, an N ⁺ type emitter region 5, and a base region 4 in the P type well between both regions in a P type well 2 formed in an N type semiconductor substrate 1. A lateral NPN bipolar transistor is formed from the P ⁺ type diffusion layer 7 serving as a well contact, the collector region 6 is connected to the signal input / output terminal 10, and the emitter region 5 is formed.
The diffusion layer 7 is connected to the ground terminal 21, and the N-type semiconductor substrate 1 is connected to a positive potential power supply terminal.

Next, the operation will be described. The protective transistor 12 conducts between the input / output terminal and the ground electrode at a voltage lower than the voltage at which the internal circuit 8 is destroyed and at a high voltage that does not hinder the operation of the internal circuit 8. This prevents the voltage of the input / output terminal from rising too high, and the internal circuit 8
Protects against positive overvoltage.

Further, in this protection transistor 12, when the voltage at the input / output terminal becomes lower than the ground electrode, the P-N junction between the collector region 6 and the well 2 operates in the forward direction, It also serves to protect the internal circuit when a negative overvoltage due to static electricity or the like is applied to the input / output terminals.

In a normal semiconductor device, internal circuit protection elements are connected to all input terminals, output terminals and power supply terminals.

FIG. 10 shows a MOS field effect transistor 1
5 shows another conventional technique using 5 as an input protection element. The difference from the prior art is that the input / output terminal 10 and the ground terminal 2 are
As in the case of 1, the MOS type field effect transistor 15 as an input protection element is connected between the input / output terminal 10 and the power supply terminal 9. As in the prior art, the width of the gate electrode (channel) of the gate electrode is set so that the transistor 15 as a protection element conducts at a voltage lower than the voltage at which the internal circuit 8 is destroyed and at a high voltage that does not hinder the operation of the internal circuit 8. Part length) and the impurity concentration of the channel part. Against an undesired applied voltage in the reverse direction, the internal circuit is protected by operating in the forward direction of the P-N junction of the source or drain region.

[0009]

Generally, the performance evaluation of a protection element against an abnormal voltage due to static electricity or the like is performed by applying a voltage to each of the input terminal and the ground terminal and between the input terminal and the semiconductor substrate (power electrode). It is evaluated by the method of applying.

At the time of this test, according to the prior art shown in FIGS. 8 and 9, the input / output signal terminal 10 and the semiconductor substrate (power supply electrode) 1
Since the P well 2 is thick and has no current path with respect to the abnormal voltage applied between and, it does not have a protection function for protecting the internal circuit 8.

On the other hand, in the prior art shown in FIG. 10, between the input / output terminal 10 and the ground terminal 21 and the input / output signal terminal 1
It is necessary to form the input protection element 15 between 0 and the power supply terminal 9. Therefore, the protection function forming area becomes about twice as large as that of the conventional technique shown in FIGS. 8 and 9, and there is a disadvantage that the layout around the terminals becomes complicated when the number of input / output signal terminals increases.

An object of the present invention is to improve the internal circuit protection function due to static electricity and the like without increasing the area occupied by the protection element.

[0013]

A feature of the present invention is that a semiconductor substrate of a first conductivity type, a well of a second conductivity type formed in the semiconductor substrate, and a first conductivity formed in the well. The first portion of the well below the first diffusion layer has a lower impurity concentration than the second portion of the well excluding the first portion, or the well Or the impurity concentration is low and the well is shallow, the first diffusion layer, the first portion of the well below the first diffusion layer, and the semiconductor substrate below the first diffusion layer. In the semiconductor device, the first protection element of the vertical bipolar transistor mechanism is configured from the above part. Here, the semiconductor device has a signal terminal, a power supply terminal, and a ground terminal, the first conductivity type first diffusion layer is connected to the signal terminal, and the first conductivity type semiconductor substrate is used as the power supply terminal. And connecting the well of the second conductivity type to the ground terminal so that the first protection element becomes conductive when the voltage at the signal terminal becomes overvoltage with respect to the power supply voltage at the power supply terminal. be able to.

Also, the second of the well of the second conductivity type
A second diffusion layer of the first conductivity type is provided in the portion of, and a lateral bipolar transistor is formed from the first diffusion layer, the second diffusion layer, and the portion of the well between the first and the second. A second protection element of the mechanism, the signal terminal of the semiconductor device is connected to the first diffusion layer, the ground terminal of the semiconductor device is connected to the second type diffusion layer and the well, and the ground terminal is connected. It is possible to make the second protection element conductive when the voltage at the signal terminal becomes an overvoltage with respect to the ground potential.

Alternatively, a second diffusion layer of the first conductivity type is provided in the second portion of the well of the second conductivity type, and the first and second diffusion layers serve as source and drain regions, and A second protection element is constituted by a MOS type field effect transistor in which a surface portion of the well between the first and second diffusion layers is used as a channel region and a gate electrode is provided on the channel region through a gate insulating film. Is connected to the signal terminal of the first diffusion layer, the ground terminal of the semiconductor device is connected to the second type diffusion layer and the well, and the voltage at the signal terminal is overvoltage with respect to the ground potential at the ground terminal. The second protection element can be brought into a conductive state when it becomes.

Another feature of the present invention is that when a well of the second conductivity type is provided in a semiconductor substrate of the first conductivity type, a mask is selectively formed on the semiconductor substrate of the first conductivity type to form the semiconductor. An impurity of the second conductivity type is introduced into the substrate, and the first portion of the well where the mask is present is laterally spread by thermal diffusion in the subsequent heat treatment, and the first portion of the well is replaced with the second portion of the well.
Of the first conductivity type diffusion layer in the first portion of the well, the impurity concentration of which is lower than that of the well, the depth of the well is shallower, or the impurity concentration is lower and the depth of the well is shallower. Is provided to form the first protection element of the vertical bipolar transistor mechanism.

According to the present invention described above, when an abnormal voltage is applied to the input / output terminal with respect to the semiconductor substrate (power supply electrode), charges flow through the shallowly formed portion of the second conductivity type well, so that the internal It is possible to prevent damage to the circuit. Further, there is no increase in the occupied area of the protection element.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a sectional view and a partial schematic circuit diagram showing a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. A P-type well 2 is provided in the N-type semiconductor substrate 1, and a first N ⁺ type diffusion layer 6, a second N ⁺ type diffusion layer 5 and a P ⁺ type diffusion layer 7 are formed in the P type well 2. ing. Then, the portion 3 of the P-type well 2 below the first N ⁺ -type diffusion layer 6 has a lower impurity concentration than the other portions of the well 2 or has a shallower depth or a lower impurity concentration. The depth is shallow.

Further, the power supply terminal 9, the input / output signal terminal 10 and the ground terminal 21 for supplying a positive potential on the same semiconductor substrate 1.
The first N ⁺ type diffusion layer 6 is connected to the signal terminal 10, the second N ⁺ type diffusion layer 5 and the P ⁺ type diffusion layer 7 are connected to the ground terminal 21, and the N type semiconductor substrate 1 is formed. Is connected to the power supply terminal 9.

The first N ⁺ type diffusion layer 6 is used as an emitter region (or collector region), and this emitter region 6
A portion 3 in which the impurity concentration of the lower P-type well 2 is made low or the depth of the well is made shallow or the impurity concentration is made low and the depth of the well is made shallow is used as a base region 3, and the N-type semiconductor thereunder A vertical bipolar transistor (P-well punch-through transistor) (P-well slit bipolar transistor) 11 having a portion of the substrate 1 as a collector region (or emitter region) is formed as a first protection element, and a signal is supplied to a power supply voltage. When an overvoltage occurs at the terminal, the transistor 11 becomes conductive and protects the internal circuit 8 formed on the same semiconductor substrate 1 from an abnormal voltage.

On the other hand, a lateral bipolar transistor in which the first N ⁺ type diffusion layer 6 is used as a collector region, the second N ⁺ type diffusion layer 5 is used as an emitter region, and the P type well portion 4 between them is used as a base region 4. (Punch through transistor) 1
2 is configured as a second protection element, and when an overvoltage occurs at the signal terminal with respect to the ground voltage, the transistor 12
Becomes conductive and protects the internal circuit 8 from abnormal voltage.

FIG. 3 is a sectional view showing an embodiment for forming the P-type well 2 of the present invention. When providing the P-type well 2 in the N-type semiconductor substrate 1, boron is introduced into the semiconductor substrate by the ion implantation method by selectively forming the ion implantation shielding film 13 on the semiconductor substrate as a mask (FIG. 3A). ), The portion 3 where the mask 13 was present is laterally spread by indentation diffusion due to the subsequent heat treatment, and the P-type well 2 is formed in which the impurity concentration is lower and the depth is shallower than other portions (FIG. 3).
(B)).

The wells of the invention for this purpose may be formed in other ways.

The vertical bipolar transistor 11 serving as the first protection element having the P-type well has the P-well when a high voltage is applied between the input / output signal terminal 10 and the power supply terminal 9 (semiconductor substrate 1). The electric charge is neutralized through the shallow portion 3 of 2 to protect the internal circuit.

The condition for the transistor 11 to operate as a protection circuit is that the collector region 6 and the semiconductor substrate 1 are electrically connected to each other at a voltage lower than the voltage at which the internal circuit 8 is destroyed and at a voltage that does not hinder the operation of the internal circuit 8. It is necessary to.

For this reason, as a result of actual manufacture and experiment,
When a P-type well is formed by implanting boron ions with a dose amount of 1.2 × 10 ¹² cm ⁻² into a semiconductor substrate having an N-type impurity concentration of 2.0 × 10 ¹⁴ cm ⁻³ , as shown in FIG. The optimum width W of the ion implantation shielding film 13 shown in A) is about 5 μm.

In the first embodiment, the power supply voltage is
It has been confirmed that both the ground voltage and the electrostatic test of JIS standard 250V are passed.

FIG. 4 is a sectional view and a partial schematic circuit diagram showing a second embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram thereof.

In this embodiment, MO is used as the second protection element.
The S-type field effect transistor 15 is formed. That is, the P-type well 2 is provided in the N-type semiconductor substrate 1, and the first N ⁺ -type diffusion layer 16, the second N ⁺ -type diffusion layer 17, and the P ⁺ -type diffusion layer 7 are formed in the P-type well 2. Has been done. Then, the portion 3 of the P-type well 2 below the first N ⁺ -type diffusion layer 16 has a lower impurity concentration than the other portions of the well 2 or has a shallower depth or a lower impurity concentration. The depth is shallow. A power supply terminal 9 for supplying a positive potential, an input / output signal terminal 10, and a ground terminal 21 are formed on the same semiconductor substrate 1, the first N ⁺ type diffusion layer 16 is connected to the signal terminal 10, and the second N ⁺ type diffusion layer 16 is connected. ⁺ Type diffusion layer 17 and P ⁺
The mold diffusion layer 7 is connected to the ground terminal 21, and the N-type semiconductor substrate 1 is connected to the power supply terminal 9. Then, as in the first embodiment, the first N ⁺ type diffusion layer 16 is used as an emitter region (or collector region), and the impurity concentration of the P type well 2 below the emitter region 16 is lowered or the depth of the well is reduced. Of the N-type semiconductor substrate 1 under the base region 3 and the collector region (or emitter region) under the region 3 where the well is shallow or the impurity concentration is low and the well depth is shallow. The transistor 11 is configured as a first protection element, and when an overvoltage occurs in the signal terminal with respect to the power supply voltage, the transistor 11 becomes conductive and protects the internal circuit 8 formed on the same semiconductor substrate 1 from an abnormal voltage. To do.

On the other hand, in the second embodiment, the first N ⁺ type diffusion layer 16 is used as the drain region and the second N ⁺ type diffusion layer 1 is used.
7 is a source region, a P-type well portion therebetween is a channel region, and a gate electrode 19 is formed on the channel region via a gate insulating film 20.
5 as a second protection element, and when an overvoltage occurs at the signal terminal with respect to the ground voltage, the transistor 15
Becomes conductive and protects the internal circuit 8 from abnormal voltage.

FIG. 6 is a sectional view and a partial schematic circuit diagram showing a third embodiment of the present invention, and FIG. 7 is an equivalent circuit diagram thereof. 6 and 7, parts having the same functions as those in FIGS. 1 to 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the third embodiment, the second protective element is not formed and the N ⁺ type diffusion layer 18 in the P type well 2 is used as the first protective element as the emitter region (or collector region). Only vertical bipolar transistors are configured.

In the third embodiment, the internal circuit is protected only by the overvoltage between the input / output signal terminal and the power supply voltage terminal (semiconductor substrate).

The vertical bipolar transistor as the first protection element of the present invention is not limited to the case where it is used in combination with the lateral bipolar transistor or the MOS field effect transistor as the second protection element, and other vertical bipolar transistors are used. It is also possible to use it in combination with a protective element.

In the above embodiment, the case where the P-type well is formed on the N-type semiconductor substrate is illustrated. However, the conductivity type opposite to that of the embodiment is read by replacing N-type with P-type and P-type with N-type. It is also possible to configure the protective element of the present invention.

[0037]

As described above, according to the present invention, although the area occupied by the conventional protection circuit is the same, the space between the input / output signal terminal and the ground electrode and between the input / output signal terminal and the power supply electrode (semiconductor substrate) is large. Both of them have the effect of preventing internal circuit damage due to abnormal voltage such as static electricity.

[Brief description of drawings]

FIG. 1 is a sectional view and a partial schematic circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing the first embodiment of the present invention.

FIG. 3 is a sectional view showing a part of a manufacturing method according to an embodiment of the present invention.

FIG. 4 is a sectional view and a partial schematic circuit diagram showing a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a second embodiment of the present invention.

6A and 6B are a sectional view and a partial schematic circuit diagram showing a third embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram showing a third embodiment of the present invention.

FIG. 8 is a cross-sectional view and a partial schematic circuit diagram showing a conventional technique.

FIG. 9 is an equivalent circuit diagram showing a conventional technique.

FIG. 10 is an equivalent circuit diagram showing another conventional technique.

[Explanation of symbols]

1 N-type semiconductor substrate 2 P-type well 3 Shallow part of P-type well 4 Base region 5 Second N ⁺ type diffusion layer (emitter region) 6 First N ⁺ type diffusion layer (emitter / collector region) 7 P ⁺ Type diffusion layer (well contact) 8 Internal circuit 9 Power supply terminal 10 Input / output signal terminal 11 First protection element (vertical bipolar transistor) 12 Second protection element (horizontal bipolar transistor) 13 Ion implantation shielding film 14 Boron Ion-implanted region 15 Second protection element (MOS field effect transistor) 16 First N ⁺ type diffusion layer (emitter / drain region) 17 Second N ⁺ type diffusion layer (source region) 18 N ⁺ type diffusion layer (Emitter / collector region) 19 Gate electrode 20 Gate insulating film 21 Ground terminal

Claims (5)

[Claims] 1. A semiconductor substrate of a first conductivity type, a well of a second conductivity type formed in the semiconductor substrate, and a first diffusion layer of a first conductivity type formed in the well. However, the first portion of the well below the first diffusion layer has a lower impurity concentration than the second portion of the well except the first portion, the well has a shallow depth, or the impurity concentration is low. Is low and the depth of the well is shallow, the vertical diffusion transistor mechanism is composed of the first diffusion layer, the first portion of the well below the first diffusion layer, and the portion of the semiconductor substrate below the first diffusion layer. A semiconductor device comprising a first protection element. 2. A semiconductor device has a signal terminal, a power supply terminal, and a ground terminal, the first diffusion layer of the first conductivity type is connected to the signal terminal, and the semiconductor substrate of the first conductivity type is the power supply. A second conductivity type well is connected to the ground terminal, and the first terminal is connected when the voltage at the signal terminal exceeds the power voltage at the power terminal.
2. The protective element of 1 is brought into a conducting state.
The semiconductor device according to. 3. A second diffusion layer of the first conductivity type is provided on the second portion of the well of the second conductivity type, and the first diffusion layer, the second diffusion layer, and the second diffusion layer. A second protection element of a lateral bipolar transistor mechanism is formed from the well portion between the first and second wells, the first diffusion layer is connected to the signal terminal of the semiconductor device, and the ground terminal of the semiconductor device is connected to the first diffusion layer. A second type diffusion layer is connected to the well, and when the voltage at the signal terminal becomes an overvoltage with respect to the ground potential at the ground terminal, the second protection element becomes conductive. The semiconductor device according to claim 1 or 2. 4. A second diffusion layer of the first conductivity type is provided on the second portion of the well of the second conductivity type, and the first and second diffusion layers are provided.
Of the first and second diffusion layers as source and drain regions.
Forming a second protection element by a MOS field effect transistor having a surface region of the well between the diffusion layers of the above as a channel region and a gate electrode provided on the channel region via a gate insulating film. When the first diffusion layer is connected, the second type diffusion layer and the well are connected to the ground terminal of the semiconductor device, and the voltage at the signal terminal becomes an overvoltage with respect to the ground potential at the ground terminal. The semiconductor device according to claim 1, wherein the second protection element is in a conductive state. 5. When providing a well of the second conductivity type in a semiconductor substrate of the first conductivity type, a mask is selectively formed on the semiconductor substrate of the first conductivity type to provide the second conductivity type on the semiconductor substrate. Of the well, where the first portion of the well where the mask was present is made lower in impurity concentration than the other second portion of the well by lateral spreading due to thermal diffusion of subsequent heat treatment, or Or the impurity concentration is low and the well is shallow, and a diffusion layer of the first conductivity type is provided in the first portion of the well to provide a first structure of the vertical bipolar transistor mechanism. 1. A method for manufacturing a semiconductor device, comprising the step of forming a protective element of 1.