JPH0645287A - Manufacture of semiconductor device, and aligner - Google Patents

Abstract

PURPOSE:To sensitively judge an etching end point even in a dry etching process in which an area to be etched is small. CONSTITUTION:In a process in which a SiO2 interlayer insulating film 3 is etched to form a micro contact hole, a resist mask 4 is selectively removed from an invalid zone beta that occupies outside a chip acquisition zone a on alphawafer W2 thereby increasing an area to be etched'. When a fluorocarbon gas is used in etching, the amount of resultant reaction products CO* is increased, and hence it becomes possible for us to observe variations in intensity of an emission spectrum. The selective removal of the resist mask 4 is carried selective exposure and a developing treatment. A simple aligner is also put forward for carrying out this selective exposure without the use of an expensive stepper.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and an exposure apparatus used for the same, and more particularly, to a method for facilitating end point determination in a dry etching process having a small area to be etched, and to realize the method. For equipment.

[0002]

2. Description of the Related Art Design rules for semiconductor devices are VLS
As the size of I to ULSI is highly reduced, the thickness of various material layers forming these semiconductor devices has become extremely thin, and the number of layers of these material layers in the vertical direction has increased to increase the wafer. The surface level difference is also increasing. During this period, the mainstream etching method has also changed from wet etching to dry etching. Under such circumstances, a highly accurate end point determination method is necessary to etch a certain material layer with respect to the underlying material layer while maintaining high selectivity and with good reproducibility.

The most rudimentary method for determining the end point is observation with an electron microscope. However, this method has a drawback that the wafer has to be taken out of the etching chamber each time the observation is carried out, the end point determination cannot be automated, and the productivity is lowered. As a simple alternative to this microscopic observation, a method has been considered in which the required etching time is calculated based on the etching rate and the etching is terminated when this time elapses. However, when the material thickness of the material to be etched is non-uniform, the plasma state is changed, the gas flow rate, and the wafer temperature are changed, the etching rate changes slightly. It is impossible to carry out etching.

Therefore, in recent years, some methods have been proposed which can observe the progress of etching in situ by a physicochemical method. As an example, (a) an optical measurement method for measuring the film thickness and optical constants of a material layer to be etched, (b) a mass spectrometry method for measuring a mass spectrum of an etching reaction product, and (c) a probe of a plasma state. The probe method for diagnosing by the method, (d) emission analysis method for measuring the emission spectrum intensity of the chemical species in plasma, and the like.

Of these, the emission analysis method is particularly widely used in production sites. For example, the principle of end point determination in the case of etching Si using a fluorocarbon-based etching gas is as follows. Etching of Si generally proceeds by a mechanism mainly composed of a radical reaction by a halogen radical. The reaction when F ^* is used as the halogen radical is represented by the following formula. Si + xF ^* → SiF _x ↑ The progress of this etching can be known by the intensity change of the emission spectrum of F ^* dissociated and produced from the fluorocarbon-based etching gas. That is, when the etching gas is supplied at a constant flow rate, but the progress of the etching emission spectral intensity since the F ^* is consumed F ^* to generate the SiF _x is reduced, to be etched Si The disappearance of F increases the amount of F ^* in the plasma and increases the emission spectrum intensity. This end point determination method is extremely effective in etching the polycrystalline silicon layer on the gate oxide film and the like.

The end point determination by such an emission analysis method is
Of course, it can be applied to etching of a SiO _x (silicon oxide) -based material layer. A typical etching process for the SiO _x -based material layer is hole processing for opening connection holes such as contact holes and via holes in the interlayer insulating film. Here, contact hole processing will be described with reference to FIG. In FIG. 8A, a SiO ₂ interlayer insulating film 3 is formed on a single crystal Si substrate 1 having an impurity diffusion region 2 as a lower layer wiring, and a resist mask 4 having a predetermined pattern is formed thereon. The chip acquisition region α of the wafer W ₁ (see FIG. 9) is shown. The chip acquisition region α is a region where a complete device chip can be cut out on a substantially circular wafer. The individual chips usually because it is rectangular, the part of which can not be cut out complete form of chips on the outer peripheral portion of the wafer W ₁ "margin" exists. This portion will be referred to as an invalid area β (see FIG. 9). The resist mask 4 has an opening 4a facing the formation position of the impurity diffusion region 2.

The etching of the SiO ₂ interlayer insulating film 3 exposed on the bottom surface of the opening 4a generally proceeds by a mechanism mainly composed of ion-assisted reaction by CF _x ⁺ .
The etching reaction in this case is represented by the following equation. SiO _x + CF _x ⁺ → SiF _x + CO _x Here, when the emission spectrum intensity of CO ^* , which is one of the etching reaction products, is observed at 483.5 nm,
Its intensity starts to increase with the start of etching. Figure 8
During the progress of etching as shown in (b), the emission spectrum intensity changes at a substantially constant intensity. As the etching progresses further, as shown in FIG. 8C, the underlying impurity diffusion region 2 is exposed and the SiO ₂ to be etched is to be etched.
When the interlayer insulating film 3 is lost, CO _x is not generated,
The emission spectrum intensity is attenuated. Therefore, the end point can be determined by detecting the time when the emission spectrum intensity is attenuated.

[0008]

However, as described above, the determination of the etching end point of SiO _x which is theoretically possible is extremely difficult in the recent hole processing. This is related to the decrease in the amount of etching reaction products generated due to the extreme decrease in the area to be etched. Design that the opening diameter of the connection hole is about 0.35-0.5 μm.
Under the rule, the area to be etched in hole processing is only about 3% of the entire wafer, and the opening diameter is 0.
Under the future design rule of about 2 μm, it is expected to decrease to less than 1%. here,
Wafer W ₁ including the chip acquisition region α shown in FIG.
When viewed as a whole, it should look almost like Fig. 9 (a). Here, a large number of openings 4a are formed in the resist mask 4 in the chip acquisition region α, but these are too fine and therefore not shown in FIG. 9 (a). Further, the film thicknesses of the SiO ₂ interlayer insulating film 3 and the resist mask 4 are greatly exaggerated as compared with the thickness of the single crystal Si substrate 1.

As described above, when most of the surface of the wafer W ₁ is covered with the resist mask 4, the amount of etching reaction products produced is extremely small. Therefore,
For example, when trying to monitor the emission spectrum intensity of CO ^* , this signal intensity is buried in the background intensity. As a result, as shown in FIG. 9B, almost no change in intensity can be detected even after the etching time has elapsed since the start of etching. Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of determining a sharp etching end point even when the area to be etched is small, and to provide an exposure apparatus for realizing this. In addition, it aims at it.

[0010]

A method of manufacturing a semiconductor device of the present invention is proposed to achieve the above-mentioned object, and occupies the outer peripheral side of the chip acquisition region on the substrate before etching. By removing at least a part of the etching mask on the ineffective region, the underlying material layer to be etched is exposed, and the area to be etched is increased.

The present invention is also characterized in that the etching mask is composed of a positive photoresist material layer, and the etching mask is removed by selective exposure and development.

The exposure apparatus of the present invention is also proposed to achieve the above-mentioned object, and uses the light source, the slit having a variable longitudinal aperture length, and the exposure light passing through the slit. A control means for changing the exposure area of the substrate is provided, and the substrate is selectively exposed to an arbitrary shape.

The present invention is also characterized in that the control means interlocks the reciprocating movement of the shutter for changing the opening length of the slit and the rotational movement of the substrate.

In the present invention, the exposure area is at least a part of an ineffective area occupying the outer peripheral side of the chip acquisition area on the substrate, and the exposure light exposes the positive photoresist material layer on the ineffective area. It is characterized by having been made to let.

[0015]

The present inventor removes the etching mask in the ineffective region occupying the outer peripheral side of the chip acquisition region to remove the etching target material layer in order to improve the sensitivity of the end point determination in the etching process in which the etching target area is small. It was considered to expose and increase the etched area. The removal of the etching mask may be performed over the entire ineffective region or a part thereof. In any case, the consumption amount of the etchant in the plasma or the generation amount of the etching reaction product is increased, and the change in these amounts can be sensitively detected without being buried in the background value. Further, the exposed portion of the material layer to be etched is an ineffective region from which it is not possible to obtain a valid chip from the beginning, so that the yield of the chip is not reduced by the present invention, and the pattern of the chip obtaining region is not formed. It will not be affected.

Generally, in dry etching,
A material layer having an etching rate sufficiently lower than that of the material layer to be etched is used as an etching mask. Depending on the process, the SiO _x based material layer or the SiN _x based material layer may be used as an etching mask, but in the present invention, a positive photoresist material is selected as a material that can be easily removed in the ineffective region. Since a positive photoresist material causes a photodecomposition reaction in the exposed portion to increase its solubility in a developing solution, if a developing process is performed after selectively exposing an ineffective region using a light source image of an appropriate shape. The etching mask in this exposed area can be removed.

Further, the present inventor also proposes an exposure apparatus for easily realizing such selective exposure. In this device, the selective exposure described above is targeted only on the outer peripheral side of the substrate, and if the chip acquisition area and the invalid area can be distinguished, precise alignment work such as normal mask alignment is unnecessary. , And is proposed by paying attention to two points. This apparatus includes a light source, a slit whose opening length in the longitudinal direction is variable, and control means for changing the exposure area of the substrate by the exposure light passing through the slit. As a means for changing the exposure area, it is conceivable to give a motion in an appropriate direction to any one of the light source, the slit, and the substrate. In any case, the locus of the light source image obtained through the slit on the substrate becomes the exposure area.

The method which is considered to be most practical in terms of accuracy and mechanism as a method of changing the exposure area is a method of rotating the substrate. The shutter at this time is naturally set so as to block the chip acquisition region. For example, if the longitudinal direction of the slit is aligned with the radial direction of the substrate and the substrate is rotated while the central side of the substrate is shielded and the opening length is fixed, a donut-shaped exposure region is obtained on the outer peripheral side of the substrate. . Furthermore, if the opening length of the slit is changed according to the rotation angle of the substrate, the outer peripheral portion of the substrate can be exposed to an arbitrary shape. The etching mask can be removed in at least a portion of the ineffective region if the exposed region of such exposure is within the ineffective region and if this exposure exposes the positive photoresist material layer. In particular, if control is performed so that the opening end of the slit traces the contour of the chip acquisition area,
The entire invalid area can be used as the exposure area.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings.

Example 1 In this example, the semiconductor device manufacturing method of the present invention is applied to contact hole processing, and the emission spectrum intensity of CO ^* generated by etching the SiO ₂ interlayer insulating film is monitored. This is an example in which the end point is detected by. This process will be described with reference to FIG. 1 in addition to FIG. 8 described above. Note that the reference numerals in FIG. 1 are partially the same as those in FIG. 9A described above. First, a SiO ₂ interlayer insulating film 3 is formed on a single crystal Si substrate 1 on which an impurity diffusion region 2 as a lower layer wiring is previously formed, and a novolac-based positive photoresist material (manufactured by Tokyo Ohka Kogyo Co., Ltd .; Product name TSMR-
V3) was applied. Subsequently, a contact hole pattern was exposed on the resist coating film using an i-line stepper (reduction projection exposure apparatus) to obtain a wafer W. The appearance of the wafer W at this stage is similar to that of the wafer W ₁ shown in FIG. 9A, but since the alkali developing treatment has not been performed yet, the wafer 4 is not formed with the opening 4a. W
Different from ₁ . At this stage, it is not necessary to carry out the alkali developing treatment because the i-line exposed portion is also dissolved and removed at the same time when the alkali developing for removing the resist mask 4 on the ineffective region β is performed in the subsequent process. This is because 4a can be formed.

In the present embodiment, the resist mask 4 was further subjected to peripheral exposure by i-line and alkali development treatment to remove the resist mask 4 in the entire ineffective region β. An exposure apparatus for performing this outer periphery exposure will be described in detail in a second embodiment below, and a method of controlling an exposure area will be described in a fourth embodiment described later. An overall image of the wafer W ₂ obtained in this way is shown in FIG. As a result, the area to be etched is about 18% compared to about 1% of the conventional wafer W _1.
Increased to%. An enlarged cross-sectional view of the etched region in the chip acquisition region α at this time is as shown in FIG. However, since the openings 4a formed by the alkali developing process are too fine,
Not shown in (a).

Next, this wafer W ₂ was set in a plasma etching apparatus, and the SiO ₂ interlayer insulating film 3 was etched using CHF ₃ gas. The progress of etching is as shown in FIG. 8B. However, in this embodiment, the SiO ₂ interlayer insulating film 3 exposed in the ineffective region β is also etched at the same time. For this reason, the CO _x , which is an etching reaction product, significantly increased as compared with the conventional process. As the etching progresses,
As shown in (c), when the underlying single crystal Si substrate 1 (more precisely, the impurity diffusion region 2) was exposed, the amount of CO _x produced decreased. The whole image of the wafer W _{3 at} this time is shown in FIG.
This is as shown in (b).

The above-described etching progress process is performed in situ by an optical emission analyzer connected to the etching chamber.
FIG. 1 (c) shows the state of monitoring at u. In the figure, the vertical axis represents the CO ^* emission spectrum intensity observed at 483.5 nm (arbitrary scale), and the horizontal axis represents the etching time (arbitrary scale). CO ^* emission spectral intensity begins to rise immediately after the start of the etching, during the etching progression remained almost constant value, SiO ₂ interlayer insulating film 3 to be etched
The value decreased as the value decreased, and eventually decreased to the same level as the value before the start of etching. In the past, since the amount of CO ^* produced was extremely small, almost no change in the emission spectrum intensity could be observed as shown in FIG. 9B. The changes shown could be clearly observed.

Embodiment 2 In this embodiment, an exposure apparatus for enabling removal of the resist mask 4 in the invalid area β as described in Embodiment 1 will be described. FIG. 2 schematically shows a configuration example of the exposure apparatus of the present invention. 2A is a top view of the device, and FIG. 2B is a sectional view taken along the line AA. This apparatus includes an exposure optical system 11, a shutter 13, a slit 12,
With the rotary wafer stage 17 as a basic component,
These are sequentially arranged on the optical axis.

The exposure optical system 11 is housed in a dark box 10 and collects the exposure light emitted from the light source 15 having an appropriate wavelength selected according to the photosensitive characteristics of the positive photoresist material. A reflector 16 for illuminating light, and other optical components not shown, such as capacitors.
It is composed of a lens and the like.

The slit 12 is an elongated opening formed in a part of the bottom surface of the dark box 10. One end in the longitudinal direction thereof is substantially aligned with the center O of the wafer W, whereby the slit 12 is opened along the direction of the radius r of the wafer W. The other end is located further outside than the outer edge of the wafer W.

The shutter 13 is the same as the dark box 10.
It is arranged in a position that covers the slit 12 inside. The shutter 13 is a rack in which one side in the longitudinal direction is processed into a sawtooth shape to form a rack, and a pinion 14 which is connected to a driving means (not shown) and rotates in the arrow Y direction is meshed with the sawtooth portion, thereby forming an arrow. It is designed to reciprocate in the X direction. This reciprocating movement changes the opening length of the shutter 13. Here, if the length from the center O of the wafer W to the tip of the shutter 13 is defined as x, the exposure light extracted from the portion of the slit 12 corresponding to the difference between the radius r of the wafer W and the length x is the wafer. This contributes to the exposure on the outer peripheral side of W.

The slit 1 is provided outside the dark box 10.
A rotary wafer stage 17 for supporting the wafer W is disposed at a position opposed to the wafer 2. This rotary wafer stage 17 has a drive unit 19 via a rotary shaft 18.
And is rotated in the direction indicated by arrow Z, for example. The control of the drive device 19 is performed by a control mechanism (not shown) in conjunction with the control of the drive means (not shown) of the pinion 14 described above.
The length x can be changed according to the rotation angle of the wafer W by the program.

Embodiment 3 In this embodiment, the above-mentioned exposure apparatus is used to perform the simplest operation of exposing the outer peripheral side of the wafer in a donut shape with a constant width, with reference to FIG. While explaining. First, the wafer W at the stage where the i-line lithography according to the contact hole pattern is completed is shown in FIG.
The exposure was performed while setting the shutter on the rotary wafer stage 17 of the exposure apparatus shown in FIG. The relationship between the length x from the wafer center O to the shutter tip and the wafer rotation angle (°) at this time is shown in a graph of FIG. 3C. Of course, the tip position of the shutter 13 at this time does not exceed the radius r of the wafer W, but the length x is based on the point where the distance from the wafer center O is the maximum in the chip acquisition region α.
Was set so as not to be smaller than this maximum distance.
As the light source 15, i-line of a high pressure mercury lamp was used.

After this peripheral exposure, alkali development treatment was performed. FIGS. 3A and 3B show a top view and a perspective view of the wafer W ₄ thus obtained, respectively. In FIG. 3A, the shaded thin ring-shaped portion is the exposure area Exp by the above-described outer peripheral exposure, and occupies a part of the ineffective area β on the outermost peripheral side. At this portion, the resist mask 4 is removed by an alkali developing process, so that the SiO ₂ interlayer insulating film 3 is formed by this ring-shaped area.
The area to be etched was increased. This wafer W ₄ was also dry-etched to form contact holes, and the progress of etching could be monitored by emission analysis.

Embodiment 4 In this embodiment, a model in which the rotational movement of the wafer and the reciprocating movement of the shutter are linked will be described. In the model used in this embodiment, as shown in FIG. 4, in the wafer W ₅ in which twelve square chips are arranged in a cross shape, the entire invalid region β on the outer peripheral side of the chip acquisition region α is exposed to the exposure region Exp. It is what Therefore, the tip of the shutter traces the cross-shaped contour of the chip formation region α on the rotating wafer W.

A calculation method for expressing the length x from the center O of the wafer W ₅ to the tip of the shutter in this case as a function of the wafer rotation angle will be described with reference to FIG.
In the exposure apparatus of FIG. 2, the wafer W actually rotates.
However, here, for convenience of explanation, it is considered that the slit 12 and the shutter 13 integrally rotate in the clockwise direction. First, orthogonal coordinates having the center O of the wafer W ₅ as an origin are set, and a perpendicular intersection point between one side of the chip acquisition region α and the vertical axis of this coordinate is set as a point A. Further, the length OA is y. This y corresponds to the length of two sides of the square. The tip of the shutter 13 starts from the point A, and the tip acquisition area α
It follows that it advances in the direction of the black arrow in the figure along the contour of the above and passes through points B, C, ... The rotation angle of the shutter 13 at this time is θ with reference to the line segment OA.
Expressed in (°). In addition, the rotation angles at points C, E, and G, which are bending points of the cross-shaped contour, are particularly θ ₁ , θ ₂ , and θ _3.
It is defined as These rotation angles can be easily calculated because each chip is square, and θ ₁ =
26.6 °, θ ₂ = 45 °, and θ ₃ = 63.4 °.
Similarly, in other quadrants, the rotation angle is defined, and θ ₄ to θ ₁₂
I named it.

The calculation is as follows. (1) When θ = 0: x = y (2) When 0 <θ <θ ₁ : In ΔBOA, co
sθ = y / x ∴x = y / cosθ (3) When θ = θ ₁ : At ΔCOA, co
s (26.6) = y / x ∴x = y / cos (26.6) = 1.12y (4) When θ ₁ <θ <θ ₂ : At ΔDOJ, cos (90−θ) = (y / 2) / X ∴x = y / 2 cos (90−θ) (5) When θ = θ ₂ : In ΔEOJ, cos (45) = (y / 2) / x ∴x = y / 2 cos (45) = 0 .71y (6) When θ ₂ <θ <θ ₃ : In ΔFOK, co
When sθ = (y / 2) / x ∴x = y / 2cos θ (7) θ = θ ₃ : In ΔGOK, cos (63.4) = (y / 2) / x ∴x = y / 2cos (63.4) = 1.12y (8) When θ ₃ <θ <90: At ΔHOI, co
s (90−θ) = y / x ∴x = y / cos (90−θ) (9) When θ = 90: x = y

In the above, the calculation method is shown in the range of 0 ≦ θ ≦ 90. However, the subsequent calculation with 180 °, 270 ° and 360 ° as the respective divisions is a repetition of the above calculation. When the length x thus calculated is plotted against the rotation angle of the wafer, a graph as shown in FIG. 5B is obtained. That is, the rotational movement of the wafer W ₅ and the shutter 13 are performed in advance.
If the change pattern of the length x is programmed in the control mechanism that controls the reciprocating motion of the above, the entire invalid region β can be exposed.

Fourth Embodiment In this embodiment, the same calculation is performed for a model that is slightly more complicated than that of the third embodiment. The model used in this embodiment is shown in FIG.
In the wafer W _{6 on} which 37 square chips are arranged as shown in FIG. 3, the entire invalid area β on the outer peripheral side of the chip acquisition area α is set as the exposure area Exp. This pattern is for realizing the pattern of the resist mask 4 shown in FIG.

A calculation method for expressing the length x from the wafer center o to the shutter tip in this case as a function of the wafer rotation angle will be described with reference to FIG. The basic idea of calculation is as described in the third embodiment. First, orthogonal coordinates having the center o of the wafer W ₆ as an origin are set, and a vertical intersection point between one side of the chip acquisition region α and the vertical axis of this coordinate is set as a point a. Further, the length oa is set to y.
This y corresponds to the length of 3.5 sides of the square. It is assumed that the tip of the shutter 13 starts from a point a, travels in the direction of the black arrow in the figure along the contour of the chip acquisition region α, and sequentially passes through points b, c, ..., M. . The rotation angle of the shutter 13 at this time is φ based on the line segment oa.
Expressed in (°). Further, the rotation angles at the points c, e, g, i, and k which are the bending points of the contour of the chip acquisition region α are defined as φ ₁ , φ ₂ , φ ₃ , φ ₄ , and φ ₅ . These rotation angles can be easily calculated because each chip is square, and φ ₁ = 23.2 ° and φ ₂ =
31 °, φ ₃ = 45 °, φ ₄ = 59 °, φ ₅ = 66.8
°. In the other quadrants, define the rotation angle in the same way,
It was named φ _{6 to} φ ₂₀ .

The calculation is as follows. (1) When φ = 0: x = y (2) When 0 <φ <φ ₁ : At Δboa, co
sφ = y / x ∴x = y / cosφ (3) When φ = φ ₁ : At Δcoa, co
s (23.2) = y / x ∴x = y / cos (23.2) = 1.09y (4) When φ ₁ <φ <φ ₂ : At Δdop, cos (90−φ) = (1.5y / 3.5 ) / X ∴x = 0.43y / 2cos (90−φ) (5) When φ = φ ₂ : At Δeos, cos (31) = (2.5y / 3.5) / x ∴x = 0.71y / cos ( 31) = 0.83y (6) φ 2 <φ <φ 3 when: △ in fos, cosφ = (2.5y / 3.5 ) / x ∴x = 0.71y / cosφ (7) φ = φ 3 when: At Δgos, cos (45) = (2.5y / 3.5) / x ∴x = 0.71y / cos (45) = 1.00y (8) When φ ₃ <φ <φ ₄ : At Δhon, cos ( 90−φ) = (2.5y / 3.5) / x ∴x = 0.71y / cos (90−φ) (9) When φ = φ ₄ : At Δioq, cos (59) = (1.5y / 3.5) / x ∴x = 0.43y / cos ( 59) = 0.83y (10) φ 4 <φ <φ 5 at the time: △ to joq There are, cosφ = (1.5y / 3.5) / x ∴x = 0.43y / cosφ (11) φ = φ 5 when: △ in koq, cos (66.8) = ( 1.5y / 3.5) / x ∴x = 0.71 y / cos (45) = 1.09y (12) When φ ₅ <φ <90: At Δlom, co
s (90−φ) = y / x ∴x = y / cos (90−φ) (13) When φ = 90: x = y

Although the calculation method has been described above in the range of 09φ ≦ 90, the subsequent calculation with 180 °, 270 ° and 360 ° as the respective divisions is a repetition of the above calculation. When the length x thus calculated is plotted against the rotation angle of the wafer, a graph as shown in FIG. 7B is obtained. In other words, the rotational movement of the wafer W ₆ and the shutter 13 are performed in advance.
If the change pattern of the length x is programmed in the control mechanism that controls the reciprocating motion of the above, the entire invalid region β can be exposed.

The present invention has been described above based on the four examples, but the present invention is not limited to these examples. For example, the material layer to be etched is not only the SiO ₂ interlayer insulating film described above, but also a polycrystalline Si layer, a polycide film, a refractory metal layer, a refractory metal silicide film, an Al-based material layer, etc. Therefore, any material layer may be used as long as it is a material layer for which the end point determination is required.

Further, as the end point determining method, the emission analysis is adopted in the above-mentioned embodiment, but the same good result can be obtained by applying the mass spectrometry method, the probe method or the like. In addition, it goes without saying that the configuration of the exposure apparatus, the wavelength of the exposure light, the type and configuration of various material layers on the wafer, the outline of the chip acquisition region, and the like can be changed as appropriate.

[0041]

As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention, the etching area is small, and it is difficult to determine the end point by the conventional etching.
Also in the process, it is possible to make a sharp end point determination. This is achieved by removing the etching mask in the ineffective region and has no effect on the pattern of the chip forming region.

The ineffective areas are selectively exposed, especially if the etching mask is constituted by a layer of positive photoresist material. The exposure apparatus proposed by the present invention for performing this outer periphery exposure has a relatively simple configuration and can be downsized. Therefore, it is not necessary to use an extremely expensive stepper once for the peripheral exposure, and there is no fear of impairing the throughput or the economy.

The present invention is extremely effective in manufacturing a semiconductor device which is designed based on a fine design rule and which requires high integration, high performance, high reliability and the like.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a process example in which the present invention is applied to contact hole processing, and FIG. 1 (a) is a perspective view showing an appearance of a wafer from which a resist mask in an ineffective region is removed,
(B) is a perspective view showing the appearance of a wafer having a SiO ₂ interlayer insulating film etched, and (c) is a graph showing the time change of CO ^* emission spectrum intensity in this etching process.

FIG. 2 is a diagram showing a configuration example of an exposure apparatus of the present invention,
(A) is a top view and (b) is the sectional view on the AA line.

FIG. 3 is a diagram illustrating an exposure method using the above exposure apparatus, FIG. 3A is a plan view showing an exposure region on a wafer,
(B) is a perspective view showing the state of the wafer from which the resist mask has been removed corresponding to this exposure region, and (c) is a graph explaining the movement of the shutter of the exposure apparatus which enables this exposure.

FIG. 4 is a plan view showing a model of a wafer when the entire invalid area is exposed using the exposure apparatus.

5A and 5B are views for explaining a calculation method for expressing the shutter length as a function of a rotation angle in the model of FIG. 4, where FIG. 5A is a plan view of a wafer and FIG. It is a graph to do.

FIG. 6 is a plan view showing another model of the wafer when the entire invalid area is exposed using the above-mentioned exposure apparatus.

7A and 7B are views for explaining a calculation method for expressing the shutter length as a function of a rotation angle in the model of FIG. 6, where FIG. 7A is a plan view of a wafer and FIG. It is a graph to do.

FIG. 8 is a schematic cross-sectional view for explaining the etching process of the SiO ₂ interlayer insulating film in the contact hole processing, FIG. 8A is a state in which a resist mask is patterned on the SiO ₂ interlayer insulating film, b) is SiO ₂
The state where the etching of the interlayer insulating film is in progress, and (c) shows the state where the etching is completed.

FIG. 9 is a diagram for explaining a problem of detecting an etching end point in conventional contact hole processing;
(A) is a perspective view showing the external appearance of the wafer, and (b) is a graph showing that the time change of CO ^* emission spectrum intensity in this etching process can hardly be detected.

[Explanation of symbols]

1 ・ ・ ・ Single crystal Si substrate 2 ・ ・ ・ Impurity diffusion region 3 ・ ・ ・ SiO ₂ interlayer insulating film 4 ・ ・ ・ Resist mask α ・ ・ ・ Chip acquisition region β ・ ・ ・ Invalid region W, W ₁ , W ₂ , W ₃ , W ₄ , W ₅ , W ₆ ... Wafer 12 ... Slit 13 ... Shutter 14 ... Pinion 15 ... High-pressure mercury lamp 17 ... Rotary wafer stage

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, wherein an etching end point is detected when a material layer to be etched on a substrate is etched through an etching mask. Prior to the etching, the outer peripheral side of a chip acquisition region on the substrate. A method for manufacturing a semiconductor device, characterized in that the material layer to be etched is exposed by removing at least a part of the etching mask on the ineffective region occupying the area. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching mask is composed of a positive photoresist material layer, and the etching mask is removed by selective exposure and development processing. . 3. A light source, a slit whose opening length in the longitudinal direction is variable, and a control means for changing the exposure area of the substrate by the exposure light passing through the slit, and the substrate is formed into an arbitrary shape. An exposure apparatus adapted to perform selective exposure. 4. The exposure apparatus according to claim 3, wherein the control unit controls the reciprocating movement of the shutter for changing the opening length of the slit and the rotational movement of the substrate in an interlocking manner. . 5. The exposure region is at least a part of an ineffective region occupying an outer peripheral side of a chip acquisition region on the substrate, and the exposure light exposes a positive photoresist material layer on the ineffective region. Claim 3 or Claim 4 made
The exposure apparatus described.