JPH0644141A - Memory information read system - Google Patents

Abstract

PURPOSE:To prevent the content of general-purpose ROM from illegally being read and analyzed from an external in a device using CPU and general-purpose ROM. CONSTITUTION:CPU 1 is connected with an address decoder 2, RAM 3 and ROM 4 by an address bus 7 and is connected with ROM 4 by data lines 8 and 9, a data line switching circuit 5, a data bus 10 and a data conversion circuit 6 exchanging the bit of data. The address decoder 2 selects RAM 3 and ROM 4 and controls the line switching circuit 5. When CPU 1 reads ROM 4, it reads data whose bit is exchanged by the data conversion circuit 6. Furthermore, the circuits, namely, at least parts except for RAM 3 and ROM 4 are composed of the control circuit 13 of the same single package LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory information reading system, and more particularly to a memory information reading system for an external memory of a CPU.

[0002]

2. Description of the Related Art Information (software) for the operation of a CPU is retained in a memory such as a ROM, an address line,
The method of operating the CPU by connecting the ROM and the CPU with a data line is generally popular. In that case, ROM
Stores information in a language and format according to the functional specifications of the CPU to be operated, and the CPU reads and recognizes the information read from the ROM according to predetermined specifications and operates. The functional specifications of the CPU are generally widely disclosed for each model.

In the conventional memory information reading method, a mask ROM storing software is used in the same LSI as the CPU.
In the one-chip control circuit of the type built into
The capacity of the built-in ROM of the PU is only 32 kbytes at the maximum, which is insufficient for realizing complicated functions, and the mask ROM cannot rewrite the stored contents, which lengthens the development period and increases the cost. For these reasons, a general-purpose ROM is tried outside the CPU, the external general-purpose ROM is connected by an address line and a data line, and the CPU reads the contents of the general-purpose ROM. Has become.

[0004]

In this conventional memory information reading method, the operating specifications of the CPU are widely disclosed, so that an apparatus having a structure for storing the operating information in a general-purpose ROM outside the CPU may be used. There is a problem that it is relatively easy for the obtained third party to read the memory contents of the general-purpose ROM and analyze the operation of the device.

Further, in recent years, for the purpose of preventing illegal use or theft of the device, it is often the case that a safety measure that operates only by a limited operation is constructed by software stored in the memory. As described above, the fact that the information (software) in the general-purpose ROM can be easily decrypted by a third party causes a problem that the device can be illegally used. Furthermore,
Even if the software does not have the above-mentioned security measures, the fact that the software can be freely read and decrypted by a third party has a problem that copyright and other rights of the manufacturer are likely to be infringed.

Further, as described above, if a control circuit of a type in which a mask ROM is built in one chip is used, the information of the mask ROM cannot be read from the outside, but the security problem is solved. There is a problem that it cannot be a practical means due to the limitation of the capacity of the mask ROM.

[0007]

According to the memory information reading method of the present invention, a CPU, a memory for storing operation information of the CPU, a signal line for transmitting and receiving data between the CPU and the memory, and the CPU And a conversion circuit that is configured in all or a part of the signal line and that converts the data read from the memory according to a certain predetermined rule.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a control circuit to which the first embodiment of the present invention is applied, and FIG. 2 is a diagram showing an example of a data conversion circuit in the control circuit shown in FIG.

In the control circuit 13 of this application example shown in FIG. 1, the CPU 1 is an 8-bit CPU, is connected to the RAM 3 and the ROM 4 by the address bus 7, and the address decoder 2 decodes the address information from the CPU 1. RAM3 / RO by controlling the RAM select signal 11 and the ROM select signal 12 by
Switching access to M4. The data line 8 of the CPU 1 is connected to the data line switching circuit 5, and the data line switching circuit 5 is connected to the data conversion circuit 6 by the data line 9. Further, the data line switching circuit 5, the data conversion circuit 6 and the RAM
3 and the ROM 4 are all connected by the data bus 10.

Here, in the data line switching circuit 5, when the RAM 3 is selected by the RAM select signal 11 and the ROM select signal 12 provided from the address decoder 2, the data line 8 is connected to the data bus 10 and the ROM 4 is selected. In this case, the data line 8 is connected to the data line 9.

Further, as shown in FIG. 2, the data conversion circuit 6 is configured so that D0 to D7 of the 8-bit data line 9 and D0 to D7 of the data bus 10 are interchanged and connected to each other.

Further, in this application example, the CPU 1, the address decoder 2, the data line switching circuit 5, the data conversion circuit 6 and the data line 8 are all configured as an internal circuit of the control circuit 13 of the LSI which is housed in the same single package. , The control circuit 13 and the RAM 3 when mounted on the device,
The three ICs of the ROM 4 are the address bus 7 and the data bus 1
0, the RAM select signal 11, and the ROM select signal 12 are connected.

With the above circuit configuration, the CPU 1 is a RAM
When accessing 3, the data is transmitted between CPU1 and RAM3 without exchanging bits and CPU1 is
When reading M4, the data whose bits have been exchanged by the data conversion circuit 6 is read. ROM
The data stored in 4 is written by exchanging the bits so that the data can be read in the correct format when viewed from the CPU 1 when the bits are exchanged by the data conversion circuit 6 in advance.

FIG. 2 is a block diagram of a control circuit to which the second embodiment of the present invention is applied.

The control circuit 13a of this application example shown in FIG.
Differently from the control circuit 13 shown in FIG. 1, the control signal 14 of the data line switching circuit 5a is independent of the RAM select signal 11 and the ROM select signal 12, and the address decoder circuit 2 allows the CPU 1 to access a predetermined address. In this case, the data line switching circuit 5a is switched.

The gist of the present invention is that the bits of all or a part of the data flowing to the outside of the control circuits 13 and 13a on the RAM 3, ROM 4 or panel are set by the configurations as seen in the above two application examples. , And the data read by the CPU 1, that is, the data obtained by decoding the bit replacement is to form a circuit that exists only as an internal signal of the control circuits 13 and 13a.

[0018]

As described above, according to the present invention, the CPU
The data read by the CPU, that is, the data in which the bit permutation is decoded exists only as an internal signal of the control circuit mounting the CPU, and a third party takes out the ROM connected to the control circuit from the device equipped with the control circuit, or the device. Even if a signal is taken out from the upper data line and an attempt is made to analyze the data, only the bit-swapped data can be easily read, making it impossible to analyze the data in a format that is widely disclosed to the CPU specifications. There is an effect that can be.

Therefore, the present invention makes it extremely difficult to analyze the data in the ROM externally connected to the CPU, that is, to analyze the operation of the device equipped with the control circuit in which the CPU is mounted, whereby the software There is an effect that the confidentiality can be protected more strongly.

[Brief description of drawings]

FIG. 1 is a block diagram of a control circuit to which a first embodiment of the present invention is applied.

FIG. 2 is a diagram showing an example of a data conversion circuit in the first embodiment.

FIG. 3 is a block diagram of a control circuit to which a second embodiment of the present invention is applied.

[Explanation of symbols]

 1 CPU 2 Address Decoder 3 RAM 4 ROM 5, 5a Data Line Switching Circuit 6 Data Conversion Circuit 7 Address Bus 8 Data Line (8 Bit Parallel) 9 Data Line (8 Bit Parallel) 10 Data Bus (8 Bit Parallel) 11 RAM Select Signal 12 ROM select signal 13, 13a control circuit

Claims (1)

[Claims] 1. A CPU, a memory for storing operation information of the CPU, a signal line for transmitting and receiving data between the CPU and the memory, and all of the signal lines in a control circuit for mounting the CPU. Alternatively, a conversion circuit that is configured in a part and converts data read from the memory according to a predetermined predetermined law is provided in the memory by a person who does not know the predetermined law. A memory information reading method, which prevents reading and decoding the stored information.