JP2007310601A - Microcomputer and method for protecting its software - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer that enables software being executed by the microcomputer or intermediate information created by the software to be safely saved in a memory area outside the microcomputer without having to modify the software and to be rewritten from the outside memory area. <P>SOLUTION: The microcomputer has a CPU, an internal memory, and a secure area determining part 101. The secure area determining part 101 has a secure area range setting register 111, a secure area validating register 110, an address determining part 113, and a secure area flag control part 115 for determining authority to access a secure area based on the result of the determination by the address determining part 113, a command from a bus, and the information of the secure area validating register and for outputting a secure area flag 120 reporting the result of the determination. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a microcomputer, and more particularly to a technique for protecting software running on a microcomputer and intermediate data generated in a process used by the software.

  In recent years, as the network environment has become broadband, a wide variety of information has become available from the network, and it has become easier to view and obtain digital content, and the importance and convenience of information distributed on the network. Has increased.

  In addition, as storage recording density increases and miniaturization, embedded devices called information home appliances other than personal computers (hereinafter referred to as PCs) such as hard disk (hereinafter referred to as HDD) recorders, portable music players, and mobile phones are also included. A large amount of digital data can be saved.

  On the other hand, loss of notebook PCs, leakage of personal information due to theft, illegal duplication of digital contents, etc. are widely taken up by mass media, and the importance of information security technology is increasing. The basis of information security technology is cryptographic technology, which is used mainly in the network world for the realization of secure communication with specific parties and the prevention of unauthorized use of information.

  As described above, built-in devices have been equipped with network functions and digital data processing functions, and at the same time, there has been an increasing demand for information security technologies including cryptographic processing. In order to realize the cryptographic processing, there are roughly two ways: realization by hardware dedicated to cryptographic processing and realization by software. For embedded devices such as information appliances where price competition is intense, product development and cost reduction during production are important factors. Generally, hardware is superior in terms of cryptographic processing performance. Since there is a tendency for product costs to increase, such as the amount of investment associated with the development of dedicated products when there is no chip to be used in the world, software implementation is often adopted.

  However, software is considered less secure in terms of security than hardware. This is because hardware can be processed secretly in the chip and expensive equipment and advanced knowledge are required for analysis, whereas in software chips such as SDRAM used as the main memory of a microcomputer Since information is stored in an external memory, there is a high risk that the information will be wiretapped, and the software object program itself is converted back into a source program using a disassembler, etc. This is because there are many analysis methods that can be easily executed compared to hardware.

  Conventionally, a technique called obfuscation of a software program is applied to such a problem, for example, the difficulty of reverse analysis is increased by complicating the logic of the program, and further, the disassembler is realized by encrypting the program itself. The so-called tamper resistance of software has been improved, for example, so that the analysis cannot be performed by using it.

Japanese Patent Laid-Open No. 2001-230770 (Patent Document 1) encrypts the program itself, decrypts it inside the microcomputer when the program is executed, and does not output the information obtained by the decryption outside the microcomputer. By providing such a mechanism, confidential information is prevented from being exposed outside the microcomputer. In addition, when it is necessary to switch the process being executed by the central processing unit (hereinafter referred to as CPU), the data (context) used by the CPU for encryption is encrypted and output to an external memory, and the context is written. By providing decryption means for returning, safe output of secret information during software execution is realized.
JP 2001-230770 A

  A microcomputer mounted on an embedded device has a smaller calculation performance and a memory capacity mounted inside the microcomputer than a processor for a PC. In addition, since cryptographic processing software requires more operations than general software, it is important to speed up cryptographic processing in embedded devices. As an example for improving the cryptographic processing performance, reusable intermediate information generated in the cryptographic processing calculation process is stored in the memory without being erased, so that the time required for the calculation can be reduced. There is a technique to reduce.

  From the viewpoint of improving tamper resistance, it is necessary to store a software program that handles secret information such as cryptographic processing and intermediate information including secret information generated by the program in a memory inside the microcomputer.

  However, the microcomputer for embedded devices has a limited memory capacity mounted inside the microcomputer, and it may be difficult to retain intermediate information generated during the cryptographic process, resulting in improved cryptographic processing performance. There was a problem that it might be difficult.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to safely save software written in the microcomputer and intermediate information generated by the software to a memory area outside the microcomputer without modifying the software, and write back from the external memory area. An object of the present invention is to provide a microcomputer that can be used.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A microcomputer according to the present invention includes a central processing unit, an internal memory for storing information, and a secure area determining unit that determines access to a secure area for storing secret information set in the internal memory, The secure area determination unit obtains an address from the secure area range setting register that sets the secure area range of the secure area, the secure area valid register that sets whether the secure area is valid or invalid, and the bus to which the secure area determination unit is connected Then, based on the address, the address determination unit that determines whether the access is to the secure area, the determination result by the address determination unit, the command from the bus, and the secure area valid register information to the secure area Determines the access authority of the user, and issues a secure area flag to notify the determination result. Those having a secure area flag control unit for.

  A microcomputer software protection method according to the present invention is a microcomputer software protection method including a central processing unit and an internal memory for storing information, and includes a secure area range setting register and a secure area valid register. Set the secure area range of the secure area and the validity or invalidity of the secure area, obtain the address from the bus in the microcomputer, determine whether the access is to the secure area based on the address, and the determination result The access authority to the secure area is determined based on the command from the bus and the secure area valid register information, and the secure area flag for notifying the determination result is output as a secure area signal to the outside of the central processing unit. Is.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, software running on a microcomputer and intermediate information generated by the software can be safely saved to a memory area outside the microcomputer only by hardware without modification of the software, and can be written from the external memory area. It can be returned.

  Also, it is possible to reduce deterioration in transfer performance between the microcomputer and the external memory due to the encryption process by encrypting only the data that needs to be encrypted instead of encrypting all the data output to the external memory. It becomes possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<Microcomputer configuration>
A configuration of a microcomputer according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a configuration of a secure area determination unit in a CPU of a microcomputer according to an embodiment of the present invention. FIG. 2 is a diagram showing a memory area of the microcomputer according to an embodiment of the present invention. 3 is a diagram showing the overall configuration of the microcomputer according to the embodiment of the present invention, and FIG. 4 is a diagram showing the configuration of the bus bridge of the microcomputer according to the embodiment of the present invention. 2 shows a configuration relating to an area control and an encryption processing section. FIG. 5 is a diagram showing the configuration of the secure area determination unit in the bus bridge of the microcomputer according to the embodiment of the present invention.

  In FIG. 1, a secure area determination unit 101 determines access to a secure area, presence / absence of encryption processing at the time of transfer to the external memory area, and presence / absence of decryption processing at the time of transfer from the external memory area. And is described in positive logic (1 when the signal is valid, 0 when the signal is invalid).

  The secure area valid register 110 indicates whether the secure area is valid / invalid. The secure area is valid only when this setting is valid, and the secure area flag control unit 115 operates.

  As shown in FIG. 2A, the secure area is set in an internal memory area of the microcomputer, and an arbitrary capacity can be set in the internal memory.

  The data in the secure area is only output when encrypted and output to the register used by the arithmetic unit in the CPU and the external memory area connected to the microcomputer as shown in FIG. 2B. It is set to permit transfer from the secure area, and transfer to an internal memory area other than the secure area is not permitted.

  The secure area range setting register 111 is a register that sets a secure area in the internal memory, and is variable by the user. However, the secure area that can be set is a range that does not exceed the internal memory area that can be used by the user in the microcomputer defined in the address map 112.

  The address determination unit 113 acquires an address from the bus to which the secure area determination unit 101 is connected, refers to the values of the secure area range setting register 111 and the address map 112, and stores the internal memory other than the secure area and the secure area The other area such as the area and the external memory area is determined and the area information is transmitted to the secure area flag control unit 115.

  When the setting of the secure area valid register 110 is valid, the secure area flag control unit 115 uses the area information from the address determination unit 113 and the command (read / write) information from the bus to which the secure area determination unit 101 is connected. The validity / invalidity of the secure area flag and the access violation are determined. If the access to the secure area is valid, the secure area flag 120 is validated, and if there is an access violation, the error flag 121 is validated.

  The secure area flag register 116 is a signal having the secure area flag as an original signal, and is added as a flag to a register used by an arithmetic unit inside the CPU. The secure area flag register indicates whether the data used by the arithmetic unit in the CPU is data in the secure area. When the secure area flag register is valid, the data stored in the register is treated the same as the data stored in the secure area.

  The secure area flag clear 114 becomes effective when processing related to the secure area flag is completed, and clears the internal state of the secure area flag control unit. That is, the secure area flag is cleared by clearing the secure area flag.

  In FIG. 3, the microcomputer 201 includes a CPU 212, a cache 213, a bus bridge 214, an internal memory 215, an external bus controller 221, a DMA controller 222, a peripheral bus controller 223, a clock generator 224, a timer 225, an interrupt controller 226, It is composed of an I / O controller 227, a CPU bus 211, an internal bus 220, and the like. The microcomputer 201 is connected to the external memory 231 and the external device 232 via the external bus 230.

  A secure area determination unit 101 shown in FIG. 1 is built in the CPU 212 and is connected to an address on the CPU bus 211 and a position where a command can be acquired (for example, an interface unit with the CPU bus 211 in the CPU 212). Access control to the secure area secured in 215 is performed.

  The secure area signal 130 output from the secure area determination unit 101 is connected between the CPU 212 and the bus bridge 214, and the DMA secure area signal 240 is connected between the bus bridge 214 and the DMA (direct memory access) controller 222.

  This connection is made by using a dedicated bus or the like, and the secure area signal 130 and the DMA secure area signal 240 can be exchanged independently of other signals. It is also possible to exchange the secure area signal 130 and the DMA secure area signal 240 using the CPU bus 211 and the internal bus 220 that are normally used instead of a dedicated bus or the like.

  The bus bridge 214 has functions such as communication protocol conversion between the CPU bus 211 and the internal bus 220, and access right adjustment.

  4, the secure area determination unit 301 has a function equivalent to that of the secure area determination unit 101 illustrated in FIG. 1, but is not related to the calculation register in the CPU 212. It is equipped with a reduced version of function 1.

  The secure area signal input / output control unit 302 inputs the secure area signal 130 at the time of transfer from the CPU bus 211 side and transmits it to the encryption instruction signal 320, and at the time of transfer from the internal bus side, the information of the decryption instruction signal 321 is received. Transmit to the secure area signal 130.

  The encryption processing unit 304 performs encryption when the encryption instruction signal based on the secure area signal 130 is valid, and performs decryption processing when the decryption instruction signal 321 is valid.

  The switch 305 transfers the encrypted data from the encryption processing unit to the internal bus side when the encryption instruction signal 320 is valid, and transfers the data from the internal bus side to the encryption processing unit when the decryption instruction signal 321 is valid. Forward. When both the encryption instruction signal 320 and the decryption instruction signal 321 are invalid, the data is transferred through a path that does not pass through the encryption processing unit.

  The encrypted data transfer destination determination unit 307 and the encrypted data transfer destination storage unit 308 store the transfer destination address of the encrypted data, and write the encrypted data back to the CPU arithmetic register and secure area. It is used to determine whether or not there is a decoding process.

  In addition, the encrypted data transfer destination determination unit 307 and the encrypted data transfer destination storage unit 308 always determine an address, and do not perform encryption on the address stored in the encrypted data transfer destination storage unit. When normal writing, that is, when data stored in the secure area is discarded, the corresponding address written in the encrypted data transfer destination storage unit is erased.

<Operation of microcomputer>
Next, the operation of the microcomputer according to the embodiment of the present invention will be described with reference to FIGS. 6 to 8 are flowcharts showing the control operation during data transfer by the CPU of the microcomputer according to the embodiment of the present invention. FIGS. 9 and 10 are direct memories of the microcomputer according to the embodiment of the present invention. It is a flowchart which shows the control action at the time of the data transfer by an access controller.

  First, as a control operation when the CPU 212 reads from the internal memory area to the CPU calculation register, as shown in FIG. 6, when a read request to the CPU calculation register is generated by the CPU 212 (step 501), the secure area The flag control unit 115 determines whether the read is from the secure area (step 502).

  If the read request is from a non-secure area, normal read processing is executed (step 503). If the read request is from the secure area, the secure area flag is validated (step 504). The secure area flag register 116 of the operation register in which the processed data is stored is validated (step 505).

  Thereafter, the read data from the secure area is stored in the calculation register (step 506), and when an operation occurs on the read data (step 507), the calculation result storage destination register is also secured. Enable the region flag register.

  After the calculation, the secure area flag control unit 115 is initialized by enabling the secure area flag clear 114 (step 508).

  At this time, the value of the secure area flag register 116 is not cleared, and is retained until the data stored in the arithmetic register is discarded or overwritten.

  As described above, in this embodiment, the data stored in the secure area is appended with information indicating that the data is in the secure area until the data is discarded. Realize protection.

  Further, as a control operation at the time of writing data stored in the CPU calculation register by the CPU 212, as shown in FIG. 7, when a write request for the CPU calculation register storage data is generated by the CPU 212 (step 601), the secure area The flag control unit 115 checks the secure area flag register 116 of the calculation register in which the data to be written is stored (step 602).

  If the secure area flag register 116 is invalid, it is processed as a normal write (step 603). If the secure area flag register 116 is valid, it is determined whether the write destination address is an internal address area (step 604). ).

  If the write destination address is an internal address area, it is determined whether it is a secure area (step 605), and if it is a secure area, the secure area flag is validated (step 607).

  If it is not a secure area, data for which the secure area flag register is valid, that is, data in the secure area is prohibited to access an internal memory area other than the secure area. Execute (step 606).

  The error processing described here may be processing that can be executed by a normal microcomputer, such as an access violation to a memory area without access right or a violation caused by specifying a memory area that does not exist.

  If the internal address space is not determined in step 604, the secure area flag is validated (step 607). In step 607, the secure area signal 130 is validated (step 608), and the CPU 212 writes the data stored in the CPU calculation register to the bus bridge 214 (step 609). When a signal indicating completion of data reception, that is, completion of write processing by the CPU 212 is received from the bus bridge 214 (step 610), the secure area flag clear unit 114 is enabled to initialize the internal state of the secure area flag control unit 115. (Step 611), the secure area signal 130 is invalidated (Step 612).

  Since the bus bridge 214 received the data with the secure area flag being valid, the data is encrypted by the encryption processing unit 304 and transferred to the internal bus side, and the encrypted data transfer destination storage unit 308 stores the encrypted data. Store the forwarding address.

  In addition, as shown in FIG. 8, as a control operation when the CPU 212 reads from the external memory space to the CPU calculation register, the read request from the CPU 212 is performed in the CPU as described above in step 502 shown in FIG. The secure area determination unit 101 processes a read request other than a read request from the secure area. At this time, the processing related to the secure area is executed in the bus bridge 214 shown in FIG.

  When a read request from the external memory to the CPU calculation register is generated from the CPU 212 to the bus bridge 214 (step 701), the CPU 212 requests the encrypted data transfer destination determination unit 307 and the encrypted data transfer destination storage unit 308. It is determined whether the read source address is the data transferred after encryption by the encryption processing unit 304 (step 702).

  If the result of determination in step 702 is an address that is not stored in the encrypted data transfer destination storage unit 308, that is, data in an area other than the secure area, it is executed as normal read processing (step 703).

  If the data is stored in the encrypted data transfer destination storage unit 308, that is, the data stored in the secure area, the decryption instruction signal 321 is validated (step 704) and the secure area signal 130 is validated (step 705) After decryption by the encryption processing unit 304 (step 706), the decrypted data is transferred to the CPU 212 (step 707).

  When the CPU 212 receives data in a state where the secure area signal 130 is valid, the CPU 212 validates the secure area flag register 116 of the storage destination register, and executes processing as data stored in the secure area (step 708).

  When the bus bridge 214 receives the read completion signal from the CPU 212 (step 709), the secure area signal input / output control unit 302 disables the secure area signal 130 (step 710).

  As a control operation at the time of a transfer request from a secure area by the direct memory access (hereinafter referred to as DMA) controller 222, as shown in FIG. 9, the bus bridge 214 receives a transfer request from the DMA controller 222 (step 801). The secure area determination unit 301 determines whether the transfer request is from the secure area (step 802).

  If the result of determination in step 802 is not a transfer request from the secure area, normal DMA transfer is performed (step 803). If the transfer request is from the secure area, the secure area signal input / output control unit 302 performs encryption. The instruction signal 320 and the DMA secure area signal 240 are validated (steps 804 and 805).

  When the bus bridge 214 receives data from the secure area (step 806), the encryption processing unit 304 encrypts the received data (step 807).

  Received data from the encrypted secure area is transferred to the DMA controller 222 (step 808).

  At this time, the bus bridge 214 does not know the address to which the data encrypted by the DMA controller 222 is transferred, and therefore does not store the transfer destination address in the encrypted data transfer destination storage unit. The encrypted data transfer destination storage unit is shared by the bus bridge 214 and the DMA controller 222 or implemented in a system that can be managed in a unified manner, and the transfer destination address when the DMA controller 222 transfers the encrypted data in the secure area. Is stored.

  As a result, the CPU 212 reads the data stored in the secure area transferred to the external memory 231 by the DMA controller 222, or vice versa, the data is stored in the secure area transferred to the external memory 231 by the CPU 212. The data can be read by the DMA controller 222.

  When the transfer to the DMA controller 222 is completed (step 809), the bus bridge 214 invalidates the encryption instruction signal 320 (step 810) and invalidates the DMA secure area signal 240 (step 811).

  When the DMA controller 222 receives the DMA secure area signal 240 together with the received data from the bus bridge 214, the DMA controller 222 transfers the received data to the external memory 231 and stores the encrypted data transfer destination memory shared with the bus bridge 214. The transfer destination address is stored in the unit 308.

  As a control operation when the DMA controller 222 transfers to the secure area, as shown in FIG. 10, when the bus bridge 214 receives a transfer request from the DMA controller 222 (step 901), the encrypted data transfer destination determination is performed. The unit 307 and the encrypted data transfer destination storage unit 308 determine whether the transfer source address is data subjected to encryption processing (step 902). If the data is not encrypted, it is processed as a normal DMA transfer (step 903).

  If the data has been subjected to encryption processing, the secure area determination unit 301 determines whether the data is transferred to the secure area (step 904).

  If the data is not transferred to the secure area, the data stored in the secure area is prohibited from being transferred outside the secure area, and error processing is executed (step 905). In the case of transfer to the secure area, the decryption instruction signal 321 is validated (step 906).

  After the decryption process (step 907), transfer to the secure area is performed (step 908). After the transfer is completed (step 909), the decoding instruction signal 321 is invalidated (step 910).

  There are data in the CPU operation register and data in the cache 213 as locations where there is data to be kept secret inside the CPU 212 other than the internal memory.

  The CPU operation register data may be saved by an interrupt, a process switch, or the like, but there is a microcomputer that has a separate save register inside the CPU, and this can be avoided by using it.

  The data in the cache 213 is set to be prohibited from being output to the outside of the microcomputer. In a configuration that enables data output in the cache 213, information equivalent to the secure area flag register 116 can be added to each entry in the cache 213, and the secure area signal 130 can also be controlled in the cache 213. With this configuration, the data stored in the secure area can be encrypted and output to the outside of the microcomputer.

  As described above, as an embodiment, a mechanism for controlling the encryption processing unit 304, the encryption processing unit 304, the secure area signal 130, and the DMA secure area signal 240 is provided in the bus bridge 214 as shown in FIG. However, in the present embodiment, the configuration is not limited to this configuration, and a portion including a CPU 212, a cache 213, a bus bridge 214, and an internal memory 215 generally called a CPU core is connected to an external module. It is desirable to install in a location where all accesses to the internal memory 215 and the CPU 212 pass.

  In the description of the present embodiment, it is described that the check is performed based on the physical address flowing on the bus. The operating system that controls the microcomputer usually uses virtual addresses.

  This embodiment can also be applied to a system that handles virtual addresses. The hardware for converting the virtual space and the physical space includes secure area determination units 101 and 301 and a secure area signal 130 inside the memory management unit, and the secure area determination unit 101 determines an address after conversion to the physical space. As a result, the same effects as those of the above-described embodiment can be obtained.

  As described above, according to the present embodiment, software being executed in the microcomputer and intermediate information generated by the software can be safely saved to a memory area outside the microcomputer only by hardware without modification of the software, and externally It is possible to write back from the memory area.

  Also, it is possible to reduce deterioration in transfer performance between the microcomputer and the external memory due to the encryption process by encrypting only the data that needs to be encrypted instead of encrypting all the data output to the external memory. It becomes possible.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a microcomputer and can be applied to software being executed on the microcomputer and an embedded microcomputer that protects intermediate data generated in the process used by the software.

It is a figure which shows the structure of the secure area | region determination part in CPU of the microcomputer which concerns on one embodiment of this invention. It is a figure which shows the memory area of the microcomputer which concerns on one embodiment of this invention. It is a figure which shows the whole structure of the microcomputer which concerns on one embodiment of this invention. It is a figure which shows the structure of the bus bridge of the microcomputer based on one embodiment of this invention. It is a figure which shows the structure of the secure area | region determination part in the bus bridge of the microcomputer which concerns on one embodiment of this invention. It is a flowchart which shows the control action at the time of the data transfer by CPU of the microcomputer which concerns on one embodiment of this invention. It is a flowchart which shows the control action at the time of the data transfer by CPU of the microcomputer which concerns on one embodiment of this invention. It is a flowchart which shows the control action at the time of the data transfer by CPU of the microcomputer which concerns on one embodiment of this invention. It is a flowchart which shows the control operation at the time of the data transfer by the direct memory access controller of the microcomputer which concerns on one embodiment of this invention. It is a flowchart which shows the control operation at the time of the data transfer by the direct memory access controller of the microcomputer which concerns on one embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Secure area | region determination part, 110 ... Secure area | region effective register, 111 ... Secure area | region range setting register, 112 ... Address map, 113 ... Address determination part, 114 ... Secure area flag clear, 115 ... Secure area flag control part, 116 ... Secure area flag register, 120 ... Secure area flag, 121 ... Error flag, 130 ... Secure area signal, 201 ... Microcomputer, 211 ... CPU bus, 212 ... CPU, 213 ... Cache, 214 ... Bus bridge, 215 ... Internal memory, 220 ... Internal bus, 221 ... External bus controller, 222 ... DMA controller, 223 ... Peripheral bus controller, 224 ... Clock generator, 225 ... Timer, 226 ... Interrupt controller, 227 ... I / O controller, 230 External bus, 231 ... external memory, 232 ... external device, 240 ... secure area signal for DMA, 301 ... secure area determination section, 302 ... secure area signal input / output control section, 304 ... encryption processing section, 305 ... switch, 307 ... Encrypted data transfer destination determination unit, 308... Encrypted data transfer destination storage unit, 320... Encryption instruction signal, 321.

Claims (10)

A central processing unit;
Internal memory for storing information,
A secure area determination unit that determines access to a secure area for storing confidential information set in the internal memory,
The secure area determination unit
A secure area range setting register for setting a secure area range of the secure area;
A secure area valid register for setting valid or invalid of the secure area; and
An address determination unit that acquires an address from the bus to which the secure area determination unit is connected, and determines whether the access is to the secure area based on the address;
Based on the determination result by the address determination unit, the command from the bus, and the information of the secure area valid register, the access authority to the secure area is determined, and the secure area flag that notifies the determination result is output. And a region flag control unit. The microcomputer according to claim 1.
The microcomputer, wherein the secure area flag control unit determines an access violation to the secure area and outputs an error flag notifying the determination result. The microcomputer according to claim 1 or 2,
A register for holding the secure area flag is provided in a calculation register used by the central processing unit for calculation,
The microcomputer is characterized in that the central processing unit outputs the secure area flag to the outside as a secure area signal. The microcomputer according to claim 3.
An encryption processing unit that receives the secure area signal and executes an encryption process and a decryption process according to an instruction of the secure area signal;
A first encrypted information transfer destination storage unit for storing a transfer destination to the external memory when transferring the encrypted information to an external memory attached to the microcomputer;
An encryption information transfer destination determination unit that performs verification of information stored in the transfer source and the first encrypted information transfer destination storage unit when information is transferred from the external memory;
As a result of the verification by the encrypted information transfer destination determination unit, if the two match, the information transferred from the external memory is decrypted by the encryption processing unit, and when the decrypted data is transferred to the central processing unit, the secure processing is performed. A microcomputer characterized by effectively setting a region signal. The microcomputer according to claim 4.
An area determination unit for determining an area to be read by the direct memory access controller in the microcomputer;
The encryption processing unit executes encryption of information read from the secure area by the secure area flag,
A microcomputer, wherein the secure area signal is set to be valid when the encrypted information is transferred to the direct memory access controller by the encryption processing unit. The microcomputer according to claim 5, wherein
The direct memory access controller includes a second encrypted information transfer destination storage unit that stores a transfer destination of the encrypted information when the secure area signal is received together with the encrypted information. A microcomputer. The microcomputer according to claim 6, wherein
The microcomputer according to claim 1, wherein the first encrypted information transfer destination storage unit and the second encrypted information transfer destination storage unit are shared. A microcomputer software protection method comprising a central processing unit and an internal memory for storing information,
The secure area range setting register and the secure area valid register are used to set the secure area range of the secure area and the validity or invalidity of the secure area,
An address is obtained from the bus in the microcomputer, and based on the address, it is determined whether the access is to the secure area, and the determination result, the command from the bus, and the information of the secure area valid register are included. A microcomputer software protection method comprising: determining a right of access to the secure area based on the result; and outputting a secure area flag notifying the determination result to the outside of the central processing unit as a secure area signal. 9. The microcomputer software protection method according to claim 8,
When the secure area signal is received, an encryption process and a decryption process are executed according to an instruction of the secure area signal, and when the encrypted information is transferred to an external memory attached to the microcomputer, When the transfer destination is stored and information is transferred from the external memory, the information of the transfer source and the stored transfer destination are collated. If the result of the collation is the same, the information transferred from the external memory is A microcomputer software protection method, wherein the secure area signal is set valid when decrypted and the decrypted data is transferred to the central processing unit. The microcomputer software protection method according to claim 9,
The area read by the direct memory access controller in the microcomputer is determined, the information read from the secure area is encrypted by the secure area flag, and the encrypted information is transferred to the direct memory access controller. In this case, the microcomputer software protection method is characterized in that the secure area signal is set to be valid.

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