JPH0644113B2 - Active matrix liquid crystal display panel manufacturing method - Google Patents

Active matrix liquid crystal display panel manufacturing method

Info

Publication number
JPH0644113B2
JPH0644113B2 JP59182107A JP18210784A JPH0644113B2 JP H0644113 B2 JPH0644113 B2 JP H0644113B2 JP 59182107 A JP59182107 A JP 59182107A JP 18210784 A JP18210784 A JP 18210784A JP H0644113 B2 JPH0644113 B2 JP H0644113B2
Authority
JP
Japan
Prior art keywords
electrode
liquid crystal
crystal display
display panel
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59182107A
Other languages
Japanese (ja)
Other versions
JPS6159475A (en
Inventor
文博 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59182107A priority Critical patent/JPH0644113B2/en
Publication of JPS6159475A publication Critical patent/JPS6159475A/en
Publication of JPH0644113B2 publication Critical patent/JPH0644113B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔発明の属する分野の説明〕 本発明は、アクティブマトリクス液晶表示パネルの製造
時に発生する静電気によるMOSトランジスタへの損傷
をふせぐ製造方法に関するものである。
The present invention relates to a manufacturing method for preventing damage to a MOS transistor due to static electricity generated at the time of manufacturing an active matrix liquid crystal display panel.

〔従来の技術の説明〕[Description of conventional technology]

液晶材料の改良、パネル組立技術の向上等により、大容
量のマトリクス液晶表示パネルが実用化された。しかし
ながらこのマトリクス液晶表示パネルは、コントラス
ト、視角特性、応答速度等の表示特性が、電卓等の表示
特性と比較し、数段劣る。市場の要求として、表示容量
の大きなしかも、表示品位に優れた液晶表示パネルの実
用化が強く望まれている。この市動ニーズを背景に、液
晶表示パネルの一方の電極基板にMOS構造の薄膜トラ
ンジスタ(TFT)を、表示エレメントの数だけ設け、
そのスイッチング動作により、液晶表示パネルを時分割
駆動するアクティブマトリクス液晶表示パネルの開発が
進められている。このアクティブマトリクス液晶表示パ
ネルは各表示エレメントに、スタチック的に電圧が印加
されるので、表示特性に優れる特徴を有している。MO
S−TFTは、その薄膜半導体材料として、CdSeに
代表されるII−IV化合物半導体、Te、ポリシリコン、
アモルファスシリコン等が検討されている。これらのM
OS−TFTは、静電気による損傷をうけやすく、一方
において液晶表示パネルは、その製造工程で静電気を帯
びやすい故、液晶表示パネルの歩留を低下させている。
Large-capacity matrix liquid crystal display panels have been put to practical use due to improvements in liquid crystal materials and panel assembly technology. However, this matrix liquid crystal display panel is inferior in display characteristics such as contrast, viewing angle characteristics, response speed and the like to those of a calculator or the like. As a market demand, there is a strong demand for practical use of a liquid crystal display panel having a large display capacity and excellent display quality. Against the background of this market need, a thin film transistor (TFT) having a MOS structure is provided on one electrode substrate of the liquid crystal display panel by the number of display elements,
Development of an active matrix liquid crystal display panel that drives the liquid crystal display panel in a time division manner by the switching operation is in progress. This active matrix liquid crystal display panel has characteristics that display characteristics are excellent because a voltage is statically applied to each display element. MO
The S-TFT includes II-IV compound semiconductor represented by CdSe, Te, polysilicon, and
Amorphous silicon is being studied. These M
The OS-TFT is easily damaged by static electricity, while the liquid crystal display panel tends to be charged with static electricity in the manufacturing process thereof, thus lowering the yield of the liquid crystal display panel.

〔発明の目的〕[Object of the Invention]

本発明の目的は、液晶表示パネルの製造工程で発生する
静電気をおさえ、MOS−TFTに損傷を与えないアク
ティブマトリクス液晶表示パネルの製造方法を提供する
ことにある。
An object of the present invention is to provide a method for manufacturing an active matrix liquid crystal display panel that suppresses static electricity generated in the manufacturing process of the liquid crystal display panel and does not damage the MOS-TFT.

〔発明の構成および作用の説明〕[Explanation of Structure and Action of Invention]

本発明による方法は、MOS構造の複数の薄膜トランジ
スタが行列状に配置形成された第1の電極基板と共通電
極を有する第2の電極基板とを有するアクティブマトリ
クス液晶表示パネルの製造方法において、前記複数の薄
膜トランジスタの行をなすゲート電極端子同志および列
をなす電極端子同志を短絡する接続部とこの接続部に連
続する共通電極端子とを前記第1の電極基板に形成する
工程と、前記接続部および前記共通電極端子を有する前
記第1の電極基板にラビング処理を施す工程と、前記第
1の電極基板の前記共通電極端子と前記第2の電極基板
の前記共通電極とを接続させつつ前記第1および第2の
電極基板を所定間隔を保ち対向させて組み立て、液晶を
封入する工程と、組み立て完了後前記接続部を前記第1
の基板から切断する工程とを含んでいる。
The method according to the present invention is a method of manufacturing an active matrix liquid crystal display panel, comprising: a first electrode substrate having a plurality of thin film transistors having a MOS structure arranged in a matrix and a second electrode substrate having a common electrode; Forming a connection part for short-circuiting the gate electrode terminals forming a row and the electrode terminals forming a column of the thin film transistor and a common electrode terminal continuous to the connection part on the first electrode substrate; Rubbing the first electrode substrate having the common electrode terminal, and connecting the common electrode terminal of the first electrode substrate and the common electrode of the second electrode substrate to each other. And a step of assembling the second electrode substrate so as to be opposed to each other with a predetermined space therebetween, and enclosing liquid crystal; and
And the step of cutting from the substrate.

以下、本発明について実施例を用い説明する。Hereinafter, the present invention will be described using examples.

一実施例のアクティブマトリクス液晶表示パネルの製造
方法に用いる液晶表示パネルの模式断面図を第1図に示
す。TFTが設けられた電極基板12と共通電極2が設
けられた電極基板1との間に液晶3が充填されている。
電極基板12にゲート電極11が所定のパターン状に形
成され、その上にゲート絶縁膜10が被われている。ゲ
ート絶縁膜上に半導体層9が所定のパターン状に形成さ
れ、その上にドレイン電極6、ソース電極7が設けられ
ており、ソース電極7は、表示電極8に接続されてい
る。ソース電極とドレイン電極間のチャンネル部を保護
する目的で絶縁膜5を設け、且つチャンネル部には、遮
光膜4が設けられている。図中13,14は、液晶分子
を配向させるための配向膜である。この配向膜は、有機
フィルムであり、布等で一方向にラビングして細溝が形
成されるが、この工程で静電気をおびやすい。又パネル
組み立て時乾燥雰囲気中で行なうため、電荷が両電極基
板間に蓄積される。第2図にマトリクス構成する場合の
ゲート電極、ソース電極、ドレイン電極の電気的接続を
示す。図に示す様にゲート電極は、n行に分割して結線
され、ドレイン電極はn列に分割して結線される。ソー
ス電極は、表示電極に結線されており、液晶層の静電容
量を介して共通電極(アース記号)に結線されている。
第3図は、本実施例の製造方法を説明するために用いる
液晶表示パネルの端子部を模式的に示したものである。
ゲート電極端子群G,G…G及びドレイン電極端
子群D,D…Dは、第1図の説明で明らかな様
に、同一電極基板12にあり、一方共通電極は、電極基
板1にあるが、この共通電極をトランスファ端子を介し
て電極基板12の共通電極端子COMに接続する。これ
らのゲート電極端子群ドレイン電極端子群及び共通電極
端子を電極基板12の4辺であらかじめ短絡される様に
電極をパターンニングする。
FIG. 1 shows a schematic cross-sectional view of a liquid crystal display panel used in the method for manufacturing an active matrix liquid crystal display panel of one embodiment. The liquid crystal 3 is filled between the electrode substrate 12 provided with the TFT and the electrode substrate 1 provided with the common electrode 2.
The gate electrode 11 is formed in a predetermined pattern on the electrode substrate 12, and the gate insulating film 10 is covered thereon. The semiconductor layer 9 is formed in a predetermined pattern on the gate insulating film, and the drain electrode 6 and the source electrode 7 are provided on the semiconductor layer 9, and the source electrode 7 is connected to the display electrode 8. An insulating film 5 is provided for the purpose of protecting the channel portion between the source electrode and the drain electrode, and the channel portion is provided with the light shielding film 4. In the figure, 13 and 14 are alignment films for aligning liquid crystal molecules. This alignment film is an organic film and is rubbed in one direction with a cloth or the like to form fine grooves, but static electricity is easily generated in this step. Further, since the panel assembly is performed in a dry atmosphere, electric charges are accumulated between both electrode substrates. FIG. 2 shows the electrical connection of the gate electrode, the source electrode, and the drain electrode in the case of forming a matrix. As shown in the figure, the gate electrode is divided into n rows and connected, and the drain electrode is divided into n columns and connected. The source electrode is connected to the display electrode, and is connected to the common electrode (earth symbol) via the capacitance of the liquid crystal layer.
FIG. 3 schematically shows a terminal portion of a liquid crystal display panel used for explaining the manufacturing method of this embodiment.
The gate electrode terminal groups G 1 , G 2 ... G n and the drain electrode terminal groups D 1 , D 2 ... D m are on the same electrode substrate 12, as is apparent from the explanation of FIG. 1, while the common electrode is Although on the electrode substrate 1, this common electrode is connected to the common electrode terminal COM of the electrode substrate 12 via the transfer terminal. The electrodes are patterned so that the gate electrode terminal group, the drain electrode terminal group, and the common electrode terminal are short-circuited in advance on the four sides of the electrode substrate 12.

第1図に示した構成のTFT電極基板12は、上述した
様にラビング工程で静電気を帯電しやすいが、第3図で
説明した様にゲート電極及びドレイン電極が端子部で短
絡されているので、TFTが損傷されることはない。
又、TFT電極基板12と共通電極基板1を一定間隙を
保ち組み立て、液晶を充填する注入孔を除いて周囲を接
着剤でシールするが、第3図で説明した様に共通電極は
ドレイン電極、ゲート電極と短絡されているので、両電
極基板間に電荷が帯電することはない。注入孔より液晶
材を充填し、その注入孔を封孔し、偏光板を貼付して、
液晶表示パネルが完成する。偏光板面をこすったり、あ
るいは偏光板の保護シートをはずす時、両電極基板間に
電荷が帯電し、液晶分子配向が一時的に乱れる現象が観
察されるが、本実施例の製造方法では、短絡されている
のでこの電荷帯電を防止できる。第3図(a),(b)で示し
た短絡は、この液晶表示パネルをモジュールに組み込む
時、第3図の一点鎖線の部分を切断することにより、開
放する。
The TFT electrode substrate 12 having the configuration shown in FIG. 1 is easily charged with static electricity in the rubbing process as described above, but since the gate electrode and the drain electrode are short-circuited at the terminal portion as described in FIG. , The TFT is not damaged.
In addition, the TFT electrode substrate 12 and the common electrode substrate 1 are assembled with a constant gap, and the periphery is sealed with an adhesive except for the injection hole for filling the liquid crystal. As described in FIG. 3, the common electrode is the drain electrode, Since it is short-circuited with the gate electrode, no electric charge is accumulated between both electrode substrates. Fill the liquid crystal material through the injection hole, seal the injection hole, attach the polarizing plate,
The liquid crystal display panel is completed. When rubbing the polarizing plate surface or removing the protective sheet of the polarizing plate, a phenomenon in which electric charge is charged between the electrode substrates and the liquid crystal molecule orientation is temporarily disturbed is observed, but in the manufacturing method of this example, Because of the short circuit, this charge charging can be prevented. The short circuit shown in FIGS. 3 (a) and 3 (b) is opened when the liquid crystal display panel is incorporated into a module by cutting the portion indicated by the alternate long and short dash line in FIG.

以上、実施例により、本発明について説明したが、アク
ティブマトリクス液晶表示パネルの製造工程での静電気
発生は、ゲート電極端子、ドレイン電極端子及び共通電
極端子を短絡することにより、おさえられるので、TF
Tの静電気による損傷から守られるので、液晶表示パネ
ルの歩留を著しく向上させることが出来る。
Although the present invention has been described with reference to the embodiments, the static electricity generation in the manufacturing process of the active matrix liquid crystal display panel can be suppressed by short-circuiting the gate electrode terminal, the drain electrode terminal and the common electrode terminal.
Since the T is protected from damage due to static electricity, the yield of the liquid crystal display panel can be significantly improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は、アクティブマトリクス液晶表示パネルの模式
断面図、第2図は、ゲート電極、ドレイン電極、ソース
電極、表示電極、共通電極の電気的接続を示した回路
図、第3図(a),(b)は、本発明を説明するために用いた
実施例の短絡手段を説明するための液晶表示パネルの端
子部を示す平面図および側面図である。 図中、1……共通電極基板、12……TFT電極基板、
11……ゲート電極、10……ゲート絶縁膜、9……半
導体層、6……ドレイン電極、7……ソース電極、8…
…表示電極、5……保護膜、4……遮光膜、13,14
……配向膜、3……液晶材。
FIG. 1 is a schematic sectional view of an active matrix liquid crystal display panel, and FIG. 2 is a circuit diagram showing electrical connection of gate electrodes, drain electrodes, source electrodes, display electrodes, and common electrodes, FIG. 3 (a). , (B) are a plan view and a side view showing a terminal portion of a liquid crystal display panel for explaining the short-circuit means of the embodiment used for explaining the present invention. In the figure, 1 ... common electrode substrate, 12 ... TFT electrode substrate,
11 ... Gate electrode, 10 ... Gate insulating film, 9 ... Semiconductor layer, 6 ... Drain electrode, 7 ... Source electrode, 8 ...
... Display electrode, 5 ... Protective film, 4 ... Light-shielding film, 13,14
…… Alignment film, 3 …… Liquid crystal material.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】MOS構造の複数の薄膜トランジスタが行
列状に配置形成された第1の電極基板と共通電極を有す
る第2の電極基板とを有するアクティブマトリクス液晶
表示パネルの製造方法において、前記複数の薄膜トラン
ジスタの行をなすゲート電極端子同志および列をなす電
極端子同志を短絡する接続部とこの接続部に連続する共
通電極端子とを前記第1の電極基板に形成する工程と、
前記接続部および前記共通電極端子を有する前記第1の
電極基板にラビング処理を施す工程と、前記第1の電極
基板の前記共通電極端子と前記第2の電極基板の前記共
通電極とを接続させつつ前記第1および第2の電極基板
を所定間隔を保ち対向させて組み立て、液晶を封入する
工程と、組み立て完了後前記接続部を前記第1の基板か
ら切断する工程とを含むことを特徴とするアクティブマ
トリクス液晶表示パネルの製造方法。
1. A method of manufacturing an active matrix liquid crystal display panel, comprising: a first electrode substrate having a plurality of MOS structure thin film transistors arranged in a matrix; and a second electrode substrate having a common electrode. Forming a connection part for short-circuiting the gate electrode terminals forming the row and the column electrode terminals forming the thin film transistor and a common electrode terminal continuous to the connection part on the first electrode substrate;
Rubbing the first electrode substrate having the connecting portion and the common electrode terminal, and connecting the common electrode terminal of the first electrode substrate and the common electrode of the second electrode substrate. At the same time, the method includes the steps of assembling the first and second electrode substrates so as to face each other with a predetermined gap therebetween, enclosing a liquid crystal, and cutting the connection portion from the first substrate after completion of the assembly. Active matrix liquid crystal display panel manufacturing method.
JP59182107A 1984-08-31 1984-08-31 Active matrix liquid crystal display panel manufacturing method Expired - Lifetime JPH0644113B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59182107A JPH0644113B2 (en) 1984-08-31 1984-08-31 Active matrix liquid crystal display panel manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59182107A JPH0644113B2 (en) 1984-08-31 1984-08-31 Active matrix liquid crystal display panel manufacturing method

Publications (2)

Publication Number Publication Date
JPS6159475A JPS6159475A (en) 1986-03-26
JPH0644113B2 true JPH0644113B2 (en) 1994-06-08

Family

ID=16112456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59182107A Expired - Lifetime JPH0644113B2 (en) 1984-08-31 1984-08-31 Active matrix liquid crystal display panel manufacturing method

Country Status (1)

Country Link
JP (1) JPH0644113B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69319760T2 (en) * 1992-02-21 1999-02-11 Toshiba Kawasaki Kk Liquid crystal display device
JP3642876B2 (en) * 1995-08-04 2005-04-27 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device using plasma and semiconductor device manufactured using plasma

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54141155A (en) * 1978-04-25 1979-11-02 Sharp Corp Production of liquid crystal cell
JPS57136676A (en) * 1981-02-18 1982-08-23 Hitachi Ltd Liquid crystal display element
JPS59166984A (en) * 1983-03-14 1984-09-20 三菱電機株式会社 Manufacture of matrix type liquid crystal display

Also Published As

Publication number Publication date
JPS6159475A (en) 1986-03-26

Similar Documents

Publication Publication Date Title
US4821092A (en) Thin film transistor array for liquid crystal display panel
US5691793A (en) Liquid crystal display apparatus having gap adjusting means under the sealing region
US7671956B2 (en) Liquid crystal display panel and fabricating method thereof
JPS59501562A (en) Method for manufacturing a display screen using thin film transistors and capacitors
GB2329061A (en) Liquid crystal display and method of manufacturing the same.
JPS6247623A (en) Liquid crystal display device
US20020197776A1 (en) Thin-film transistor, liquid-crystal display device, and method of producing the same
JPS61230186A (en) Assembly for non-linear type control element for flat electrooptic display screen flat screen therefor
JP2521752B2 (en) Liquid crystal display
US5815231A (en) Liquid crystal display and method of manufacturing the same
US5432625A (en) Display screen having opaque conductive optical mask and TFT of semiconductive, insulating, and conductive layers on first transparent conductive film
JP3633250B2 (en) Liquid crystal device and manufacturing method thereof
US6459466B1 (en) Liquid-crystal display device with improved yield of production and method of fabricating the same
JPH0644113B2 (en) Active matrix liquid crystal display panel manufacturing method
JPS6242127A (en) Liquid crystal display unit with light blocking and cell spacer construction
JP3265687B2 (en) Liquid crystal display
JP3105187B2 (en) Color liquid crystal panel and manufacturing method thereof
JPH0580651B2 (en)
JPS6236687A (en) Display unit
JP3107778B2 (en) Color liquid crystal panel and manufacturing method thereof
JP3223394B2 (en) Manufacturing method of liquid crystal display device
JP2687967B2 (en) Liquid crystal display
KR100237677B1 (en) In-plane switching mode liquid crystal display device and its manufacturing method
JP2566130B2 (en) Method for manufacturing substrate for active matrix display device
JPS6145221A (en) Device for image display and its manufacture

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term