JPH0644089A - Information processor - Google Patents

Abstract

PURPOSE:To efficiently use the plural arithmetic operation units of plural instruc tion streams so is to execute them. CONSTITUTION:Plural operand buffers 51, 61, 71 and 81, the plural arithmetic operation units 52, 62, 72 and 82, plural register files 107-109, execution control parts 54, 64, 74 and 84 controlling the execution of the plural instruction streams and a context back-up memory 111 storing the context of the instruction stream are provided. The execution control parts 54, 69, 74 and 84 stops the execution of the instruction stream of an instruction which becomes a main cause when a specified event occurs or a specified state is detected, saves the context in the context back-up memory 111 and executes change-over to the new instruction stream context so as to start execution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for efficiently using a plurality of arithmetic units by issuing instructions of a plurality of instruction streams in parallel.

[0002]

2. Description of the Related Art As an example of a conventional information processing apparatus, there is a multi-thread processor which processes a plurality of instruction streams simultaneously in one processor. For this method,
“A Multi threaded Processor Architecture with Sim
ultaneous Instruction Issuing, ”In Proc. of ISS'9
1: International Symposium on Supercomputing, Fukuo
ka, Japan, pp.87-96, November 1991. FIG. 7 shows a block diagram of this conventional information processing apparatus. In FIG. 7, 200 is an instruction cache, 201 is an instruction fetch unit, 202 is a decoding unit, 203 is a standby station, 204 is an instruction schedule unit, 205 is a functional unit, and 206 is a register set. The operation of the conventional information processing apparatus configured as described above will be described.

Each instruction fetch unit 201 reads an instruction having a different instruction stream from the instruction cache 200.
Decoding unit 202 decodes each instruction stream instruction,
The instructions are stored in a standby station 203 connected to a functional unit 205 capable of processing. The instruction scheduling unit 204 selects the appropriate instruction from the standby station 203 and sends it to the functional unit 205. Functional unit 2
05 is executed using the register set 206.

A feature of this processor is that a plurality of instruction streams are shared by the arithmetic units and executed. Since the existing superscalar processing type processor multiplexes (multiplies) only the functional unit 205, only one instruction stream can be processed at the same time, and pipeline interlock frequently occurs due to the dependency between instructions. As a result, functional unit 205
It was difficult to improve the performance because the usage efficiency did not increase. Also,
In the processor of the conventional example, the instruction level parallelism can be increased by executing the instructions of a plurality of instruction streams in parallel, the usage efficiency of each functional unit can be increased, and the performance can be improved.

[0005]

However, the above configuration has the following problems. Functional unit 205
It is assumed that a cache miss occurs when a load instruction of a certain instruction stream is executed in one load / store unit. When a cache miss occurs, the cache updates the data from the main memory and the load / store unit falls into an interlock state. As a result, for a long time, the decoding unit 202 of the instruction stream that has caused the cache miss and the like waits for the instruction issuance, and the instruction following the load instruction cannot be executed. Then, the load / store unit cannot be used for the instructions of other instruction streams, and eventually the entire processor is stopped. In this way, if a pipeline interlock occurs at one place, it affects the entire processor and causes performance degradation.

In view of the above problems, it is an object of the present invention to provide an information processing apparatus which realizes high performance by reducing pipeline interlock and lock time in a processor which simultaneously executes a plurality of instruction streams.

[0007]

In order to solve the above problems, the present invention provides an information processing apparatus according to the first aspect of the invention, wherein a plurality of instruction preparation units, a plurality of operation execution units, and a plurality of operation execution units are provided. A register file and an instruction schedule section provided between the instruction preparation section and the operation execution section are provided, and when a specific event occurs or a specific state is detected, the instruction of the instruction causing the event It is characterized in that the execution of the flow is stopped, the context of the stopped instruction flow is saved in the memory, the context of the new instruction flow is stored from the memory, and the execution is started.

According to another aspect of the present invention, there is provided an information processing apparatus, comprising a plurality of instruction preparation units, a plurality of operation execution units, a plurality of register files, and an instruction schedule provided between the instruction preparation unit and the operation execution units. Section, an instruction stream execution control section that controls execution of a plurality of instruction streams, and a memory that stores the context of the instruction stream.The instruction stream execution control section generates a specific event or a specific state. When it is detected, the execution of the instruction stream that caused it is stopped, the context of the stopped instruction stream is saved in memory, the context of the new instruction stream is stored from memory, and execution is started. Is characterized by.

An information processing apparatus according to a third aspect of the present invention includes a plurality of instruction preparation units, a plurality of arithmetic execution units, and a plurality of register files at least more than the instruction preparation units.
An instruction schedule section provided between the instruction preparation section and the operation execution section, and an instruction stream execution control section for controlling the execution of a plurality of instruction streams are provided. The instruction stream assigned to the instruction preparation section is executed according to the register file, but when a specific event occurs or a specific state is detected, the instruction of the instruction that caused it It is characterized in that the execution of the newly assigned instruction stream is started by stopping the execution of the instruction stream, making the instruction preparation section assigned to that instruction stream correspond to the instruction stream that has not been assigned yet.

An information processing apparatus according to a fourth aspect of the present invention includes a plurality of instruction preparation units, a plurality of operation execution units, and a plurality of register files at least larger than the instruction preparation units.
The instruction flow execution control includes: an instruction scheduling unit provided between the instruction preparation unit and the operation execution unit; an instruction flow execution control unit that controls execution of a plurality of instruction flows; and a memory that stores a context of the instruction flow. The section associates the instruction stream with the instruction preparation section and the register file, and executes the instruction stream assigned to the instruction preparation section, but when a specific event occurs or a specific state is detected, Stops the execution of the instruction stream that was the cause, makes the instruction preparation section that was assigned to that instruction stream correspond to the instruction stream that has not been assigned, and It is characterized by starting execution.

An information processing apparatus according to a fifth aspect of the present invention is characterized in that a specific event that triggers the switching of instruction streams is a mishit during cache access.

In the information processing apparatus according to the sixth aspect of the present invention, when a specific event occurs or a specific state is detected, the instruction preparation assigned to the instruction stream of the instruction causing the event is prepared. It is characterized in that the execution of the section is stopped and the internal state of the instruction preparation section is initialized.

According to the information processing apparatus of the invention as set forth in claim 7, the context for saving and saving the execution of the instruction stream includes the first PC, and when the instruction stream is executed again, the execution is restarted from the first PC. It has a feature.

According to another aspect of the present invention, an information processing apparatus sets a specific event that triggers the switching of instruction streams as a mishit during cache access, and when a cache miss occurs, aborts the memory access instruction and ends normally. It is characterized by that.

According to the information processing apparatus of the present invention, when a new instruction stream is allocated to the instruction preparation section and the instruction execution is restarted, the memory access instruction which has been interrupted due to a switching factor is re-executed. It has a feature.

According to the information processing apparatus of the present invention, a specific event that triggers the switching of the instruction stream is regarded as a mishit at the time of cache access, and when saving the context of the instruction stream, the PC of the memory access instruction is saved. The feature is that they also evacuate together.

According to the information processing apparatus of the present invention, a specific event that triggers the switching of instruction streams is regarded as a mishit at the time of cache access, and a memory access instruction is also included when the context of the instruction stream is saved. It is characterized by retreating to.

An information processing apparatus according to a twelfth aspect of the present invention is characterized in that the memories for saving the context are on the same processor.

According to the information processing apparatus of the thirteenth aspect of the present invention, the instruction flow execution control unit does not allocate a specific state to the instruction flow whose context is saved in the memory and is not allocated to the instruction flow. If there is a register file, the context is restored to the register file and the instruction stream is assigned to the register file.

According to another aspect of the present invention, in an information processing device, a specific event that triggers a switching of instruction streams is regarded as a mishit during cache access, and a memory access address is also included when the context of the instruction stream is saved. It is characterized by retreating to.

An information processing apparatus according to a fifteenth aspect of the present invention is characterized in that a specific event that triggers the switching of instruction streams is set as an error related to memory access.

[0022]

In the information processing apparatus according to the first aspect of the present invention, the instruction stream in which the interlock has occurred is put into a sleep state (save) and the hardware mechanism is assigned to another instruction stream, that is, the instruction stream is switched and executed. Therefore, it is possible to reduce the interlock and lock time of the pipeline, improve the usage efficiency of the functional unit, and realize high performance.

In the information processing apparatus according to the second aspect of the present invention, the instruction stream in which the interlock has occurred is put in the sleep state, the context is saved in the memory, the context of the new instruction stream is restored, and the hardware mechanism is allocated. That is, by switching and executing the instruction streams, the pipeline interlock and lock time can be reduced, the usage efficiency of the functional units can be improved, and high performance can be realized.

In the information processing apparatus according to the third aspect of the present invention, by providing more register files than the instruction preparation unit, even if an interlock occurs, the context of the instruction stream in which the interlock occurs is stored in the memory. Since a new instruction stream can be executed without saving, a high-speed instruction stream switching can be performed.

In the information processing apparatus according to the fourth and thirteenth aspects of the present invention, the interlock is generated when the interlock is generated by providing more register files than the instruction preparation unit and a memory for saving the context. The context of the instruction stream is saved in the memory, but the context of the new instruction stream can be prepared in the register in advance, so switching between normal instructions and instruction streams can be performed overlappingly, so fast instruction stream switching is possible. You can

In the information processing apparatus according to the fifth aspect of the present invention, the specific event that triggers the switching of the instruction stream is a mishit during cache access,
The overhead at memory access can be reduced.

In the information processing apparatus according to the sixth aspect of the present invention, when a specific event occurs or a specific state is detected, the instruction assigned to the instruction stream of the instruction causing the event. By stopping the execution of the preparation section and initializing the internal state of the instruction preparation section, pipeline control becomes easier.

In the information processing apparatus according to the seventh aspect of the present invention, the context for saving and saving the execution of the instruction stream includes the head PC, and when the instruction stream is executed again, the execution is restarted from the head PC. This facilitates control of instruction switching.

According to another aspect of the information processing apparatus of the present invention, a specific event that triggers the switching of instruction streams is regarded as a mishit during cache access, and when a cache miss occurs, the memory access instruction is aborted and the processing ends normally. By doing so, control of instruction switching becomes easy.

In the information processing apparatus according to the ninth aspect of the present invention, when a new instruction stream is allocated to the instruction preparation section and the instruction execution is restarted, the memory access instruction that caused the switching and was aborted is re-executed. This facilitates control of instruction switching.

In the information processing apparatus according to the tenth aspect of the present invention, a specific event that triggers the switching of instruction streams is regarded as a mishit at the time of cache access, and when the context of the instruction stream is saved, a memory access instruction PC
Also, by saving together, instruction re-execution becomes possible and switching control becomes easy.

In the information processing apparatus according to the invention of claim 11, a specific event that triggers the switching of instruction streams is regarded as a mishit during cache access, and memory access instructions are also stored when the context of the instruction stream is saved. By saving together, instruction re-execution can be realized at high speed and switching control becomes easy.

In the information processing apparatus according to the twelfth aspect of the present invention, by implementing the memory for saving the context on the same processor, it is possible to execute the instruction in parallel with the instruction using the external bus such as high-speed switching or load instruction. .

In the information processing apparatus according to the fourteenth aspect of the present invention, a specific event that triggers the switching of the instruction stream is regarded as a mishit at the time of cache access, and the memory access address is also stored when the context of the instruction stream is saved. By saving together, instruction re-execution can be realized at high speed and switching control becomes easy.

In the information processing apparatus according to the fifteenth aspect of the present invention, the overhead at the time of the memory access error can be reduced by setting the specific event that triggers the switching of the instruction stream as an error related to the memory access.

[0036]

1 is a block diagram of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, 11 and
Reference numeral 21 is an instruction buffer for storing instructions fetched from the memory, 12 and 22 are instruction fetch control units for calculating addresses of fetched instructions and managing addresses (same as PC (program counter) values), 13 And 23
Is an instruction fetch counter (hereinafter abbreviated as FC) that stores the address of the instruction to be fetched, 14 and 24 are instruction decoding units that decode the instructions output from the instruction buffers 11 and 21,
Denoted by 15 and 25 are deciphering program counters (hereinafter abbreviated as deciphering PCs) for storing the addresses of the instructions being deciphered corresponding to the deciphering units 14 and 24. A15 and decryption PC B25 is not only the decoded PC value
Stores the D number.

51, 61, 71 and 81 are operand buffers for temporarily storing instructions from registers, and 52, 62, 72 and 82 are arithmetic units. The functions of these arithmetic units need not be particularly limited. For ease of explanation and considering the general configuration, 52 is a load / store unit that processes memory access instructions, 62 is an integer arithmetic unit that processes integer arithmetic, and 72 is floating point addition / subtraction or integer and floating point. Floating point adder unit to convert between, 82
Is a floating-point multiplication unit that performs floating-point multiplication and division.

53, 63, 73 and 83 are operations or
Is an operation buffer for temporarily storing instructions, 5
4, 64, 74 and 84 are execution systems that control each arithmetic unit.
The control part, 55, 65, 75 and 85 are the addresses of the instructions being executed.
Execution program counter that stores (execution PC) (hereinafter,
This is the execution PC. 55 and run
PC 65 indicates not only the execution PC value but also the instruction stream ID number.
I have paid.

Reference numeral 101 is a selector for selecting an address for instruction fetch from the instruction fetch control units 12 and 22, 102 is an operation switch for connecting an operation resulting from instruction decoding, an immediate value, etc., to an arithmetic unit to be processed, and 103 is A PC switch for connecting the decoded PC value to the corresponding execution PC in conjunction with the operation switch 102, 104 denotes the immediate value output from the instruction decoding units 14 and 24 and the operand output from the register files 107, 108 and 109. Operand switches connected to the operand buffers 51, 61, 71 and 81.

Reference numeral 105 denotes a pipeline control unit for controlling pipeline control such as invalidating a pipeline or re-executing an instruction, and 106 selects a register file 107, 108, or 109 to be executed and registers it. Register designating switch that outputs numbers, register file 10
7, 108 and 109 have integer and floating point registers corresponding to the arithmetic units 52, 62, 72 and 82.

110 is a write switch for connecting the calculation result to the corresponding register, 111 is a context backup memory for storing the contents of the register files 107, 108 and 109 and the execution PC value when the instruction stream is switched, 112 Is a backup switch that connects the register files 107, 108 and 109 and the context backup memory 111 when the data is transferred between them, 113
Is a scoreboard indicating the number of a register in which instructions are being executed and data is not fixed. 114 is a state of the scoreboard and a data dependency check unit for checking whether data dependency occurs from an instruction. 115 is an instruction flow state. 5 is a state management table showing a register file corresponding to an instruction fetch unit corresponding to

For the sake of clarity, mechanisms having the same function (such as an instruction buffer and an instruction decoding unit) will be distinguished by adding an appropriate alphabet to the end of the name as shown in FIG. Those to which the same alphabet is added may be considered to handle the same instruction stream.

The instruction buffers 11 and 21 are respectively A, instruction buffer B, similarly the instruction decoding unit
14 and 24 are also instruction decoding units A, instruction decoding unit B
And The instruction fetch control units 12 and 22 and the decoding PCs 15 and 25 are the same as shown in FIG. Register files 107, 108 and 109 are respectively registered X, register file Y, register file Let Z.

The operation of the information processing apparatus of this embodiment constructed as above will be described below with reference to FIG. First, before describing the operation, preconditions regarding data (including instructions) and configuration will be described. The number of instruction streams (threads) is four, and the instruction stream 1, the instruction stream 2, the instruction stream 3, and the instruction stream 4 are provided for the sake of easy understanding. As shown in FIG. 1, the register file has three sets of X, Y, and Z (10
7, 108, 109). Similarly, the instruction fetch unit
(Instruction buffers 11 and 21 and instruction fetch control units 12 and 22
Etc.), instruction decoding units 14, 24, etc. are two sets. Therefore, there are two instruction streams that can be executed simultaneously. Although the arithmetic units 52, 62, 72, 82 are pipelined, detailed configurations such as the number of pipeline stages are not directly specified because they are not directly related to the present invention. Further, the instruction decoding units 14 and 24 decode one instruction for each instruction stream, so that only one instruction can be issued at a time. It is assumed that the load / store unit 52 is connected to the cache unit and can access data at high speed when hit.

Table 1 shows the initial state of the instruction fetch unit and the register file corresponding to the state of the instruction stream.

[0046]

[Table 1]

This is equivalent to the contents of the state management table 115 in the pipeline control unit 105. The pipeline control unit 105 updates the contents of this state management table 115 and at the same time, based on the contents of the state management table 115. Control instruction flow and pipeline. The initial state will be described with reference to Table 1.

Instruction streams 1 and 2 are currently being executed inside the information processing apparatus, and instruction streams 3 and 4 are in an executable state. Since the instruction streams 1 and 2 are in the execution state, they are allocated to the register files 107, 108, and 109, and the instruction fetch unit fetches the instructions of the instruction streams 1 and 2. Therefore, for instruction stream 1, the instruction fetch unit A (instruction buffer A11 and instruction fetch controller
(Including A12, etc.) A14
(Decryption PC The instruction file is decoded by A15 etc.) and the operation is performed by the operation unit (the operation unit is used depending on the type of the instruction regardless of the instruction flow) X107
To run.

Similarly, for instruction stream 2,
Chi unit B (instruction buffer B21 or instruction fetch system
Part (Including B22, etc.)
B24 (decoding PC B25 etc. are included)
Is an arithmetic unit (for arithmetic units,
Register file
Run using Y108. Command flow 3 and command flow 4
Is an executable state in the initial state.
You can't use files, instruction decoding units, etc. But the register
There is another set of files, so instruction stream 3
Dista file I will assign it to Z109.

Instruction stream 1 or instruction stream 2 in the arithmetic unit
Is being executed and there is no instruction to process, it is in the idle state. In the scoreboard 113, register numbers whose results have not been determined due to execution are managed for each instruction stream. The context backup memory 111 stores register resources of an instruction stream which are not currently stored in the register files 107, 108 and 109.

Next, the operation in the steady state where switching does not occur will be described.

Instruction fetch controller A12 is life of command flow 1
Instruction fetch and instruction buffer It is stored in A11. same
Like the instruction fetch controller B22 is an instruction of instruction stream 2
Instruction buffer It is stored in B21. Instruction
Control unit A12 and B22 supplies commands seamlessly
Since it is the main function to do so, it lives independently of other configurations.
Command buffer A11 and Supply command to B21. order
buffer A11 and If B21 becomes full (full)
Stop. FC A13 and B23
Stores the address of the instruction used when performing a switch. Steady state
In the state, the address is incremented and the fetch destination address is incremented.
Calculate the reply. The fetch destination address is
Selected by the lector 101. Branch if a branch occurs
Operations such as address calculation of the destination instruction and fetch of the destination instruction
Although there is a work, it is omitted because it is not particularly related to the present invention.

Instruction decoding unit A14 and In the description of the stages below from B24, the operation will be described from the instructions of the instruction stream 1 and the instruction stream 2 in order to make the operation easy to understand.

Instruction decoding unit A14 is the instruction buffer A11 to LOAD instruction (memory to register load instruction)
The instruction decoder B24 is the instruction buffer B21 to ADD
Instructions (addition instructions between integer registers) are fetched, respectively decoded to create an operation, and an arithmetic unit to process the operation is determined. At the same time, it is checked whether a data dependency has occurred in the same instruction stream. Dependency check scoreboard 11
3 and the data dependence check unit 114.

Specifically, a register number whose register value is not fixed because it is being executed at present is registered in the scoreboard 113. It is compared with the register number read from the instruction decoding unit. The generation is returned to the instruction decoding unit. This is to prevent an instruction to be executed hereafter from using a register value that does not reflect the result.
Registering the register number is the instruction decoding unit A14 and The instruction is registered when the instruction is issued to the arithmetic unit by B24, and the register number is released by the execution control units 54, 64, 74 and 84 of the arithmetic units when the instruction execution is completed.

Decryption PC A15 and decryption PC B25 is a command solution
Reading department A14 and instruction decoder PC value corresponding to B24
Since it stores it, the instruction decoding unit A14, B24 is command
Iffa A11, When you receive an order from B21,
At the same time the instruction fetch controller A12, Receives PC value from B22
Brush off. Decoding PC as described above A15 decrypted PC value
Besides, the ID of command stream 1 is a decryption PC Command flow 2 for B25
Is stored. Believe about data dependencies
Academic report CPSY-90-54 ('90 .7) "SIMP (single instruction
Flow / multiple instruction pipeline) based super ska
La Processor Improvement Policy ”.

If data dependency has occurred, the dependency relation
The issue of the instruction is stopped until the
If it is not, the instruction decoding unit
To the register file at the same time
Make a request. Instruction stream 1 is a register file Use X107
So the instruction decoding section A14 is a register file X
Sends the register number to 107 and decodes the instruction B24 is a cash register
Star file Send to Y108. At the same time, decryption PC
A15 and decryption PC B25 decryption PC value processed
To the arithmetic unit. Register designation switch 106
Instruction decoding unit based on the state management table 115 A14 and Regis
File X107, instruction decoding unit B24 and register
File Connect Y108. Operation switch 1
02 connects the instruction decoding unit and the arithmetic unit from the decoding result
It Similarly, the PC switch 103 uses the decryption result from the decryption PC.
And connect the execution PC. In the case of this embodiment, the instruction decoding unit
LOAD instruction from A14, instruction decoding unit B24 to AD
D command is issued, so operation switch 10
2 is the instruction decoding unit A14, load store unit 52, instruction
Decoding section B24 and the integer arithmetic unit 62 are connected. For PC
Switch 103 is also connected with the same correspondence (decoding PC A15
Execution PC55, Decoding PC Perform B25 and execution PC65). life
Ryu 1 is a register file Instruction flow 2 using X107
Is a register file Because I use Y108,
Land switch 104 is a register file X107 and road
Store unit 52, register file Y108 and integer
Connect the arithmetic unit 62.

The operation at the input of the load store unit 52
Register file in land buffer 51 Read from X107
The value of the operand that is projected is input to the integer arithmetic unit 62.
Register file in certain operand buffer 61 Y10
Store the operand value read from 8. And command
Decoding section Operation issued by A14
Command decoding unit Operation issued by B24
Decoding PC in operation buffer 63 A15
Decode PC value and execute instruction stream 1 ID PC A55,
Decoding PC Decode B25 PC value and command stream 2 ID
Line PC Store in B65.

Hereinafter, each arithmetic unit operates and
It is executed based on the operand, and the result is registered in each register or memory.
Store in memory etc. In the load store unit 52
Is a memo calculated by executing the LOAD instruction of instruction stream 1.
Fetch data from cache based on readdress,
Register file Store in register in X107. Order
In the arithmetic unit 62, the ADD instruction is executed and
Register file of calculation result Stored in register in Y108
To do. The execution control units 54 and 64 are the load store unit 52 and
Register file X107 and integer calculation unit 62
Dista file Write switch to connect Y108
Control the switch 110.

The execution control units 54 and 64 complete the calculation and register files. X107, After writing to Y108,
The register number registered in the scoreboard 113 is cleared. At the same time, the execution PC is invalidated (necessarily updated if a subsequent instruction comes in). Since the arithmetic unit has a pipeline structure, a plurality of execution PCs are required correspondingly, but the description is omitted because it is not directly related to the present invention.

Further, when the operation issued from the instruction decoding unit uses the same arithmetic unit, the structure of the present embodiment requires a mechanism for making one of the operations wait, but it is not directly related to the present invention. The mechanism is omitted because it is not relevant. If the configuration of the arithmetic unit changes, the waiting mechanism may become unnecessary. Similarly, when two instructions of the same instruction stream are simultaneously processed, it is necessary to wait for writing to the register file or to provide a plurality of register file write ports. Since they are not directly related, the description is omitted.

Subsequently, in the case where the switching of the instruction stream occurs, the state transition diagram of the instruction stream shown in FIG. 2 and FIG.
5 is an explanatory diagram showing the transition of the instruction flow from the execution state to the sleep state, an explanatory diagram showing the transition of the instruction flow shown in FIG. 4 from the sleep state to the execution state, and the instruction flow shown in FIG. 5 from the execution state to the execution state. The operation will be described with reference to the explanatory diagram for transition to and the data layout diagram of the context backup memory shown in FIG.

FIG. 2 is a state transition diagram showing the relationship between the state of the instruction stream and the event causing the state transition. Since the instruction stream 1 is in the executing state (a), the resources of the processor are used to process the instruction. It is assumed that the load store unit 52 executes the load instruction of instruction stream 1 but causes a cache miss. When a cache miss occurs, the cache updates the data from the main memory, and the load / store unit 52 falls into an interlock state. Therefore, the instruction stream 1 is put into the sleep state (a) in order to put another instruction stream into the execution state. The instruction stream 1 may be executed if the cache updates the data from the main memory. Executable state (c)
Transition to. Since the instruction stream 1 is in the executable state, if the hardware resources for execution can be secured, it can transit to the execution state (A).

The case where the switching of the instruction stream occurs will be described along with the state transition of the instruction stream as outlined below.

(1) Since instruction stream 1 and instruction stream 2 are in the execution state, processor resources are used (instruction stream 1 is a register file X107, instruction stream 2 is a register file
Y108) Processing the instruction. (Initial state, instruction stream 1 and instruction stream 2: execution state) (2) The load / store unit 52 executes the load instruction of instruction stream 1, but a cache miss occurs.

(3) The context of the instruction stream 1 is saved in the context backup memory 111, and the instruction stream 1 is put into the sleep state. (Instruction flow 1: execution state → sleep state) (4) Set the FC value etc. to execute the instruction flow 3 in which the context is prepared in the register file in the executable state.

(5) The instruction stream 3 is activated. (Instruction flow 3: Executable state → Execution state) (6) Since instruction flow 4 is in the executable state, the context backup memory 111 stores the context in the register file. Store in X107.

(7) The cache updates the missed data. (Instruction flow 1: dormant state → executable state) A detailed operation will be described along the above (1) to (7).

(1-1) Until the LOAD instruction of the instruction stream 1 makes a cache access in the load / store unit 52, the description is the same as the above description of the steady state. The initial state of the instruction stream is shown in Table 1 above. A state of a series of operations is shown in FIG.

(2-1) As a result of cache access, a cache miss occurs. The cache miss information is sent to the pipeline control unit 105.

(2-2) The pipeline control unit 105 requests the execution control unit 54 of the load / store unit 52 to investigate the instruction flow causing the cache miss. The execution control unit 54 has an instruction stream 1
Is transmitted to the pipeline control unit 105.

(2-3) The pipeline control unit 105 refers to the state management table 115, and the instruction of the instruction stream 1 causes a cache mishit. A14,
Instruction buffer A11, instruction fetch controller A12, decryption PC The processing of the part upstream of the instruction decoding part such as A15 is stopped and the issuing of the instruction is prohibited.

(2-4) The pipeline control unit 105 controls the execution control unit 54 to normally terminate the load / store unit 52. However, the process ends without writing anything to the actual write register.

(2-5) The pipeline control unit 105 investigates the processing status of the instruction of the instruction stream 1 via the execution control units 64, 74 and 84, and if there is one that is already being processed by the arithmetic unit. If it stops until the end.

(3-1) If there is no instruction in the instruction stream 1 that is already being processed by the arithmetic unit, the pipeline control section 105
The context of instruction stream 1 is saved in the context backup memory 111. In the case of this embodiment, the context is a register file X107, decryption PC A15 (including ID of instruction flow), Execution PC of load / store unit 52
A55 (LOAD instruction PC), load / store unit 52
The operation buffer 53 (operation of LOAD instruction) and the memory access address. Normal,
The memory access address is calculated using the contents of the operand buffer 51. Context backup
FIG. 6 shows a context in which the execution of the instruction stream stored in the memory 111 is stopped and saved. In the case of executing the instruction stream, the context includes a head PC and the head PC is
Execute from C.

(3-2) Pipeline control unit 105 executes instruction stream 1
The scoreboard 113 and the like are also invalidated so that there is nothing significant regarding.

(3-3) The pipeline controller 105 causes the state of the instruction stream 1 in the state management table 115 to transit from execution to sleep. This is shown in Table 2.

[0078]

[Table 2]

(4-1) The pipeline control unit 105 executes the execution PC of the LOAD instruction that causes the instruction stream 3 from the context backup memory 111 to the dormant state, and the execution PC of the operation and memory access address. A55, operation buffer 53, and load / store unit 52 are restored. A series of operations relating to the instruction stream 3 is shown in FIG.

(4-2) The pipeline control unit 105 sends the decoding PC of the instruction stream 3 from the context backup memory 111 to FC. Set to A13. Decoding PC The command stream 3 ID is set in A15.

(5-1) The pipeline control section 105 shifts the instruction fetch unit ( A) and instruction decoder A14 has a free space, instruction stream 3 is ready for execution, and the register file has already been created. Z109
The state of the instruction stream 3 in the state management table 115 is changed from the executable state to the executable state because the state is assigned to the.
It is shown in Table 3. FIG. 5 shows a series of operations related to the instruction stream 3.
Shown in.

[0082]

[Table 3]

(5-3) The pipeline control unit 105 instructs the execution control unit 54 of the load / store unit 52 to execute the operation set in the operation buffer 53 and the memory access address set in the load / store unit 52. To re-execute the LOAD instruction of instruction stream 3.

(5-4) Since the pipeline control unit 105 executes the instruction stream 3, the instruction fetch control unit 105 FC against A12 The execution of the instruction is started from A13.

(5-5) Instruction fetch control section A12 is FC
Instruction fetch starts from the address of A13
Command buffer The instruction is stored in A11. Instruction decoder A14
Is the instruction buffer Decode the instruction stored in A11. Since
The instructions are processed as described in the descending and steady state.

(6-1) The pipeline control unit 105 changes the register file when the instruction stream 1 transits to the sleep state. Since the X107 has a vacancy and the instruction stream 4 is in the executable state, the context of the instruction stream 4 is set in the register file. X10
Assign to 7. Context backup memory 1
Register file from 11 Transfer the data to X107.
It is shown in Table 4.

[0087]

[Table 4]

(6-2) The pipeline control unit 105 uses the register file for the instruction stream 4. The state management table 115 is updated as if X107 was allocated.

(7-1) The cache updates the data of the mishit which caused the instruction stream 1 to transit to the sleep state.

(7-2) The pipeline control unit 105 changes the state of the instruction stream 1 from the sleep state to the executable state because it is updated in the cache, and the state management table 115
To update. It is shown in Table 5.

[0091]

[Table 5]

The series of state transitions and the internal operation have been described above, but an example of the state transitions thereafter is shown below.

Instruction flow 2: Execution state → Hibernation state Instruction flow 4: Executable state → Execution state Instruction flow 1: Context backup memory 111 register file Allocate Y108 Instruction stream 3: execution state → sleep state (instruction stream 2: sleep state → executable state) instruction stream 1: executable → execution state As described above, according to this embodiment, (1) By putting the instruction stream that generated the lock into a dormant state (saving) and allocating the hardware mechanism to another instruction stream, that is, by switching the instruction stream and executing it, the pipeline interlock and lock time are reduced, and the functional unit It can improve the usage efficiency and realize high performance.

(2) The instruction stream in which the interlock is generated is put in the sleep state, the context is saved in the memory, the context of the new instruction stream is restored, and the hardware mechanism is allocated, that is, the instruction stream is switched and executed. This reduces the pipeline interlock and lock time, improves the usage efficiency of the functional units, and realizes high performance.

(3) By providing more register files than the instruction preparation section, even if an interlock occurs,
Since a new instruction stream can be executed without saving the context of the instruction stream that has generated the interlock in the memory, high-speed instruction stream switching can be performed.

(4) When an interlock occurs by providing more register files and a memory for saving the context than in the instruction preparation section, the context of the instruction stream in which the interlock occurs is saved in the memory, Since the context of such an instruction stream can be prepared in the register in advance, a normal instruction and an instruction stream can be overlapped and executed, so that a high-speed instruction stream switching can be performed.

(5) By implementing the memory for saving the context on the same processor, it is possible to execute in parallel with an instruction using the external bus, such as a high-speed switching or a load instruction.

(6) The overhead at the time of memory access can be reduced by making the specific event that triggers the switching of the instruction stream a miss hit at the time of cache access.

(7) When a specific event occurs or a specific state is detected, the execution of the instruction preparation section assigned to the instruction stream of the instruction causing the stop is stopped, and the instruction preparation section is stopped. Pipeline control is facilitated by initializing the internal state of the.

(8) It is easy to control the switching of instruction streams by including the leading PC in the context for stopping and saving the instruction stream, and restarting the instruction stream when the instruction stream is executed again. become.

(9) Control of instruction switching is facilitated by setting a specific event that triggers instruction flow switching as a mishit during cache access, and when a cache miss occurs, aborts the memory access instruction and terminates normally. become.

(10) When a new instruction stream is assigned to the instruction preparation section and the instruction execution is restarted, the instruction to switch the instruction stream can be easily controlled by re-executing the memory access instruction that caused the switching and was aborted. become.

(11) A specific event that triggers the switching of instruction streams is regarded as a mishit at the time of cache access,
When the context of the instruction stream is saved, the PC of the memory access instruction is also saved together, so that instruction re-execution becomes possible and switching control becomes easy.

(12) A specific event that triggers the switching of instruction streams is regarded as a mishit at the time of cache access,
When the context of the instruction stream is saved, the memory access instruction is also saved, so that instruction re-execution can be realized at high speed and switching control can be facilitated.

(13) A specific event that triggers the switching of instruction streams is regarded as a mishit at the time of cache access,
When the context of the instruction stream is saved, the memory access address is also saved, so that instruction re-execution can be realized at high speed and switching control becomes easy.

(14) The overhead at the time of memory access can be reduced by setting a specific event that triggers the switching of instruction streams as an error related to memory access.

In this embodiment, the number of register file sets is 3, the number of instruction buffers and instruction decoding units is 2, and the operation executing units are 4 types. Since it has nothing to do with the gist, there is no restriction on the configuration or the number.

In this embodiment, the PC value and operation of the load instruction for the load instruction to be re-executed are saved in the context backup memory. However, for example, only the PC value is saved and re-executed from the instruction fetch. A method or a method of saving an instruction and re-execution from decoding may be used. In addition, the fact that both the PC value and the operation are saved is in consideration of the occurrence of an exception, and does not limit the present invention.

In the present embodiment, a load instruction is used as an example of using the load / store unit for convenience of explanation, but a similar function can be realized for a store instruction.

In this embodiment, the load instruction is re-executed after the information management table is updated, but the order may be reversed. Regarding the order of procedures other than this, only one example is given in this embodiment.

In this embodiment, branch processing is not described because it is not particularly related to the present invention.

In this embodiment, the load instruction is used as the trigger for switching, but it is also applicable to instructions and events that generate interlocks.

In this embodiment, after the instruction flow switching is decided,
It is saved in the memory until a new instruction stream is set. However, if there is a sufficient number of register file sets, context backup may be performed by switching the new instruction stream and then performing overlap execution.

In this embodiment, the memory is provided on the processor and the context such as the register file of the instruction stream that enters the sleep state is saved in the memory, but it may be saved in the external memory.

In the present embodiment, a memory is provided on the processor and the context of the register file of the instruction stream that enters the sleep state is saved in the memory. However, no on-chip memory is provided and the instruction stream allocated to the register file is used. It is also possible to use the external memory when switching or switching the context of the register file.

[0116]

As described above, the information processing apparatus of the present invention can: (1) reduce pipeline interlock and lock time, improve the usage efficiency of functional units, and realize high performance.

(2) Since the switching between the normal instruction and the instruction stream can be executed in an overlapping manner, the instruction stream can be switched at high speed.

(3) It can be executed in parallel with an instruction such as a load instruction that uses an external bus.

(4) The overhead at memory access can be reduced.

(5) Pipeline control and instruction flow switching control are facilitated.

Many things such as the above can be realized, and their practical effects are great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a state transition diagram showing the relationship between the state of the instruction stream in FIG. 1 and the event causing the state transition.

FIG. 3 is an explanatory diagram showing a transition of the instruction flow in FIG. 1 from an execution state to a sleep state.

FIG. 4 is an explanatory diagram showing a transition of the instruction flow in FIG. 1 from a sleep state to an executable state.

5 is an explanatory diagram showing a transition of the instruction flow in FIG. 1 from an executable state to an execution state.

6 is a data layout diagram of the context backup memory in FIG. 1. FIG.

FIG. 7 is a block diagram of a conventional information processing apparatus.

[Explanation of symbols]

11, 21 ... Instruction buffer, 12, 22 ... Instruction fetch control unit, 13, 23 ... Fetch counter (FC), 14, 24 ... Instruction decoding unit, 15, 25 ... Decoding program counter (Decoding P
C), 51, 61, 71, 81 ... Operand buffer, 52 ...
Load store unit, 62 ... Integer calculation unit, 72
… Floating point addition unit, 82… Floating point multiplication unit, 53, 63, 73, 83… Operation buffer,
54, 64, 74, 84 ... Execution control unit, 55, 65, 75, 85 ... Execution program counter (execution PC), 101 ... Selector, 10
2, 103, 104, 106, 110, 112 ... Switch, 105 ... Pipeline control unit, 107, 108, 109 ... Register file, 111 ... Context backup memory, 1
13 ... Scoreboard, 114 ... Data dependency check unit, 115
… State management table.

Claims (15)

[Claims] 1. A plurality of instruction preparation units, a plurality of operation execution units, a plurality of register files, and an instruction scheduling unit provided between the instruction preparation units and the operation execution units, wherein the instruction preparation unit comprises: Instruction fetch means for reading instructions,
From dependency analysis means for analyzing and storing the data dependence information from the operation execution part, and instruction decoding means for decoding the instruction read by the instruction fetch means and judging the issuability of the instruction based on the data dependence information. The instruction scheduling unit accepts instruction decoding results from a plurality of instruction preparation units and selects an instruction decoding result that can be issued for the operation executing units in the instruction accepting state among the plurality of operation executing units. , A means for outputting each instruction among them to a corresponding operation executing portion, wherein the operation executing portion executes the instruction received from the instruction scheduling portion, and decodes the dependency elimination information at the end of execution of the instruction. Sometimes it includes a means for notifying the dependency analysis means of the instruction preparation section that has performed dependency analysis, and when a specific event occurs or a specific state is detected. Information that is characterized by stopping the execution of the instruction stream that caused the instruction, saving the context of the stopped instruction stream in memory, storing the context of the new instruction stream from memory, and starting execution. Processing equipment. 2. A plurality of instruction preparation units, a plurality of operation execution units, a plurality of register files, an instruction schedule unit provided between the instruction preparation units and the operation execution units, and a plurality of instruction stream executions. An instruction stream execution control unit for controlling and a memory for storing a context of the instruction stream are provided, and the instruction preparation unit, an instruction fetch unit for reading an instruction, and a dependency analysis for analyzing and storing data dependency information from the operation executing unit. Means and instruction decoding means for decoding the instruction read by the instruction fetch means to determine the issue possibility of the instruction based on the data dependence information, and the instruction schedule section includes instructions from a plurality of instruction preparation sections. In addition to accepting the decoding result, select the instruction decoding result that can be issued to the operation executing unit that is in the instruction accepting state from the plurality of operation executing units, and select each instruction among them. Means for outputting a command to a corresponding operation executing unit, the operation executing unit executing the instruction received from the instruction scheduling unit, and performing dependency analysis when the instruction is decoded, the dependency resolution information when the instruction is completed. The instruction flow execution control unit includes a unit for notifying the dependency analysis unit of the instruction preparation unit, and when a specific event occurs or a specific state is detected, the instruction of the instruction that is the factor An information processing apparatus, which stops execution of a flow of instructions, saves a context of the stopped instruction flow in a memory, stores a context of a new instruction flow from the memory, and starts execution. 3. A plurality of instruction preparation units, a plurality of operation execution units, a plurality of register files at least larger than the instruction preparation units, and an instruction scheduling unit provided between the instruction preparation units and the operation execution units. And an instruction stream execution control unit for controlling execution of a plurality of instruction streams, wherein the instruction preparation unit is
Instruction fetch means for reading instructions, and dependency analysis means for analyzing and storing data dependency information from the operation executing unit,
The instruction fetch unit includes an instruction decoding unit for decoding the instruction read by the instruction fetch unit and determining the instruction issuance possibility based on the data dependency information, and the instruction scheduling unit outputs the instruction decoding results from a plurality of instruction preparation units. Along with accepting
The operation executing unit including means for selecting an instruction decoding result that can be issued to an operation executing unit in an instruction accepting state among a plurality of operation executing units and outputting each instruction among them to a corresponding operation executing unit; The execution unit includes means for executing the instruction received from the instruction scheduling unit, and means for notifying the dependency resolution information at the end of execution to the dependency analysis means of the instruction preparation unit that has performed the dependency analysis at the time of decoding the instruction. The instruction stream execution control unit associates the instruction stream with the instruction preparation unit and the register file, and executes the instruction stream allocated to the instruction preparation unit, but does not generate a specific event or a specific state. When it is detected, the execution of the instruction stream of the instruction that caused it is stopped, and the instruction preparation section assigned to the instruction stream is dealt with to the instruction stream not assigned yet. Is allowed, the information processing apparatus characterized by initiating the execution of the newly allocated instruction stream. 4. A plurality of instruction preparation units, a plurality of operation execution units, a plurality of register files at least larger than the instruction preparation units, and an instruction scheduling unit provided between the instruction preparation units and the operation execution units. An instruction stream execution control unit for controlling execution of a plurality of instruction streams; and a memory for storing a context of the instruction stream. The instruction preparation unit includes an instruction fetch unit for reading instructions and data from the operation execution unit. The instruction scheduling unit includes a dependency analysis unit that analyzes and stores dependency information, and an instruction decoding unit that decodes the instruction read by the instruction fetch unit and determines the issue possibility of the instruction based on the data dependency information. , A command that can receive the instruction decoding results from a plurality of instruction preparation units and can be issued to an operation execution unit that is in an instruction acceptable state among a plurality of operation execution units. The instruction execution unit includes means for selecting an instruction decoding result and outputting each instruction among them to a corresponding operation executing unit, wherein the operation executing unit executes the instruction accepted from the instruction scheduling unit, and eliminates dependence upon execution. Means for notifying information to the dependency analyzing means of the instruction preparing section which has carried out dependency analysis at the time of decoding the instruction, and the instruction stream execution control section associates the instruction stream with the instruction preparing section and the register file, The instruction stream allocated to the preparation section is executed, but when a specific event occurs or a specific state is detected, execution of the instruction stream of the instruction that caused it is stopped, and The context of the instruction stream is saved in the memory, the instruction preparation section assigned to the instruction stream has not been allocated to the instruction preparation section, and it is allocated to the register file. In correspondence with the instruction stream that have information processing apparatus characterized by initiating the execution of the newly allocated instruction stream. 5. The information processing apparatus according to claim 1, wherein the specific event that triggers the switching of the instruction stream is a mishit at the time of cache access. 6. When a specific event occurs or a specific state is detected, the execution of the instruction preparation unit assigned to the instruction stream of the instruction causing the event is stopped, and the instruction preparation unit is stopped. The information processing apparatus according to claim 1, wherein an internal state of the information processing device is initialized. 7. The head PC is included in the context for stopping and saving the execution of the instruction stream, and when the instruction stream is executed again, the execution is restarted from the head PC. An information processing apparatus according to claim 2. 8. A memory access instruction is aborted and terminated normally when a cache hit occurs as a specific event that triggers the switching of instruction streams and when a cache miss occurs.
The information processing device according to any one of 1. 9. A new instruction stream is allocated to the instruction preparation section,
5. The information processing apparatus according to claim 1, wherein when the instruction execution is restarted, the memory access instruction that has caused the switching and was aborted is re-executed. 10. A specific event that triggers the switching of instruction streams is a mishit at the time of cache access, and when the context of the instruction stream is saved, the PC of the memory access instruction is also saved. Claim 1
5. The information processing apparatus according to any one of 4 to 4. 11. A specific event that triggers the switching of the instruction stream is a mishit at the time of cache access, and when the context of the instruction stream is saved, the memory access instruction is also saved. The information processing apparatus according to any one of 1 to 4. 12. The memory for saving the context is provided on the same processor.
The information processing device described. 13. The instruction stream execution control unit, when the context is saved in a memory, has a specific state resolved, and if there is a register file not allocated to the instruction stream, the context is stored in the register file. The information processing apparatus according to claim 4, wherein the restored instruction stream is assigned to the register file. 14. A specific event that triggers the switching of instruction streams is a mishit at the time of cache access, and when the context of the instruction stream is saved, the memory access address is also saved. The information processing apparatus according to any one of 1 to 4. 15. The information processing apparatus according to claim 1, wherein a specific event that triggers the switching of the instruction stream is an error related to memory access.