JPH0643782Y2 - A motor drive device having a film idling function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a motor drive device having a film idling function, and more particularly to a motor drive device for automatically idling a predetermined number of frames.

Among motor drive devices that automatically perform shutter release of a camera and film winding, it is already known that the film is also automatically fed.

However, in the conventional motor drive device having the film idling function, when the set film frame number is reset, it is automatically reset on the assumption that the reset is performed when the film is loaded into the camera. I started feeding by air. However, the number of set film frames is not always the number of frames that can be shot in the loaded film, and if the number of set film frames is different from the number of frames that can be shot, simply pressing the reset button will empty the film wastefully. There was a problem that it was sent. In particular, in a motor drive device that automatically stops film winding when the number of film frames has reached the set number of film frames, shooting cannot be continued unless reset, so the above-mentioned problems occur. It was remarkable.

In view of the above points, an object of the present invention is to provide a second counting means for counting the number of idle feed frames of the film, in addition to the first counting means for counting the number of photographed frames, and to operate the reset means. Another object of the present invention is to provide a motor drive device having a film idling function, in which only the first counting means is reset.

According to the present invention, when the reset means is operated, the first
Since only the number of photographed frames of the counting means is reset and the number of idle feed frames of the second counting means is not reset, it is necessary to prevent the film from being idle-fed based on the output from the second counting means. You can Therefore, in the motor drive device in which the film winding is automatically stopped when the number of photographed frames reaches the set number of film frames,
Set a film frame number smaller than the number of frames that can be shot (for example, 5 frames in a 36-frame film), shoot 5 frames continuously, stop automatically, reset, and shoot 5 frames again. You will be able to shoot.

Hereinafter, the present invention will be described based on an embodiment shown in the drawings.

1 (A) and 1 (B) show an electric circuit of a motor drive device having a film idling function, showing an embodiment of the present invention. This motor drive device is provided with a release switch S ₁ for starting the shutter release of the camera, and this release switch S ₁ is made of a normally open switch and is provided in the motor drive device. When a release button (not shown) is pressed, the switch S ₁ is closed only while the release button is pressed. One end of this switch S ₁ is grounded, and the other end is connected to a power supply (see FIG. 6) which takes a potential −V _EE2 via a diode D ₁ and a resistor R ₄ in series. The other end of the switch S ₁ is connected to a connection contact J ₅ that connects the motor drive device and the power supply device. Above diode D ₁ and resistor R ₄
Is connected to the input terminal of the inverter N4, the output terminal of the inverter N4 is connected to the other input terminal of the NAND gate A7, and is also connected to the other input terminal of the NAND gate A3. ing. One input terminal of the NAND gate A3 is connected to the output terminal of the NAND gate A6, and the output terminal of the NAND gate A3 is connected to the input terminal of the inverter N5, the other input terminal of the NAND gate A5 and the NAND gate.
It is connected to the other input terminal of A6.

The output terminal of the inverter N5 is connected to each reset signal input terminal of a plurality of flip-flop circuits which are cascaded to form a binary counter BC1. The binary counter BC1 after closing the release switch S _1, until the release signal camera is crocodile transmitted, i.e.,
The drive motor M1 starts to rotate, and the motor drive device counts a predetermined time (for example, 60 ms) to hold the shutter release signal in the camera until the camera release mechanism is operated by the mechanical coupling mechanism. The pulse signal of frequency f ₃ is input from the frequency dividing circuit 60 to the input terminal of the first-stage flip-flop circuit. The output terminal of the final stage flip-flop circuit of the binary counter BC1 is connected to the NAND gate via the inverter N6.
It is connected to one input terminal of A4. The output terminal of the NAND gate A4 is connected to one input terminal of the NAND gate A5,
The output terminal of the NAND gate A5 is connected to the other input terminal of the NAND gate A4, and both the NAND gates A4 and A5 form an RS flip-flop circuit. The output terminal of the NAND gate A5 is connected to one input terminal of the NAND gate A6, and the output terminal of the NAND gate A6 is a 3-input NAND gate A8.
, A second input terminal of the 3-input NAND gate A11, one input terminal of the NAND gate A7, one input terminal of the NAND gate A3, the other input terminal of the NAND gate A25, the other input terminal of the NAND gate A29, and Each of them is connected to one input terminal of the NAND gate A31.

The inverter N4 to N6, a NAND gate A3~A6 and binary counter BC1, depending on the closure of the release switch S _1,
A shutter release signal holding circuit that outputs an "L" level signal for a predetermined time regardless of the closing time is formed. The shutter release signal holding circuit and the NAND gate A7 form a release switch. Depending on the closing of S ₁ , when the closing time is shorter than the above specified time, an "H" level signal is output for a predetermined time, and when the closing time is longer than the above specified time, the closing time A circuit that outputs an "H" level signal is formed during this period. That is, as shown in FIG. 2 (a), when the closing time of the release switch S ₁ is shorter than the predetermined time, the inverter
The outputs of N4 to N6, NAND gates A3 to A5 and binary counter BC1 change as shown in FIGS. 2 (b) to (h), and the outputs of NAND gates A6 and A7 are shown in FIGS. 2 (i) and (i). The output as shown in j) is obtained. Further, as shown in FIG. 3 (a), when the closing time of the release switch S ₁ is longer than the predetermined time, the inverter N4 to N6, a NAND gate A3~A5 and output of the binary counter BC1 third
Change as shown in Figures (b) to (h), and the NAND gate A6
Outputs shown in FIGS. 3 (i) and 3 (j) are obtained at the output terminals of A7 and A7.

The output terminal of the NAND gate A7 is connected to the input terminal of the inverter N7 and also connected to the second input terminal of the 3-input NAND gate A1. The first input end of the NAND gate A1 is connected to the down terminal dw of the camera switch S ₂ provided on the armature of the camera through the inverter N1 and a connection contact (not shown). This camera switch S
₂ , the movable contact piece is formed by a changeover switch that switches between the up terminal up and the down terminal dw according to the up and down movement of the movable reflecting mirror of the camera, and the up terminal up is connected via a connection contact not shown. The motor drive device is grounded at the trap. Also, between the up terminal up and down terminal dw,
A motor drive device is connected to a resistor R ₁ arranged on the arm via a connection contact (not shown). Further, the movable contact piece terminal of the camera switch S _2, as well are connected to a power supply to take potential -V _EE2 through the resistor _{R 2 (R 2 «R 1)} , is connected to the input terminal of the inverter N2. The output terminal of the inverter N2 is connected to the third input terminal of the NAND gate A1 and also connected to one input terminal of the NAND gate A2. The other input end of the NAND gate A2 is connected to the output end of the inverter N1. The output terminal of the NAND gate A1, the resistance R ₃ is connected to the base of the PNP transistors T ₁ through the emitter of the transistors T ₁ to the base of the PNP transistor T _2, the collector is connected to the collector of the transistor T ₂ The collector is connected to the connection contact J ₄ which connects the motor drive unit and the power supply unit. The output terminal of the NAND gate A2 is connected to the first input terminal of the 5-input NAND gate A15 and the 5th input terminal through the inverter N3.
Each is connected to the first input terminal of the input NAND gate A16.

The output terminal of the inverter N2 is also connected to the input terminal of the inverter N12 and the other input terminal of the NAND gate A19, respectively. The output terminal of the inverter N12 is connected to each reset signal input terminal of the four flip-flop circuits which are cascaded to form a binary counter BC2. It is connected to the input terminal of the first-stage flip-flop circuit of the binary counter BC2 and the output terminal of the inverter N11.
The input terminal of the inverter N11 is connected to an oscillation circuit composed of inverters N8, N9, a capacitor C ₁ and a resistor R ₅ . The oscillator circuit, the output terminal of the inverter N8 is connected to the input end of the one end and the inverter N9 resistor R ₅ through a capacitor C _1, the other end and output end input terminal of the inverter N8 inverter N9 resistor R ₅ The output terminal of the inverter N8 is the output terminal of the oscillation circuit. The output terminal of the inverter N11 is also connected to the input terminal of the frequency _dividing circuit 60, and the output terminal of the frequency _dividing circuit 60 divides the frequency of the output of the oscillation circuit into frequencies f _{1 to} f _n (n is Any positive integer)
The pulse signal of is obtained. These pulse signals (f _{1 to} f _n ) are used as input pulse signals for various circuits in the motor drive device. The output terminal of the final stage flip-flop circuit of the binary counter BC2 is
It is connected to one input terminal of a NAND gate A18 via an inverter N16. The output terminal of the NAND gate A18 is connected to one input terminal of the NAND gate A19, and
The output terminal of 19 is connected to the other input terminal of the NAND gate A18, and both NAND gates A18 and A19 form an RS flip-flop circuit. The output terminal of the NAND gate A18 is also connected to the first input terminal of the 3-input NAND gate A11, and the output terminal of the NAND gate A19 is connected to the inverter N18.
One end of NAND gate A25 via, binary counter B
It is connected to the input terminal of the flip-flop circuit at the first stage of C3 and one input terminal of the NAND gate A49 (see FIG. 1B).

The output terminal of the NAND gate A25 is connected to the clock signal input terminal CK of the D latch circuit DF1 (see FIG. 1 (B)). Further, the binary counter BC3 is formed by connecting two flip-flop circuits in cascade, and serves to count the number of idle feed frames when the film is idle fed. Reset signal input terminal of the flip-flop circuit of the binary counter BC3 is connected to the other end cap switch S ₃ after the camera is crocodile disposed via a connection contact (not shown). The rear cover switch S ₃ is for detecting the opening / closing of the rear cover of the camera, and is closed when the rear cover is opened. One end of the rear cover switch S ₃ is grounded to the motor drive device through a connection contact (not shown), and the other end is connected to a power supply having a potential -V _EE2 through a connection contact (not shown) and a resistor R ₉ . .
The other end of the rear cover switch S ₃ are connected via the inverter N22 to the other input terminal and the 3 second input terminal of the input NAND gate A28 of the NAND gate A27.

The output terminal of the first-stage flip-flop circuit forming the binary counter BC3 has a decoder 30 through an inverter N19.
It is also connected to the input terminal (see Fig. 1 (B)).
The output terminal of the subsequent flip-flop circuit forming the binary counter BC3 is connected to the second input terminal of the 3-input NAND gate A26 and the input terminal of the decoder 30 via the inverter N21. The first input terminal of the NAND gate A26 is connected to the output terminal of the inverter N54 (see FIG. 1 (B)). The output end of the NAND gate A26 is connected to one input end of the NAND gate A27, the other input end of the NAND gate A32, the other input end of the NAND gate A33 and one input end of the NAND gate A58 (see FIG. 1B). The output terminal of the NAND gate A27 is connected to the other input terminal of the NAND gate A26 and the first input terminal of the NAND gate A28. The output terminal of the NAND gate A28 is connected to one input terminal of the NAND gate A29, and the output terminal of the NAND gate A29 is connected to the third input terminal of the NAND gate A28. The output terminal of the NAND gate A28 is connected to the other input terminal of the NAND gate A9 and the NAND gate A9.
It is also connected to the third input terminal of A8.

The output terminal of the NAND gate A31 is connected to one input terminal of the NAND gate A32, the output terminal of the NAND gate A32 is connected to the other input terminal of the NAND gate A31, and both the NAND gates A31 and A32 form an RS flip-flop circuit. is doing. The output terminal of the NAND gate A32 is connected to one input terminal of the NAND gate A33, and the output terminal of the NAND gate A33 is connected to the fifth input terminal of the NAND gate A15.

A second input terminal of the NAND gate A8 is the change-over switch of the continuous shooting and one-frame shooting (hereinafter, referred to as continuous single change-over switch the switch) is connected to one frame shooting terminal b of S _7.
The movable contact terminal of this continuous single changeover switch S ₇ is grounded, and the continuous shooting terminal a is a free terminal. In addition, the single-piece shooting terminal b of the continuous single changeover switch S _{7 and} the electric potential through the resistor R ₆ .
-V _EE2 is connected to the power supply and diode D
₂ is connected in the reverse direction to a connection contact J ₁ that connects the motor drive device and the power supply device. The output terminal of the NAND gate A8 is connected to the third input terminal of the NAND gate A15. The output terminal of the inverter N7 is
It is connected to one input terminal of the NAND gate A9, and the output terminal of the NAND gate A9 is connected to the second input terminal of the NAND gate A15. Further, the output terminal of the NAND gate A11 is connected to one input terminal of the NAND gate A12, and the output terminal of the NAND gate A12 is connected to the third input terminal of the NAND gate A11. The other input end of the NAND gate A12 is connected to the output end of the NAND gate A14, and the output end of the NAND gate A11 is the second end of the NAND gate A16.
Is connected to the input end of.

On the other hand, the motor drive device is provided with a motor switch S ₆ that switches according to shutter release and film winding. The movable contact terminal of the motor switch S ₆ is grounded, and the hoisting terminal a has a potential -V through the resistor R _7.
EE2 is connected to the power supply and the inverter N14
And is connected to the other input end of the NAND gate A14. Further, the release terminal b of the motor switch S ₆ is connected to a power source that takes a potential −V _EE2 through the resistor R ₈ and is also connected to one input end of the NAND gate A13 through the inverter N13. The output terminal of the NAND gate A13 is connected to one input terminal of the NAND gate A14, the output terminal of the NAND gate A14 is connected to the other input terminal of the NAND gate A13, and both NAND gates A13 and A14 form an RS flip-flop circuit. There is. The output terminal of the NAND gate A14 is connected to the third input terminal of the NAND gate A16, and the fourth terminal of the NAND gate A15 is connected via the inverter N15.
It is also connected to the input end of. Also, Nand Gate A16
The fourth input terminal of is connected to the output terminal of the NAND gate A53 (FIG. 1 (B) refer), the fifth input terminal of the NAND gate A16, connection contacts J ₁₂ (FIG. 1 (B) see )It is connected to the.

The output terminals of the NAND gates A15 and A16 are connected to one and the other input terminals of the NAND gate A17, respectively. Are connected to the reset signal input terminal and the input terminal of the inverter N34, respectively. The output terminal of the inverter N32 is connected to the base of the PNP transistor T ₃ via a resistor R _15, the emitter of the transistor T ₃ is grounded, NPN type transistor T ₄ the collector through a resistor R ₁₆
Connected to the base of. The collector of the transistor T ₄ is connected to the base of the PNP type transistor T ₅ through the resistor R ₁₇ , and the emitter of the transistor T ₄ is connected to the base of the NPN type transistor T ₆ . Above transistor T ₅
The emitter is grounded, and the collector is connected to the collectors of the one and the NPN type transistor T ₉ of the driving motor M1. The collector of the transistor T ₆ is
It is connected to the other end of the drive motor M1 and its emitter is connected to a connection contact J ₆ which connects the motor drive device and the power supply device. A diode D ₃ is inserted between the emitter and collector of the transistor T ₆ . The emitter of the transistor T ₉ is connected to the connection contact J ₆ , and the base is a resistor.
It is connected to the collector of the PNP transistor T ₁₁ through R ₂₀ . The emitter of the transistor T ₁₁ is grounded, and the base is connected to the output terminal of the NAND gate A 46 through the resistor R ₂₁ . The above transistors T _{3 to} T ₆ , T ₉ ,
T _11, the diode D ₃ and resistor _{R 15 ~R 17, R 20,} R 21 are,
The drive circuit 12 (see FIG. 6) of the motor M1 is formed.

The binary counter BC6 is formed by connecting a plurality of flip-flop circuits in cascade, and serves to count a fixed time for braking the drive motor M1. This 2
The pulse signal of frequency f ₄ is input from the frequency dividing circuit 60 to the input terminal of the first-stage flip-flop circuit of the binary counter BC6, and the output terminal of the last-stage flip-flop circuit is
It is connected to one input terminal of a NAND gate A44 via an inverter N33. The output terminal of the NAND gate A44 is connected to one input terminal of the NAND gate A45,
Is connected to the other input terminal of the NAND gate A44, and both NAND gates A44 and A45 form an RS flip-flop circuit. The other input terminal of the NAND gate A45 is connected to the output terminal of the inverter N34, and the output terminal is connected to one input terminal of the NAND gate A46.
The other input terminal of 46 is connected to the output terminal of the inverter N34. The binary counter BC6, the inverters N33, N34 and the NAND gates A44 to A46 form a brake circuit for braking the drive motor M1 for a certain period of time. That is, when the output of the NAND gate A17 is inverted to the “L” level, the output of the inverter N32 becomes the “H” level and the transistor T ₃
Since each of ~ T ₆ is turned off, the power supply to the motor M1 is cut off and at the same time, the binary counter BC6 is reset so that the output of the counter BC6 becomes "L" level and the NAND gate A44
One input terminal is "H" level, the other input terminal of the NAND gate A45 becomes "H" level, the output of NAND gate A46 changes to "L" level, the transistors T _11, T ₉ is turned on, By short-circuiting both ends of the motor M1, the motor M1
Is braked. Then, when the output of the binary counter BC6 is inverted to "H" level after a certain period of time, one input end of the NAND gate A44 becomes "L" level and one input end of the NAND gate A46 becomes "L" level. since the output of the NAND gate A46 is inverted to "H" level, the transistors T _11, T ₉ is turned off, the braking of the motor M1 is released.

1B, the other input end of the NAND gate A49 is connected to the output end of the NAND gate A56, and the output end is connected to one input end of the NAND gate A51. The other input end of the NAND gate A51 is connected to the output end of the NAND gate A52, and the output end is connected to the clock signal input end CK of the BCD (Binaly Coded Decimal) down counter 10 via the inverter N38. BC
The D down counter 10 is a counter that counts down by one each time a photo is taken from the set number of film frames, and has seven input terminals A _{I to} G _I and seven output terminals A _{o to} G _o . Each has its own lower 4 bits input terminal
A _{I to} D _I and output terminals A _{o to} G _o correspond to the first digit of decimal number,
The input terminals E _{I to} G _I and the output terminals E _{o to} G _{o of the} upper 3 bits correspond to the second digit of the decimal number. This BCD down counter 10
Input terminals A _{I to} G _I are connected to output terminals Q _{A to} Q _G of the D-latch row 20, respectively, and output terminals A _{o to} G _o are input terminals D _{A to} D _{G of the} D-latch row 20. Respectively connected to. The output terminals A _{o to} G _o of the BCD down counter 10 are connected to the input terminals of the decoder 30, respectively, and the output terminal of the decoder 30 is a driver.
The driver 40 is connected to the input end thereof, and the output end of the driver 40 is connected to the drive electrodes of a liquid crystal display (LCD) 50 as a display device. Further, the output terminal A of the BCD down counter 10
_o ~G _o are connected to the 7 input terminal of the input NAND gate A55 via the inverter N41～N47. The output terminal of the NAND gate A55 is connected to the input terminal D of the D latch circuit DF1, and the output terminal Q of the D latch circuit DF1 is input via the inverter N48 to one input terminal of the NAND gate A52 and one input terminal of the NAND gate A53. Connected to each end. The other input terminal of the NAND gate A52 is connected to the inverter N49.
Is connected to the output end of the NAND gate A53, and the other input end of the NAND gate A53 is a switch for detecting whether or not a long film back is attached to the camera (hereinafter, this switch is referred to as a long length detection switch) S _13a , It is connected to the other end of S _13b .

The long detection switches S _13a and S _13b are formed of normally-closed dual switches provided in the motor drive device, and when the long film back is attached to the camera, FIG. As shown in, it is designed to be opened in conjunction with this. One end of one switch S _13a of the long detection switches S _13a and S _13b is grounded through a connection contact J ₁₁ that connects the motor drive device and the long film back, and the other end of S _13a is It is connected through a resistor R ₂₃ to a power supply that has the potential -V _EE2 . Also, the other switch S _13b
One end of the switch S is connected to the connection contact J ₁₂ that connects the motor drive unit and the long film back, and the switch S
The other end of _13b is connected to the other end of switch S _13a . The connection contact J ₁₂ is connected to a power source that takes a potential −V _EE2 through a resistor R ₂₄ and is also connected to a fifth input end of the NAND gate A 16 (see FIG. 1A). A long frame number counter switch S ₁₂ is connected between the connection contacts J ₁₁ and J _{12 of} the long film back.
This switch S ₁₂ is a switch interlocking with a mechanical subtraction type film counter provided in the long film back, and is shown in FIG. 4 (B) when the count of the counter becomes zero. It is designed to be opened.

The other ends of the long detection switches S _13a and S _13b are connected to the other input end of the NAND gate A57 and the input end of the decoder 30, respectively. One input terminal of the NAND gate A57 is connected to the other end of the reset switch S ₅ through the inverter N53. This reset switch S ₅
Is the number of set film frames stored in the D latch row 20 in BCD
It is a normally-open switch for resetting to the down counter 10, and is closed only when a reset button (not shown) corresponding to the switch S ₅ is pressed.
One end of this reset switch S ₅ is grounded and the other end is a resistor.
It is connected to a power supply that has the potential -V _EE2 through R ₂₅ .

The output terminal of the NAND gate A57 is connected to the other input terminal of the NAND gate A58 and the NAND gate A58 via the inverter N54.
26 (see FIG. 1 (A)), respectively. The output end of the NAND gate A58 is connected to the other input end of the NAND gate A59, and one input end of the NAND gate A59 is connected to the output end of the inverter N49. The output terminal of the NAND gate A59 is connected to the set terminal of the BCD down counter 10 via the inverter N55.
Connected to SET. Therefore, BCD down counter 10
On the basis of a signal input to the set terminal SET via the inverter N55, the number of set film frames stored in the D latch row 20 is input and reset.

The motor drive device is further provided with a set switch S ₄ . The set switch S ₄ is a normally open switch for setting the number of film frames in the D latch row 20, and is closed only when a set button (not shown) corresponding to the switch S ₄ is pressed. It is supposed to do. One end of this set switch S ₄ is grounded, and the other end is connected to a power supply that takes a potential −V _EE2 through a resistor R ₂₂ and is connected to an input end D of a D latch circuit DF 2 for preventing chattering. . At the clock signal input terminal KC of the D latch circuit DF2, the frequency f ₂ is fed from the frequency dividing circuit 60 (see FIG. 1A).
Pulse signal is applied to the output terminal Q of the same circuit DF2.
Are connected to the input terminal of the inverter N49 and the other input terminal of the NAND gate A56, respectively. Above inverter
The output terminal of N49 is connected to the other input terminal of the NAND gate A5, and is also connected to each reset signal input terminal of the five flip-flop circuits which are cascaded to form the binary counter BC7. A pulse signal of frequency f ₁ is applied from the frequency dividing circuit 60 (see FIG. 1A) to the input terminal of the first-stage flip-flop circuit of the binary counter BC7. The output terminal of the flip-flop circuit is connected to one input terminal of the NAND gate A56 via the inverter N51. The output terminal of the NAND gate A56 is connected to the other input terminal of the NAND gate A49, and is also connected to the clock signal input terminal CK of the D latch train 20 via the inverter N52. Therefore, the D latch train 20 is adapted to change the value of the stored number of set film frames based on the pulse signal inputted through the inverter N52. That is, FIG. 5 (a)
When the set switch S ₄ is closed as shown in, the frequency f ₁
Frequency f ₁ obtained by frequency-dividing the pulse signal (see FIG. 5B)
A pulse signal of / 32 is output from the binary counter BC7, and this is passed through the inverter N51, NAND gates A56, A49, A51 and the inverter N38 (Figs. 5 (f), (g), (l),
(See (m) and (n)), and is applied to the clock signal input terminal CK of the BCD down counter 10. Therefore, the counter 10
Subtraction is performed according to this pulse signal. At the same time,
The pulse signal output from the binary counter BC7 is also applied to the clock signal input terminal CK of the D latch train 20 through the inverter N51, the NAND gate A56, and the inverter N52 (see FIGS. 5 (f) to (h)). . Therefore, the D latch row 20 is
Every time a pulse signal is input, the BCD down counter 10
The content of is transferred and stored, and the number of set film frames is updated. Therefore, the contents of the BCD down counter 10 are the contents of the decoder 3
Since it is displayed on the liquid crystal display 50 through the driver 0 and the driver 40, if the set switch S ₄ is closed when the displayed number of frames reaches a desired value, the number of film frames in the D latch row 20 is displayed. Is set. At this time, it goes without saying that the content of the BCD down counter 10 is the set number of film frames.

If the closing time of the set switch S ₄ is shorter than the cycle of the output pulse signal of the binary counter BC 7, only 1 pulse is input to the BCD down counter 10, so the counter 10 is down by 1 and the set switch S ₄ is set. If the S ₄ is closed for a long time, since the continuously pulse signal to the BCD down counter 10 is input, the counter 10 is sequentially counted down. BCD down counter 10
When a pulse signal is input again after the content of is zero, the content of count 10 returns to the maximum value that can be input,
The subtraction can be performed again.

Returning to FIG. 1 (A), not only the power supply E ₁ but also the above-mentioned drive motor is included in the power supply device connected to the motor drive device.
A control circuit 13 for M1 (see FIG. 6) is also incorporated. The control circuit 13 is connected to the circuit of the motor drive device by connecting contacts J ₁ , J _{3 to} J ₆ . Of these connecting contacts, the connecting contact J ₅ is connected to the base of the NPN transistor T ₂₂ through the resistor R ₃₁ and the transistor T ₂₂
The emitter of is connected to connecting contact J ₆ . The collector of the transistor T ₂₂ is connected to the emitter of the NPN transistor T _21, the base transistor T ₂₁ is connected to the connection contact J ₄ through a resistor R _32. The collector of the transistor T ₂₁ is connected via a resistor R _33.
It is connected to J ₃ as well as to one end of capacitor C ₁₁ . The other end of the capacitor C ₁₁ is connected to the connection contact J ₅ through a resistor R ₃₄ and also the diode D ₁₂
Is connected in the forward direction to the base of the NPN transistor T ₂₄ and the resistor R _{37 to} the cathode of the diode D ₁₁ . The anode of diode D ₁₁ is for continuous shooting
It is connected to a connection contact J ₆ via a switch (hereinafter, referred to as a continuous single switch) S ₉ for switching one frame shooting. The continuous shooting mode can be obtained by opening the serial / single switch S ₉ , and the single frame shooting mode can be obtained by closing the switch.

The emitter of the transistor T ₂₄ is connected to the connection contact J ₆ and also to the emitter of the NPN transistor T ₂₅ . The collector of the transistor T ₂₄ is connected to the emitter of the NPN type transistor T ₂₃ , and the base of the transistor T ₂₃ is connected to the connection contact J ₄ via the resistor R ₃₅ . The collector of the transistor T ₂₃ is connected to the connection contact J ₅ through the resistor R _{36 and} the base of the transistor T ₂₅ . The collector of the transistor T ₂₅ is connected to the connecting contact J ₅ via the relay Y ₁ and the diode D ₁₃ in parallel. The relay Y ₁ is interlocked with the changeover switch S ₁₁ , and when the relay Y ₁ is not energized, the changeover switch S ₁₁ brings the movable contact piece into contact with the braking terminal j,
When the relay Y ₁ is energized, the changeover switch S
₁₁ movable contact pieces are switched to the power supply connection terminal i.

The connection contact J ₅ is connected to one end of the normally open operation switch S ₈ , and the other end of the switch S ₈ is connected to the connection contact.
J ₃ , positive electrode of power supply E ₁ and braking terminal j of changeover switch S ₁₁
Respectively connected to. Negative of the power source E ₁ is the power switch S ₁₀ connection contact J ₆ and the changeover switch S ₁₁ via the
Of the power supply connection terminals i. The movable contact terminal of the changeover switch S ₁₁ is connected to the connection contact J ₁ . The connection contact J ₃ is grounded in the motor drive device, and therefore, when the power switch S ₁₀ is closed, the connection contact J ₆ is at the potential -V due to the electromotive voltage of the power supply E _1.
It is designed to take _EE1 .

FIG. 6 shows a power supply circuit system in the motor drive device. The power supply E ₁ is a large-capacity power supply for driving a motor arranged in the power supply device, and the power supply E ₂ is a small-capacity power supply for a motor control / display circuit provided in the motor drive device. The positive electrode of the power source E ₂ is grounded, and the negative electrode is connected to the emitter of the NPN transistor T ₃₁ . The base of the transistor T ₃₁ is grounded through the resistor R ₄₁ , and is also connected to the anode of the Zener diode ZD ₁ through the diode D ₂₁ in the forward direction. The collector of the transistor T ₃₁ is grounded via the capacitor C ₂₁ and is also connected to the emitter of the PNP type transistor T ₃₂ . The emitter of the transistor T ₃₂ is also connected to the other end of the motor control / display circuit 11, and one end of the motor control / display circuit 11 is grounded. The base of the transistor T ₃₂ is connected to the emitter of the PNP type transistor T ₃₃ , the collector is connected to the collector of the transistor T ₃₃ through the resistor R ₄₂ , and the connecting contact J ₆
It is connected to the. The base of the transistor T ₃₃ is
It is connected to the anode of the Zener diode ZD _{1 and also to} the connection contact J ₆ through a resistor R ₄₃ .
The Zener diode ZD ₁ is a motor control / display circuit 1
It serves to generate a constant voltage to be supplied to 1, the cathode of which is grounded. Motor control above
The output end of the display circuit 11 is connected to the input end of the motor drive circuit 12, one end of the motor drive circuit 12 is grounded, and the other end is connected to the connection contact J ₆ . Further, both ends of the drive motor M1 are connected to the motor drive circuit 12.

On the other hand, one end of the motor drive circuit 13 provided in the power supply device is grounded to the motor drive device through the connection contact J ₃ , and the other end is connected to the connection contact J ₆ and the power switch S It is connected via ₁₀ to the negative pole of the power supply E ₁ . The positive electrode of the power source E ₁ is grounded through the connection contact J ₃ . The motor control circuit 13 is connected to the motor control circuit 11 through a connection contact.

In the power supply circuit system of such a motor drive device,
When the power switch S ₁₀ is closed, power is supplied to the motor control circuit 13 and the motor drive circuit 12 from the power supply E _{1 at the} voltage V _EE1 , and a constant voltage circuit composed of the transistors T ₃₂ , T ₃₃ and the zener diode ZD ₁ is opened. _Power is supplied to the motor control / display circuit 11 via the voltage V _EE2 via the motor control / display circuit 11. Since the power switch S ₁₀ is on, the transistor T ₃₁ is off and the power of the power source E ₂ is not consumed. Further, when the power switch S ₁₀ is off, power is not supplied to the motor control circuit 13 and the motor drive circuit 12, but the base potential of the transistor T ₃₁ becomes “H” level.
The transistor T ₃₁ turns on, and the motor control / display circuit 11
The power is supplied from the power source E ₂ only to.

As described above, the motor drive device of this embodiment is configured.

Next, the operation of this motor drive device will be described.

First, in the initial state, as long as the power source battery (power source E ₁ ) is loaded in the motor drive device, power is being supplied to the motor control / display circuit 11 (see FIG. 6). Each circuit element has an output state as shown in (a) to (z), (α), (β) of FIGS. 7 (A) and (B), for example. That is, in this initial state, since the release switch S ₁ is open, the output of the NAND gate A6 is at the “H” level (see FIGS. 7A and 7A), and the movable reflecting mirror is at the lowered position. Therefore, the output of the inverter N3 is at "H" level (see FIGS. 7 (A) and (g)). In addition, the motor switch S ₆
Since the release terminal b has been switched to the ring, the output of the NAND gate A14 is at the "L" level (see FIGS. 7A and 7D). Furthermore, if at least one output of the BCD down counter 10 is at "H" level,
The output of the NAND gate A55 is at "H" level, and the output of the D latch circuit DF1 is at "H" level.

The inverter N3, which is the input to the NAND gate A15
Output is "H" level (see FIGS. 7 (A) (g)), NAND gate A9 output is "L" level (see FIGS. 7 (A) (c)), NAND gate A8 output is "L". Since the output of the inverter N15 is at "H" level (see FIG. 7 (A) (i)) and the output of the NAND gate A33 is at "H" level, the NAND gate The output of A15 is "H" level. The output of the inverter N3, which is the input of the NAND gate A16, is at the "H" level (see FIG. 7 (A) (g)), and the output of the NAND gate A11 is at the "L" level (FIG. 7 (A) (e). Since the output of the NAND gate A14 is at "L" level (see FIGS. 7A and 7D) and the output of the NAND gate A53 is at "H" level, the output of the NAND gate A16 is at "H" level. There is. Therefore, the output of the NAND gate A17 is at "L" level and the inverter N32
The output of They become "H" level, the transistor T ₃ through T ₆
Is off and motor M1 is not rotating.

When the rear cover of the camera is opened to load the film from such an initial state, the rear cover switch S ₃ is turned on (7th
(See FIGS. 7B and 7W.) "H" level reset signals are applied to the reset signal input terminals of the respective flip-flop circuits forming the binary counter BC3. Therefore, the output of each flip-flop circuit becomes "L" level (7th
(B) (u) and (v)), the output of the NAND gate A27 becomes "H" level (see (B) and (z) in FIG. 7). However, at this time, the output of the NAND gate A26 becomes "L" level (see FIG. 7 (B) (β)), and therefore the output of the NAND gate A33 remains "H" level.

After loading the film into the camera and closing the rear cover, the rear cover switch S ₃ is turned off (see FIGS. 7 (B) and (w)).
Therefore, the "L" level signal is applied to the reset signal input terminals of the respective flip-flop circuits forming the binary counter BC3.

Next, when the release button is pressed from this state and the release switch S ₁ is closed, as described above, the switch
After closure of S _1, for a predetermined time (e.g., 60 ms), the output of the NAND gate A6 is maintained at "L" level (Figure 7 (A)
(See (a)), the output of the inverter N7 becomes "L" level (see FIGS. 7 (A) and (b)), and the NAND gate A8 and
Each output of A9 becomes "H" level (Fig. 7 (A))
(See (h) and (c)). Initially, NAND gate A1
5 inputs are “H” except outputs of NAND gates A8 and A9
Since the output of the NAND gates A8 and A9 becomes "H" level, the output of the NAND gate A15 becomes "L" level (see FIG. 7 (A) (k)), and the output of the NAND gate A17 becomes The "H" level and the output of the inverter N32 become the "L" level (see FIGS. 7 (A) (l) and (m)). Therefore, the transistor T ₃ turns on and the transistor
T _4, T ₅ and T ₆ are turned on, respectively, energization is performed to the drive motor M1, the motor M1 starts rotating for the film jump feed.

Drive motor M1 is rotated, the release is performed, the movable reflecting mirror is increased, the camera switches S ₂ is up pin up
The output of the inverter N3 is inverted to the "L" level because it is switched to the ring (see FIG. 7 (A) (g)). Therefore, the outputs of the NAND gates A15 and A16 both become "H" level (see FIGS. 7A, 7J, and 7K), and the NAND gate A1
The output of 7 becomes "L" level (see FIG. 7 (A) (l)). Accordingly, the output of the inverter N32 becomes "H" level (Figure 7 (A) (m) see), turned off and the transistor T _3, and off the transistor T _4, T ₅ and T ₆ are each motor Power to M1 is cut off. At the same time, the "L" level output of the NAND gate A17, the braking circuit is activated, the output of the NAND gate A46 is constant time "L" level, the transistors T ₁₁ and T ₉ are turned on, the motor M1 Both ends are short-circuited and the motor M1 is braked. Therefore, the motor M1 suddenly stops. further,
Almost at the same time as when the movable reflecting mirror is raised, the motor switch S ₆ switches the hoisting terminal a to the hoist.

When the movable reflecting mirror is raised and the shutter is actuated to end the exposure, the movable reflecting mirror is moved back and forth this time, and the camera switch S ₂ is switched to the down terminal dw.
At this point, the motor switch S ₆ has already switched to the hoisting terminal a, so the output of the NAND gate A14 is "H".
Level, the output of the inverter N3 becomes "H" level (7th
(A), (d), and (g)), the output of the NAND gate A16 becomes "L" level (see (A) and (j) in FIG. 7). Therefore, the output of the NAND gate A17 becomes "H" level and the output of the inverter N32 becomes "L" level (Fig. 7 (A)).
(L), since the (m) refer), the transistor T ₃ through T ₆ is turned on, it starts to rotate the motor M1 again performs upper winding of the film.

By the way, the output of the NAND gate A19 is at "L" level in the initial state (see FIG. 7 (B) (s)), but when the movable reflecting mirror rises, the output of the inverter N2 becomes "L" level (see 7 (B) (p)), the output of the NAND gate A19 becomes "H" level (FIG. 7 (B) (s).
reference). Further, when the movable reflecting mirror descends, the output of the inverter N2 becomes "H" level (see FIG. 7 (B) (p)), which causes the output of the binary counter BC2 to be "a little delayed by the chattering time". It becomes H "level. Therefore,
The output of the NAND gate A19 becomes "L" level (see FIG. 7 (B) (s)). Therefore, one pulse is input to the input end of the binary counter BC3 each time the movable reflecting mirror moves up and down once.

At the stage when the first film winding is completed, the output of the NAND gate A28 remains at the “L” level (see FIG. 7 (B) (o)), so the outputs of the NAND gates A8 and A9 are “H”. It is at the level (see FIGS. 7 (A), (h), and (c)), and since the movable reflecting mirror is descending,
The output of N3 is at "H" level (see FIG. 7 (A) (g)). Further, since the motor switch S ₆ is changed release terminal b Gawani cutting, (see FIG. 7 (A) (i)) the output of the inverter N15 is "H" level. Therefore, the output of NAND gate A15 becomes "L" level (Fig. 7 (A)).
(See (k)), the output of the NAND gate A17 is at "H" level,
The output of the inverter N32 becomes "L" level (see (A), (l), (m) in FIG. 7), the motor M1 continues to rotate, and then, similarly to the case of the first time, the second release. And film winding is performed.

When the camera switch S ₂ switches the up terminal up again to the upper side with the _second raising of the mirror, the output of the binary counter BC3 becomes “H” level (see FIG. 7 (B) (v)). Therefore, the output of the NAND gate A27 becomes "L" level and the output of the NAND gate A28 becomes "H" level (Fig. 7 (B)).
(See (o) and (z)). By this output of the NAND gate A28 becomes "H" level, the output of NAND gate A9 is a signal from the subsequent release switch S _1, i.e., a state which is determined by the output of the inverter N7. Also, the output of the NAND gate A8 becomes "L" level (Fig. 7 (A)).
Therefore, the output of the NAND gate A15 becomes "H" level (see FIG. 7 (A) (k)). Therefore, when the second winding of the film is completed, the idling of the film is automatically stopped regardless of whether the release switch S ₁ is opened or closed.

The description of the operation of the above air feed, is a description of preliminary feeding operation in the motor drive one frame shooting mode the communication single change-over switch S ₇ is switched to the one frame of imaging terminal b of the continuous single switching In the continuous shooting mode in which the switch S ₇ is switched to the continuous shooting terminal a and the power supply unit opens the continuous single switch S ₉ , the binary movement is performed when the movable reflecting mirror is raised for the second time. The counter BC3 outputs the "H" level output, and the output of the NAND gate A26 becomes the "H" level. On the other hand, since the output of the NAND gate A6 remains at "H" level, the output of the NAND gate A32 remains at "H" level (see FIGS. 7C and 7J), but the NAND gate A3
The output of 3 becomes "L" level because the output of the NAND gate A26 becomes "H" level (see FIG. 7 (C) (k)). This is maintained until the next release button is pressed.
When the output of the NAND gate A33 becomes "L" level, the output of the NAND gate A15 always becomes "H" level, so that the release cannot be performed.

Next, the operation of the motor drive device in the case of single frame photography will be described. One-frame shooting mode, the motor drive device or switch the communication single change-over switch S ₇ of I in one frame shooting terminal b side, or continuous single change-over switch S ₉ the power supply is I
Obtained when you close the. Here, a case where the continuous single changeover switch S _{7 is changed over} to the terminal b will be described as an example.

To do one frame shooting, an empty feeding of the film to close the release switch S ₁ by pressing the release button from the finished state, as in the case of air feed described above, the output of NAND gate A6 and A7 are " Since the output of the NAND gates A8 and A9 becomes the "H" level (see FIGS. 8 (h) and 8 (c)), the output of the NAND gate A15 is output. Becomes "L" level (8th
(See FIG. (K)). Therefore, the output of the NAND gate A17 becomes "H" level and the output of the inverter N32 becomes "L" level (see FIGS. 8 (l) and 8 (m)), and the motor M1 starts rotation for shutter release. . When the motor M1 rotates, increases the movable reflecting mirror, camera switch S ₂ is switched up pin up Gawani cutting. Then, the output of the inverter N3 becomes "L" level (see FIG. 8 (g)), and the output of the NAND gate A15 returns to "H" level (see FIG. 8 (k)). Therefore, the output of NAND gate A17 is at "L" level,
The output of the inverter N32 becomes “H” level (see (l) and (m) in FIG. 8), the power supply to the motor M1 is cut off, and the brake circuit operates for a certain period of time to rotate the motor M1. Is stopped. Further, almost simultaneously with the rise of the movable reflecting mirror, the motor switch S ₆ is switched to the hoisting terminal a, and the output of the NAND gate A14 becomes "H" level (see FIG. 8 (d)).

When the shutter is operated and the exposure is finished after the movable reflecting mirror is raised, the camera switch S ₂ is switched to the down terminal dw as the movable reflecting mirror moves back and down. As a result, the output of the inverter N3 is inverted to the "H" level (see FIG. 8 (g)). Also, because the output of NAND gate A14 is at "H" level, NAND gate A11
Output remains at "H" level (see FIG. 8 (e)). Therefore, the output of the NAND gate A16 becomes "L" level (see FIG. 8 (j)), the output of the NAND gate A17 becomes "H" level, and the output of the inverter N32 becomes "L" level (see FIG. 8 (l). ), (M)), the motor M1 now starts to rotate due to film winding.

When the winding of the film for one frame that has been photographed is completed, the motor switch S ₆ switches the release terminal b to the ring, so that the output of the NAND gate A14 becomes "L" level (see FIG. 8 (d)). The output of the NAND gate A16 returns to "H" level (see FIG. 8 (j)). Therefore, Nand Gate A17
Output goes to "L" level and the output of the inverter N32 goes to "H" level (see (l) and (m) in FIG. 8), the power supply to the motor M1 is cut off and the brake circuit is operated for a certain time. The motor M1 is actuated and the rotation of the motor M1 is stopped. At the time when the winding of this film is completed, even if the release switch
Even if S ₁ continues to be closed, the output of NAND gate A 6 returns to “H” level, so the input terminals of NAND gate A 8 are all at “H” level.
Since the output of A8 is at "L" level, the NAND gate A1
The output of 5 always becomes "H" level. Therefore, there is no possibility that the release operation will be performed again after the film is wound, and when one frame is photographed and the film is wound, the motor drive device surely stops the operation.

In addition, the content of the BCD down counter 10 is decremented by one in accordance with the above-described one frame shooting. That is, the output of the inverter N2 changes as shown in FIG. 9 (a) in response to one up / down movement of the movable reflecting mirror, and the inverter N1
2, Binary counter BC2, Inverter N16, NAND gate A18, A19
Since the output of the inverter changes as shown in FIGS. 9 (b) to 9 (e) and (h), one pulse is output to the output terminal of the inverter N18. The output of the NAND gate A56 is as long as "H" not closed the set switch S ₄ so (Figure 9 (l) refer), the pulse output of the inverter N18, the NAND gate A
Through 49, A51 and inverter N38 (Fig. 9 (p),
(See (q) and (r)), and is input to the clock signal input terminal CK of the BCD down counter 10. Therefore, the BCD down counter 10 is decremented by 1 in response to one up / down movement of the movable reflecting mirror. When the content of the counter 10 becomes zero, the output of the D latch circuit DF1 becomes "L" level, and the pulse signal is not applied to the clock signal input terminal CK of the counter 10 through the inverter N48 and the NAND gates A52 and A51. , Counter 10 stops further subtraction.

Next, the operation of the motor drive device in the case of continuous shooting will be described. In the case of this continuous shooting, the single continuous switch S ₇ is switched to the continuous shooting terminal a. Incidentally, it is necessary to open the continuous single change-over switch S ₉ the power supply is I also select a continuous shooting mode.

When switching the communication single change-over switch S ₇ the continuous shooting terminal a side, the potential of the other end of the same switch S ₇ is made to change according to the switching of the changeover switch S ₁₁ of I the power unit . That is, the changeover switch S ₁₁ is set to the “H” level when the braking terminal j is switched to the alligator side, and is set to the “L” level when the power supply connection terminal i is switched to the alligator.

The first frame of the release and Furuimu hoisting is carried out similarly to the case of a one-frame shooting as described above, when the on Furuimu winding is completed, continuous single change-over switch S ₉ on the power supply I is opened it makes the changeover switch S ₁₁ is a power supply connection terminal i side, therefore, a second input terminal of the NAND gate A8 is stuck in the "L" level. Therefore,
As shown in FIG. 10 (h), the output of the NAND gate A8 is at the "H" level, the output of the NAND gate A15 is at the "L" level, the output of the NAND gate A15 is at the "L" level, and the output of the NAND gate A17 is at the output. "H" level, the output of the inverter N32 becomes "H" level (Fig. 10 (k), (l),
(See (m)), the motor M1 continues to rotate, and the second frame is released following the film winding of the first frame. Then, after the release, the film of the second frame is wound as in the case of the first frame.

If, as shown in FIG. 10, the release switch S ₁ is opened after the second frame is released, the transistor T ₂₂ is turned off and the relay Y ₁ is deenergized in the power supply device. ₁₁ , the braking terminal j is switched to the alligator. Therefore, the second input terminal of the NAND gate A8 becomes "H" level, and the output of the gate A8 is inverted to "L" level (see FIG. 10 (h)). Therefore, when the film winding for the second frame is completed and the motor switch S ₆ is switched to the release terminal b, the motor drive device is stopped and the continuous shooting is completed.

It is needless to say that a pulse signal is input to the BCD down counter 10 and the content of the counter 10 is decremented by 1 each time the movable reflecting mirror is moved up and down even during the continuous shooting.

Then, when the contents of the BCD down counter 10 become zero during continuous shooting, all the output terminals A _{o to} G _{o of} the counter 10 become “L” level, so the output of the NAND gate A55 becomes “L” level. Becomes "L" level output of the NAND gate A55 is a D latch circuit DF1 is read in synchronism with the vertical movement of the closing or movable reflecting mirror of the release switch S _1, and is outputted from the output Q of the circuit DF1. In other words, when the shooting of the preset number of film pieces is completed,
The output of the D latch circuit DF1 is inverted to "L" level. When the output of the D latch circuit DF1 becomes "L" level, the inverter N
48, 4th of Nandgate A16 through Nandgate A53
Since the input terminal of is at "L" level, the output of the gate A16 is always at "H" level, the output of the NAND gate A17 is at "L" level, the output of the inverter N32 is at "H" level, and the film The rotation of the motor M1 for hoisting is automatically stopped. Also, since the output of NAND gate A52 becomes "L" level and the output of NAND gate A51 becomes "H" level, even if the shutter is released by manually winding the film thereafter, the count operation of BCD down counter 10 Is not done.

Further, although the content of the BCD down counter 10 does not become zero during continuous shooting, the film winding is automatically stopped even when the film reaches the end. That is, when the exposure for the last one frame is completed, the movable reflecting mirror descends and the motor M1 rotates to try to wind up the film. However, since the film has reached the end portion, one frame cannot be wound up, and the motor switch S ₆ switches the release terminal b to the ring while the release mechanism is not charged (see FIG. 11 (n)). . Then, the output of the NAND gate A14 becomes "L" level (see FIG. 11 (g)), and the output of the NAND gate A11 becomes "L" level (first).
See Fig. 1 (f). On the other hand, since the change-over switch S ₁₁ of the power supply device is switched to the power supply connection terminal i, the output of the NAND gate A8 is at the "H" level (see FIG. 11 (j)) and the NAND gate A15. , A17, and the inverter N32 allow the motor M1 to continue rotating for the next release (see FIGS. 11 (p) and 11 (q)). However, since the release mechanism is not charged, raised the movable reflecting mirror is not performed, when the motor switch S ₆ is the time switched to the winding terminal a motor M1 is stopped, the NAND gate A11 since "L" level The output prevents the motor M1 from restarting rotation.

When the content of the BCD down counter 10 becomes zero as described above, the reset switch is used to restore the content of the counter 10 to the set film frame number stored in the D latch row 20.
The S ₅ may be closed. Thus, the "L" level signal is applied to one input terminal of the NAND gate A57 through the inverter N53, and the "L" level signal is applied to the set signal input terminal of the BCD down counter 10 through the NAND gate A57, the inverter N54, the NAND gates A58, A59, and the inverter N55. Since the H "level signal is applied, the number of set film frames stored in the D latch row 20 is input and set in the BCD down counter 10. At the time of closing of the reset switch S _5, the inverter N5
The output of 4 is input to the NAND gate A26, and the output of the gate A26 is forcibly set to the "H" level so that the film is not fed in advance when the number of film frames is reset.

Further, the number of film frames is automatically returned by closing the rear cover switch S ₃ . That is, when opening the lid after the camera for the exchange of the film, the back cover switch S ₃ is closed, but when the switch S ₃ is closed, since the binary counter BC3 is reset, the output of the inverter N21 is "H "Level, the output of the inverter N22 becomes" L "level, and the output of the NAND gate A26 becomes" L "level. Therefore, the output of NAND gate A58 becomes "H" level, and NAND gate A58
59, the "H" level signal is applied to the set signal input terminal of the BCD down counter 10 through the inverter N55. Therefore, the BCD down counter 10 is set to the value of the set film frame number stored in the D latch row 20.

On the other hand, if the release switch S ₁ is closed with the rear lid still open, the output of the inverter N22 is at the “L” level (see FIG. 12 (d)), and the output of the NAND gate A28 is at the “H” level. It remains at the level (see Fig. 12 (g)). Therefore, in the single frame shooting mode, all the inputs of the NAND gate A8 become "H" level after the single frame shooting,
The output of the gate A8 becomes "L" level (see FIG. 12 (h)), and the second frame is not released. Further, in the case of a continuous shooting mode, in while closing the release switch S _1, performed continuously on the release and film take is, when opening the release switch S _1, the changeover switch of the power supply I S ₁₁ is switched to the braking terminal j,
Since the second input terminal of the NAND gate A8 becomes the "H" level, the subsequent shooting operation is not performed as in the case of the single frame shooting mode.

By the way, when the long film back is attached to the camera, the motor drive device enters the no-count mode. That is, when the long film back is attached to the camera,
As described above, the elongate film unless the content of the mechanical subtractive film counter built in the back is not zero, the long frame number counter switch S ₁₂ as shown in FIG. 4
Is closed, the potential of the connecting contact J ₁₂ becomes "H" level. Further, the electric potentials at the other _ends of the long attachment detection switches S _13a and S _13b become "L" level. For this reason, Nand Gate A5
The output of 7 becomes "H" level, and BCD down counter 1 via inverter N54, NAND gates A58, 59, and inverter N55.
The "H" level signal is input to the set signal input terminal of 0,
The counter 10 is in a set state in which the stored value of the D latch column 20 is output. Therefore, the counter 10 does not perform the subtraction even if the photographing is performed. That is, when the long film back is attached to the camera, the set state of the BCD down counter 10 is maintained, so that the motor drive device enters the no count mode. Further, if the other input terminal of the NAND gate A53 becomes "L" level and the number of film frames set in the D latch row 20 is other than zero, the output terminal Q of the D latch circuit DF1 also becomes "H" level. A53 output is "H"
It becomes a level. Therefore, the input to the NAND gate A16, the output potential and the NAND gate A53 connection contact J ₁₂ is both "H" level, the winding of the film becomes ready.

Then, when the content of the mechanical subtraction type film counter built into the long film bag becomes zero, the switch S ₁₂
Is released and the potential of the connection contact J ₁₂ is inverted to the “L” level, so that the output of the NAND gate A16 is always at the “H” level, and subsequent film winding is impossible.

Also, when the motor drive device of the present embodiment is equipped with a camera that cannot be used by mounting the motor drive device, the motor drive device does not perform the release operation or the film winding operation. That is, as shown in FIG. 13, a camera of an unusable model has a diode between the down terminal dw of the camera switch S ₂ and a connection contact (not shown).
Even if D ₂₁ is connected in the forward direction and the down terminal dw of the camera switch S ₂ is switched to the alligator, the input terminal of the inverter N1 will always be at the "H" level.
The output of A2 becomes "H" level, the output of the inverter N3 becomes "L" level, and the outputs of the NAND gates A15 and A16 always become "H" level. Therefore, the motor drive device prevents the release operation and the film winding operation from being performed. It should be noted that the camera can be used to manually release and wind the film.

14 (A) and 14 (B) show an electric circuit of a motor drive device having a film idling function according to another embodiment of the present invention. The motor drive device of the present embodiment is different from the motor drive device of the embodiment shown in FIGS. 1A and 1B in that , (2) A function to display that fact while the film is being fed, (3) A function to instruct the rewinding operation of the next film when the content of the BCD down counter 10 becomes zero, (4) It is configured by adding a rewinding function and a function to automatically stop at the end of rewinding. Therefore, regarding the configuration of the motor drive device of this embodiment, FIG.
Differences from the configuration of the motor drive device of the embodiment shown in (B) will be mainly described.

First, the output terminal of the flip-flop circuit at the subsequent stage of the binary counter BC2 is connected to one input terminal of the NAND gate A18 via the inverter N16 and also connected to the input terminal of the flip-flop circuit F1. The reset signal input terminal of the flip-flop circuit F1 is connected to the output terminal of the inverter N12, and the output terminal is connected to one input terminal of the NAND gate A21 via the inverter N17.
The output end of the NAND gate A18 is connected to one input end of the NAND gate A19, and the output end of the NAND gate A19 is
Both NAND gates A18 and A19 are connected to the other input terminal of the NAND gate A18 to form an RS flip-flop circuit. The output terminal of the NAND gate A18 is also connected to the first input terminal of the 3-input NAND gate A11 and one input terminal of the NAND gate A23, and the output terminal of the NAND gate A19 is connected to the binary counter BC3 via the inverter N18. It is connected to the input terminal of the first-stage flip-flop circuit and also to one input terminal of the NAND gate A48 (see FIG. 14B).

The output terminal of the NAND gate A21 is connected to the NAND gate A
22 is connected to one input terminal of the NAND gate A22, and the output terminal of the NAND gate A22 is connected to the other input terminal of the NAND gate A21. The NAND gates A21 and A22 form an RS flip-flop circuit. The output terminal of the NAND gate A22 is connected to the other input terminal of the NAND gate A23, and the output terminal of the NAND gate A23 is connected to one input terminal of the NAND gate A24. The other input end of the NAND gate A24 is connected to the output end of the inverter N28, and the output end of the NAND gate A24 is connected to the D latch circuit DF1 (Fig. 14 (B)).
(See) the clock signal input terminal CK.

Further, the camera to which the motor drive device of this embodiment is mounted is provided with a rear cover lock switch S _{14 in} parallel with the rear cover switch S ₃ . The rear lid lock switch S ₁₄ is a switch that is closed by opening the rear lid and is for detecting whether or not the rear lid is securely closed. The other end of the rear cover switch S ₃ is connected to one input terminal of the NAND gate A34, the other input terminal of the NAND gate A34 is connected to the other end of the device type detection switch S _15. The type detection switch S ₁₅ is a switch that is closed when mounting the camera compatible models to the motor drive device is used to determine the suitability of the motor drive unit and the camera. Therefore, when mounting the camera incompatible type motor drive unit, by type detection switch S ₁₅ is not closed, so that the function of the motor drive device is limited. That is, as will be described in detail later,
This motor drive device is equipped with a shutter release and film winding function when a compatible camera is installed.
It has various functions such as a subtraction counter function, automatic jump feed / reset and its display function, and film rewind and its display function. However, when a camera of a non-conforming model is installed, the shutter release and Only the film winding function and the subtraction counter function can be performed. Therefore, the camera of the non-conforming model does not mean a camera that cannot be used for this motor drive device at all, and the signal transmission is not possible because the corresponding connection contact is missing between the camera and the motor drive device. A camera that is insufficient and does not exhibit the specific function of the motor drive device. Therefore, it is different from the unusable camera described above.

One end of the model detection switch S ₁₅ is grounded, and the other end is connected to a power supply that takes a potential -V _EE2 through a resistor R ₁₁ and is also connected to a first input end of a 4-input NAND gate A26. . The output terminal of the NAND gate A34 is connected to the other input terminal of the NAND gate A27 and the second input terminal of the three-input NAND gate A28, and is also connected to the input terminal of the inverter N24. The output terminal of the inverter N24 is connected to the other input terminal of the NAND gate A36 via the inverter N26, and is also connected in cascade to each reset signal input terminal of the three flip-flop circuits forming the binary counter BC4. Each is connected.

The output terminal of the subsequent flip-flop circuit forming the binary counter BC3 is connected to the third input terminal of the 4-input NAND gate A26 and the input terminal of the decoder 30 (see FIG. 14B) via the inverter N21. It is connected. The second input terminal of the NAND gate A26 is connected to the output terminal of the inverter N54 (see FIG. 14 (B)). Nand gate
The output end of A26 is connected to one input end of a NAND gate A27, one input end of a NAND gate A58 (see FIG. 14B) and the decoder 30, respectively.
The output terminal of A27 is connected to the fourth input terminal of the NAND gate A26 and the first input terminal of the NAND gate A28. The output terminal of the NAND gate A28 is connected to one input terminal of the NAND gate A29, and the output terminal of the NAND gate A29 is connected to the third input terminal of the NAND gate A28. The output terminal of the NAND gate A28 is connected to the other input terminal of the NAND gate A29, and is also connected to one input terminal of the NAND gate A42 via the inverter N23.

The pulse signal of frequency f ₄ is applied from the frequency dividing circuit 60 to the input terminal of the first-stage flip-flop circuit of the binary counter BC4, and the output terminal of the last-stage flip-flop circuit is passed through the inverter N25. Connected to one input terminal of the NAND gate A35. The output terminal of the NAND gate A35 is connected to one input terminal of the NAND gate A36, the output terminal of the NAND gate A36 is connected to the other input terminal of the NAND gate A35, and both the NAND gates A35 and A36 are R
It forms an S flip-flop circuit. Nand Gate A
The output terminal of 35 is connected to the other input terminal of the NAND gate A38 and the other input terminal of the NAND gate A39, respectively, and is also connected to the other input terminal of the NAND gate A42, and the output terminal of the NAND gate A42 is connected to the NAND gate A9.
Of the NAND gate A8 and the third input terminal of the NAND gate A8. The output terminals of the NAND gate A36 are cascaded to form a binary counter BC5.
Each of the flip-flop circuits is connected to each reset signal input terminal. A pulse signal of frequency f ₅₅ is applied from the frequency dividing circuit 60 to the input terminal of the first-stage flip-flop circuit of the binary counter BC5, and the output terminal of the last-stage flip-flop circuit is passed through the inverter N27. It is connected to one input end of the NAND gate A37. The output terminal of the NAND gate A37 is connected to one input terminal of the NAND gate A38, the output terminal of the NAND gate A38 is connected to the other input terminal of the NAND gate A37, and both NAND gates A37 and A38 form an RS flip-flop circuit. is doing. The output terminal of the NAND gate A38 is connected to one input terminal of the NAND gate A39, and the output terminal of the NAND gate A39 is connected to the other input terminal of the NAND gate A41.
The output terminal of the NAND gate A41 is connected to the other input terminal of the NAND gate A24 and the other input terminal of the NAND gate A29 via the inverter N28.

Further, the camera is provided with an R clutch switch S ₁₇ and a film switch S ₁₈ , respectively, and the motor drive device is provided with an R lever switch S ₁₆ . The film switch S ₁₈ is a switch for detecting whether or not a film is loaded in the camera, and is opened when the film is loaded and closed when the film is not loaded. It is like this. One end of the switch S ₁₈ is grounded to the motor drive device through a connection contact (not shown), and the other end is connected to a power supply having a potential -V _EE2 through a connection contact (not shown) and a resistor R ₁₂ . . Also, the above R
The clutch switch S ₁₇ is a switch related to the R clutch for rewinding the film and is adapted to be closed in the rewinding state. One end of the switch S ₁₇ is grounded to the motor drive device through a connection contact (not shown), and the other end is connected to a connection contact (not shown) and a resistor R.
It is connected through ₁₃ to a power supply that takes a potential -V _EE2 . Further, the R lever switch S ₁₆ is a switch interlocking with an R lever (not shown) for rewinding provided in the motor drive device, and is closed at the time of rewinding. One end of the R lever switch S ₁₆ is grounded, and the other end is connected to the fifth input terminal of the NAND gate A15 and the fourth input terminal of the NAND gate A16 via the inverter N29, and the three-input NAND gate A43 is connected. Is connected to the first input end of. Further, the other end of the switch S ₁₆ is connected to a power source which takes a potential −V _EE2 through the resistor R ₁₄ . The second input terminal of the NAND gate A43 is the other end of the R clutch switch S _17, the third input terminal, an inverter N
They are connected to the other end of the film switch S ₁₈ via 31 respectively. The output terminal of the NAND gate A43 is an inverter N
It is connected to the input terminal of 35 and one input terminal of the NAND gate A47, respectively.

Further, in the motor drive circuit 13, the collector of the transistor T ₆ is connected to the connection contact J ₆ via the diode D ₃ in the reverse direction.
It is also connected to the collector of the PNP transistor T ₇ . The emitter of the transistor T ₇ is grounded, and the base is connected to the collector of the PNP type transistor T ₈ . The collector of the transistor T ₈ is
It is connected to the connection contact J ₆ through a resistor R ₁₈ , and the base is connected to the output end of the inverter N 36 through a resistor R ₁₉ . The input end of the inverter N36 is connected to the output end of the inverter N35. The base of the transistor T ₁₁ is connected to the output terminal of the inverter N37 through the resistor R ₂₁ , and the input terminal of the inverter N37 is connected to the output terminal of the NAND gate A47. The other input end of the NAND gate A47 is connected to the output end of the NAND gate A46 of the brake circuit.

Moving to FIG. 14B, the other input end of the NAND gate A48 is connected to the output end of the NAND gate A54, and the output end of the NAND gate A48 is connected to one input end of the NAND gate A49. . Also, Nand Gate A54
One and the other input terminals are connected to the output terminal A _o of the least significant bit and the output terminal G _{o of the} most significant bit of the BCD down counter 10.
Respectively connected to.

The decoder 30 in the motor drive device of this embodiment is
NAND gates A101 to A135 and inverters N101 to N138
Are connected and configured as shown in FIGS. 15 (A) and (B). And the NAND gates A104 and A109
16 is a signal for driving the electrodes for displaying the camera rewinding member set of the liquid crystal display 50 shown in FIG. 16 and the electrodes for returning the motor rewinding member rewinding member respectively, and the inverters N106 to N111 Is a signal for driving each electrode for displaying the motor drive device rewinding member set, film rewinding, rear lid opening, film loading, rear lid closing, and reset button pressing. The outputs of the inverters N116 to N125 are signals for driving the first digit of the electrodes for displaying the remaining number of frames of the liquid crystal display 50, and the outputs of the inverters N134 to N138 drive the second digit. It is a signal. Furthermore, the outputs of the NAND gates A126 to A128 are signals for driving the electrodes for dot display of the liquid crystal display 50, respectively.

As described above, the motor drive device having the film idling function of this embodiment is different from the motor drive device of the embodiment shown in FIGS. 1 (A) and 1 (B).

Next, the operation of this motor drive device will be described focusing on the differences from the operation of the motor drive device of the embodiment shown in FIGS. 1 (A) and 1 (B).

First, the initial state is the same as the case of the motor drive device of the embodiment shown in FIGS. 1 (A) and 1 (B) (FIG. 17 (A) (a) to (o)). And FIGS. 17 (B) (p) to (z) and (α)). When a compatible camera is attached, the model detection switch S ₁₅ remains on (see Fig. 17 (A) (e)), and when an incompatible camera is attached, the model detection switch S15 is detected. Switch S
₁₅ turns off. Hereinafter, unless otherwise specified, it is assumed that a compatible camera model is installed.

When the rear cover of the camera is opened to load the film from such an initial state, the rear cover switch S ₃ and the rear cover lock switch S ₁₄ are turned on (see FIGS. 17 (A) (c) and (d)). ) Since the "H" level reset signal is applied to the reset signal input terminal of each flip-flop circuit forming the binary counter BC3, the output of each flip-flop circuit becomes "L" level (Fig. 17). (A) and (g)), the output of the NAND gate A26 is at "L" level (see FIG. 17 (A) (i)), and the output of the NAND gate A27 is at "H" level (FIG. 17 (A) (j)). (See). Also, the output of the inverter N24 becomes "H" level (Fig. 17 (A)).
(See (o)), the "H" level reset signal is applied to the reset signal input terminal of each flip-flop circuit forming the binary counter BC4, and the binary counter BC4 is reset.

After the film is loaded in the cassette, closing the rear cover, rear cover switch S ₃ is opened (FIG. 17 (A) (C) see)
At the same time, the rear lid lock switch S ₁₄ is opened slightly later (see FIGS. 17 (A) and (d)). Then the inverter
Returning to N24 outputs "L" level (FIG. 17 (A) (o) refer), the binary counter BC4 starts counting of the pulse signal of the frequency f _4. Then, when the output of the binary counter BC4 is inverted to the "H" level after a lapse of a predetermined time, the inputs of the NAND gate A39 are both set to the "H" level, so that the gate A39 is also turned on.
Output becomes "L" level (see FIG. 17 (B) (u)). Therefore, the output of the NAND gate A41 becomes "H" level (see FIG. 17 (B) (v)), the output of the inverter N28 becomes "L" level (see FIG. 17 (B) (w)), and the NAND gate A29 becomes It is reset (see FIG. 17 (A) (l)). Then, the output of the NAND gate A28 is at "L" level (see FIG. 17 (A) (k)), and the output of the inverter N23 is at "H" level (see FIG. 17 (A) (m)).
Since the output of A35 is also at "H" level (see FIGS. 17 (B) and (q)), the output of NAND gate A42 is at "L" level (17th level).
(See FIGS. (B) and (x)). The output of the NAND gate A42 is input to the NAND gate A15 via the NAND gates A9 and A8, and the output of the gate A15 becomes "L" level (see FIG. 17 (B) (y)). Therefore, Nand Gate A17
Output "H" level (FIG. 17 (B) (alpha) refer), the output of the inverter N32 becomes "L" level, the transistor T ₃ through T ₆ is turned on, current is conducted to the driving motor M1 Is
The motor M1 starts the rotation for film idling.
After the output of the NAND gate A36 is inverted, the binary counter BC5
Counts the pulse signal of frequency f ₅ and when a predetermined time elapses, the output of the counter BC 5 is inverted and the NAND gate A 39
The output of is at "H" level and the output of the NAND gate A41 is at "L" level (see FIGS. 17 (B) (u) and (v)).
Return to the initial state.

After the drive motor M1 is rotated, shutter release and film winding are performed twice each, and the motor drive device stops after the film is fed by two frames, as shown in FIGS. 1 (A) and 1 (B). This is similar to the case of the motor drive device shown in FIG.

The above description of the jump feed operation is the operation when a compatible model camera is attached to the motor drive device, but when a non-compatible model camera is attached, the model detection switch S ₁₅ turns off and the NAND gate Since the output of A34 is "H" level and the output of the inverter N24 is "L" level, 2
The circuit including the binary counters BC4 and SC5 does not work, and NAND gate A
The outputs of 35 and A39 remain at "H" level. Therefore, the output of NAND gate A26 and A28 is always "H" level, so remains the output of NAND gate A42 is at the "H" level, the rear cover switch S ₃ by opening and closing the rear cover, the rear lid lock switch S ₁₄ Even if it is opened / closed, the binary counter BC3 is reset, but the output of the NAND gate A42 is in the same state as that at the end of the idling. Therefore, it is necessary to press the release button and close the release switch S ₁ in order to feed the film in this state. When the release switch S ₁ is closed, the film is idly fed in substantially the same manner as the film idling by the rear lid closing signal.

By the way, when a film of a compatible model is mounted, the dot display is performed on the liquid crystal display 50 (see FIG. 16) when the film is fed. That is, the rear cover switch S _3, by opening the rear lid lock switch S _14, to empty the feed of the second frame output of the NAND gate A26 (FIG. 18 (A) (g) refer) is "L"
And the output of each flip-flop circuit that forms a binary counter BC3 with this output (FIG. 18 (A) (c),
(See (d)) and the logical operation in the decoder 30
Until the first frame jump feed is completed, dots 2 and 3 are displayed as shown in FIG. 19 (B).
(See FIGS. 18 (A), (n), and (o)) Until the second frame is completed, as shown in FIG. 19 (c), only the dot 3 is displayed (FIG. 18). (A) and (o)), and when the blank feeding is completed, all the dots are displayed as shown in FIG. 19 (D). If a non-conforming camera is attached, the output of the NAND gate A26 will remain at the "H" level (see Fig. 18 (B) (g)).
The output of the inverter N129 is at "L" level (Fig. 18 (B)).
(See (k)), and the outputs of the NAND gates A124 and A125 become "H" level (see (B) (l) and (m) in FIG. 18).
The potential of the output and connection contact J ₁₂ of the NAND gate A54 is "H"
Under the condition of being a level, NAND gates A126 to A1
All 28 outputs are at "L" level (Fig. 18 (B) (n),
(See (c) and (p)), and dot display is not performed as shown in FIG. 19 (D).

Further, the motor drive device of the present embodiment performs the same operation as that of the motor drive device shown in FIGS. And 1
When the number of remaining frames, which is the content of the BCD down counter 10, becomes zero due to frame shooting or continuous shooting, the inverter N116 and the inverter N116 in the decoder 30 (see FIGS. 15A and 15B) are displayed.
The output of NAND gate A130 becomes "L" level because both outputs of N134 become "H" level.
Output becomes "H" level. If the attached camera is a compatible model, the model detection switch S ₁₅ remains on and the signal input to the NAND gate A102 is at "H" level, so the output of the NAND gate A104 becomes "H" level and the LCD display On the container 50 (see FIG. 16), pictograms of the camera rewinding member set are displayed. Next, when the R clutch, which is the camera rewinding member, is set, the R clutch switch S ₁₇ is turned on, the output of the inverter N106 becomes "H" level, and the pictogram of the motor rewinding member rewinding member set is displayed. Be done. When the R lever, which is the motor drive device rewinding member, is set before the R clutch is set, the output of the NAND gate A103 becomes "L" level, the output of the NAND gate A104 becomes "H" level, and the camera winding The pictograms of the return member set are displayed first. When both the R clutch and the R lever are set, the film is rewound, as will be described later, and the fact is displayed on the liquid crystal display 50 by pictograms based on the output of the inverter N107. . Further, if the mounted camera is a non-conforming model, the model detection switch S ₁₅ is opened, so the opening / closing signals of the rear cover lock switch S ₁₄ , R lever switch S ₁₆ , R clutch switch S _17, etc. The drive device is not transmitted to the alligator, the output of the inverter N111 becomes "H" level, and the reset button is pressed.

By the way, the BCD down counter 10 shown in FIG. 14 (B) is a 42-ary counter, and when the content of the counter 10 is "0" to "40", it represents the number of frames of the film, When the content of the counter 10 is "41", the no-count mode is set. That is, when the content of the BCD down counter 10 becomes "41", the output terminals A _o and G _o output "H" level, the output of the NAND gate A54 is "L" level, and the decoder 30 ( Since the output of the NAND gate A129 in FIG. 15 (A) and (B) is at "H" level and the output of the inverter N130 is at "L" level, the outputs of the NAND gates A114 to A123 and A131 to A135 are all at "H". "Level, all outputs of inverters N116 to N125 and N134 to N138 are" L "
As the level is reached, the number of frames is not displayed on the liquid crystal display 50. Further, since the "L" level output of the NAND gate A54 is applied to the other input end of the NAND gate A48, the count pulse is not input to the BCD down counter 10. Further, since the outputs of the NAND gates A126 to A128 are all at the “H” level, as shown in FIG.
Dot 2 and dot 3 are displayed.

Also, in the case of no count mode in which the long film back is attached to the camera, the “L” level potential at the other _ends of the long detection switches S _13a and S _13b is the NAND gate of the decoder 30.
Since it is applied to one input terminal of A129 and the output of NAND gate A129 is always at "H" level, the liquid crystal display is the same as when the contents of 3CD down counter 10 becomes "41".
At 50, the number of pieces is not displayed. Also, Nand Gate A1
Since the outputs of 26 to A128 are all at the "H" level, dot 1, dot 2 and dot 3 are displayed (see FIG. 19 (A)).

When the R clutch and the R lever are both set according to the instruction on the liquid crystal display 50 after the film is taken, the R clutch switch S ₁₇ and the R lever switch S ₁₆ are set.
Are turned on, the output of the inverter N29 is “L”.
When the output of the NAND gate A15 becomes "H" level, the film winding becomes impossible. Also, if a film is loaded in the camera, the film switch
Since S ₁₈ is open, the output of NAND gate A43 is “L”.
Level, and with the transistor T _8, T ₇ is turned through an inverter N35, N36, NAND gate A47, transistor T _11, T ₉ is turned on through inverter N37. Thus the driving motor M1 current flows through the transistor T ₇ and T _9, the motor M1 is rotated in the opposite direction to that during the winding of the film. Therefore, the film is rewound. During the film rewinding, the inverter N1 of the decoder 30
The "H" level output is output from 07, and the liquid crystal display 50 displays the pictogram during film rewinding.

Then, when the rewinding of the film is completed, the film switch S ₁₈ is turned on, the output of the inverter N31 becomes “L” level, and the output of the NAND gate A43 becomes “H” level, so that the transistors T ₈ , T ₇ and T _11, T ₉ are turned off, respectively. Therefore, when the drive motor M1 is de-energized and the motor M1 is stopped, the rewinding of the film automatically ends. Further, since the output of the inverter N107 of the decoder 30 is inverted to the “L” level, the display on the liquid crystal display 50 during film rewinding is erased.

As described above, according to the present invention, it is possible to provide a motor drive device having a convenient film idling function which is very convenient to use, and which solves the conventional drawbacks described at the beginning of the specification.

[Brief description of drawings]

1 (A) and 1 (B) are electric circuit diagrams of a motor drive device having a film idling function, showing an embodiment of the present invention, FIGS. 2 (a) to (j) and FIG. (A) to (j) are
FIGS. 4A and 4B are time charts showing the output states of the respective parts of the shutter release signal holding circuit provided in the motor drive device shown in FIGS. 1A and 1B, and FIGS. 1 (A),
FIG. 5 (a) to FIG. 5 (n) are electric circuit diagrams of a main part showing open / closed states of switches when a long film back is attached to the motor drive device shown in FIG. ) And (B) are time charts showing output states when the number of frames is set in the motor drive device, and FIG. 6 is a power supply circuit in the motor drive device shown in FIGS. 1 (A) and (B). Fig. 7 (A) (a)-(n) and Fig. 7 (B) (o) showing an electric circuit diagram showing the system.
~ (Z), (α), (β) are the same as in Fig. 1 (A),
FIG. 7 (C) (a) to (n) and FIG. 7 (D) are time charts showing the output states of the motor drive device shown in FIG. (O)
8A to 8U are time charts showing the output states of the motor drive device shown in FIGS. 1A and 1B when the film is idly fed in the continuous shooting mode, and FIGS. (N) is a time chart showing the output state at the time of single frame shooting in the motor drive device shown in FIGS. 1 (A) and 1 (B), and FIGS. 1A and 1B are time charts showing output states when the counter is subtracted in the motor drive device shown in FIGS. 1A and 1B, and FIGS. FIGS. 11 (a) to 11 (q) are time charts showing output states during continuous shooting in the motor drive device shown in FIG. At the time of automatic stop due to the end of the film Time charts showing the respective states, FIGS. 12 (a) to 12 (h) are outputs of the motor drive device shown in FIGS. 1 (A) and 1 (B) during idling with the rear lid open. FIG. 13 is a time chart showing the state, FIG. 13 is an electrical circuit diagram of a main part showing a case where an unusable camera is attached to the motor drive device shown in FIGS. 1 (A) and 1 (B), FIG. A) and (B) show another embodiment of the present invention,
An electric circuit diagram of a motor drive device having a film idling function, FIGS. 15 (A) and 15 (B) are electric circuit diagrams showing a more detailed configuration of the decoder shown in FIG. 14 (B). FIG. 16 is a front view showing an electrode structure of the liquid crystal display shown in FIG. 14 (B), FIGS. 17 (A) (a) to (o) and FIGS. 17 (B) (p).
˜ (z) and (α) are time charts showing the output states of the motor drive device shown in FIGS. 14 (A) and 14 (B) when the film is fed by the rear lid closing signal, respectively. (A) (a)-(p) and FIG. 18 (B) (a)
Outputs for dot display when a compatible model camera and a non-compatible model are mounted on the motor drive device shown in FIGS. 14 (A) and 14 (B). 19 (A) to 19 (D) are time charts showing respective states, and are front views of relevant parts showing the manner of dot display or dot non-display in the liquid crystal display shown in FIG. 10 ... BCD down counter (first counting means) 13 ... Motor control circuit (motor control means) 20 ... D latch train (storage means) A16 ... NAND gate (motor control means) A26 ... NAND gate A55 ... NAND gate (discrimination means) BC3 ... binary counter (second counting means) M1 ... drive motor S ₅ ... reset switch (reset means)

Claims (1)

[Scope of utility model registration request] 1. A setting means for manually setting an arbitrary number of film frames, a storage means for storing the number of film frames set by the setting means, and a one-frame signal corresponding to one film feed. The signal generating means, the first counting means for counting the one frame signal in order to detect the number of film frames photographed, the stored number of film frames and the counted number of film frames photographed are Discriminating means for discriminating that a predetermined relationship has been established, winding control means for stopping the automatic winding based on the output of this discriminating means, and the above-mentioned one frame in order to detect the number of frames of the film that have been fed in an idle manner. Second counting means for counting the signals, idle feed control means for controlling the idle feed of the film until the count value by the second counting means reaches a predetermined number of frames, and the second counting means The number of pieces is reset A motor drive device having a film idling function, which comprises a resetting means for forcibly manually resetting the value of the first counting means to the stored number of frames. .