JPH064330A - Test system - Google Patents

Abstract

PURPOSE:To provide the test system which can efficiently execute tests over a wide range with satisfactory reproducivility. CONSTITUTION:A tester 10 is composed of a parameter storage part 11, parameter setting part 17 to prepare test object instructions or various limit conditions based on pseudo random numbers and to store them in the parameter storage part 11, instruction sequence start part 14 to transfer test instruction sequences from an instruction sequence generation part 12 and output data from a data generation part 13 to an information processor 20 and to execute them, simulator part 15 to perform simulation based on the output data of the instruction sequence generation part 12 and the output data of the data generation part 13, executed result comparison part 16 to compare the executed result of the information processor 20 with the simulation result of the simulator part 15, and error information output part 18 to output error information when the compared result shows non-coincidence at this executed result comparison part 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test system,
In particular, it relates to a test system for information processing equipment.

[0002]

2. Description of the Related Art A conventional information processing system test system is
The operator has to manually set the parameters for generating the test instruction sequence of the information processing apparatus. In addition, when changing the parameter, the operator once stopped the test system, changed the parameter, and restarted the test system.

[0003]

However, in the above-mentioned conventional example, the parameter setting at the time of generating the test instruction sequence must be manually performed, and the parameter must be manually changed. However, there are inconveniences that it takes a lot of time to operate the system and necessary and sufficient tests cannot be performed due to an error or imbalance in parameter setting.

[0004]

SUMMARY OF THE INVENTION The object of the present invention is to improve the disadvantages of the conventional example, and in particular, to perform the test efficiently while automatically changing the parameters when the test instruction sequence is generated randomly. It is to provide a test system capable of performing a wide range of tests with good reproducibility.

[0005]

Therefore, according to the present invention, a test apparatus creates a test target instruction and various constraint conditions based on a pseudo random number and a parameter storage unit that stores a test target instruction and various constraint conditions. A parameter setting unit to be stored in the parameter storage unit, an instruction sequence generation unit to create a test instruction sequence by referring to the parameter storage unit based on a pseudo random number, and a data generation unit to create data based on the pseudo random number, An instruction sequence starting unit that transfers the test instruction sequence created by the instruction sequence generation unit and the data created by the data generation unit to the information processing device for execution, and a test instruction sequence created by the instruction sequence generation unit and a data generation unit The execution result ratio that compares the execution result in the information processing device and the simulation result in the simulator part with the simulator part that performs the simulation based on the data created in And parts, it adopts a configuration that includes an error information output unit for outputting error information when the comparison result in the execution result comparison unit does not match. This aims to achieve the above-mentioned object.

[0006]

When the test apparatus is activated, the parameter setting unit sets the test target instruction and various constraint conditions in the parameter storage unit by using the pseudo random number. The instruction sequence generation unit refers to the parameter storage unit by using a pseudo random number, selects a test instruction having a predetermined number of instructions, and generates an instruction sequence that matches each constraint condition. The data generation unit uses pseudo-random numbers to generate data used in an instruction sequence.

The instruction sequence activation unit transfers the instruction sequence generated by the instruction sequence generation unit and the data generated by the data generation unit to the information processing device and activates it. The simulator section performs simulation using the same instruction sequence and data transferred to the information processing apparatus, and generates an expected value of execution result.

When the execution in the information processing device is completed, the execution result comparison unit compares the execution result in the information processing device with the simulation result in the simulator unit. If the comparison result does not match, the error information including the instruction string and the initial value of the data and the execution result is output to the list via the error information output unit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The embodiment shown in FIG. 1 includes an information processing device 20 that performs various types of information processing, and a test device 10 that tests the information processing device 20.

Here, as shown in FIG. 2, the test apparatus 10 includes a parameter storage unit 1 that stores instructions to be tested, register constraint conditions, and memory operand constraint conditions.
1, a parameter setting unit 17 that stores an instruction to be tested, a register constraint condition, and a memory operand constraint condition in the parameter storage unit 11 based on the pseudo random number; and a test by referring to the parameter storage unit 11 based on the pseudo random number. An instruction sequence generation unit 12 that generates an instruction sequence, a data generation unit 13 that generates data based on a pseudo random number, and an instruction sequence generation unit 12
An instruction sequence starting unit 14 for transferring the test instruction sequence created in step 1 and the data produced in the data generating unit 13 to the information processing device 20 for execution, and a test instruction sequence created in the instruction sequence generating unit 12 and a data producing unit A simulator unit 15 that performs a simulation based on the data created in 13; an execution result comparison unit 16 that compares the execution result of the information processing device 20 with the simulation result of the simulator unit 15;
An error information output unit 18 is provided for outputting error information when the comparison results of the execution result comparison unit 16 do not match.

The parameter storage unit 11 also stores an instruction table unit 11A for storing instructions to be tested and a register constraint for storing register constraint conditions for selecting from which range a register used by the instruction to be tested can be selected. A condition part 11B and a memory operand constraint condition part 11C for storing a restriction on a start boundary address on the memory operand used in the instruction to be tested, a restriction on its length, and a restriction on an allocation position on the memory. It has.

The information processing device 20 comprises a main memory device 22 for storing instruction sequences and data, and an arithmetic processing device 21 for executing an instruction sequence using the data stored in the main memory device 22. ing.

Although not shown, the test apparatus 10 has an external storage device for storing various processing programs and data, and an input / output for an operator to start the test apparatus 10 and display a result. A device, a printer for outputting error information, and the like are provided side by side.

Next, the first operation of this embodiment will be described with reference to the flowchart of FIG.

.. When the test apparatus 10 is activated, the parameter setting unit 17 sets the test target instruction in the instruction table unit 11A using a pseudo random number, and sets the register constraint condition, that is, the selectable range of the register used in the test target instruction as the register constraint. The memory operand constraint condition is set in the condition unit 11B, that is, the start boundary address limit on the memory for the memory operand used in the test target instruction, its length limit, and the allocation position limit on the memory are specified. Set to (Step 3 in FIG. 3)
1). At the same time, start the timer.

.. The instruction sequence generation unit 12 selects a test instruction having a predetermined number of instructions with reference to the instruction table unit 11A, the register constraint condition unit 11B, and the memory operand constraint condition unit 11C by using a pseudo random number, An instruction string is generated so as to meet the memory operand constraint condition (step 32 in FIG. 3).

.. The data generator 13 generates data to be used in the instruction sequence by using the pseudo random number (step 33 in FIG. 3).

.. The instruction sequence activation unit 14 includes the instruction sequence generation unit 1
The instruction sequence generated in 2 and the data generated in the data generation unit 13 are transferred to the information processing device 20.

The information processing device 20 stores the transferred instruction sequence and data in the main storage device 22.

The instruction sequence activation unit 14 activates the information processing device 20.

The information processing device 20 stores an instruction sequence from the main storage device 22 in a register of the arithmetic processing device 21, and the arithmetic processing device 21 executes the instruction sequence.

When the execution is completed, the instruction sequence starting unit 14
Is a register of the arithmetic processing unit 22 and a main storage unit 23.
The execution result stored in is read and saved (step 34 in FIG. 3).

.. The simulator unit 15 uses the same instruction sequence and data transferred to the information processing device 20,
A simulation is performed and an expected value of the execution result is generated (step 35 in FIG. 3).

[0024]. The execution result comparison unit 16 compares the execution result of the information processing device 20 with the simulation result of the simulator unit 15 (step 36 in FIG. 3).

If the comparison results are in agreement, nothing is done and the process proceeds to the following (step 39 in FIG. 3). If the comparison results do not match, the error information including the instruction string and the initial value of the data and the execution result is output to the list via the error information output unit 18 (step 38 in FIG. 3), and the following (step 39 in FIG. 3). ) Processing.

.. The timer is checked (step 39 in FIG. 3), and if the preset time has elapsed, the process returns to the above process (step 31 in FIG. 3). If the preset time has not elapsed, the process returns to the above process (step 32 in FIG. 3).

In this way, the above processing steps are repeatedly executed until the operator instructs the stop.

Next, the second operation of this embodiment will be described with reference to the flowchart of FIG.

.. When the test apparatus 10 is activated, the parameter setting unit 17 sets the test target instruction in the instruction table unit 11A using a pseudo random number, and sets the register constraint condition, that is, the selectable range of the register used in the test target instruction as the register constraint. The memory operand constraint condition is set in the condition unit 11B, that is, the start boundary address limit on the memory for the memory operand used in the test target instruction, its length limit, and the allocation position limit on the memory are specified. Set to (Step 4 in FIG. 4)
1). At the same time, the comparison counter is reset.

.. The instruction sequence generation unit 12 selects a test instruction of a predetermined number of instructions by referring to the instruction table unit 11A, the register constraint condition unit 11B, and the memory operand constraint condition unit 11C using the pseudo random number, An instruction sequence is generated so as to meet the memory operand constraint condition (step 42 in FIG. 4).

.. The data generator 13 generates data to be used in the instruction sequence by using the pseudo random number (step 43 in FIG. 4).

.. The instruction sequence activation unit 14 includes the instruction sequence generation unit 1
The instruction sequence generated in 2 and the data generated in the data generation unit 13 are transferred to the information processing device 20.

The information processing device 20 stores the transferred instruction sequence and data in the main storage device 22.

The instruction sequence activation unit 14 activates the information processing device 20.

The information processing apparatus 20 stores the instruction sequence from the main memory 22 in the register of the arithmetic processing unit 21, and the arithmetic processing unit 21 executes the instruction sequence.

When the execution is completed, the instruction sequence starting unit 14
Is a register of the arithmetic processing unit 22 and a main storage unit 23.
The execution result stored in is stored and saved (step 44 in FIG. 4).

.. The simulator unit 15 uses the same instruction sequence and data transferred to the information processing device 20,
A simulation is performed and an expected value of the execution result is generated (step 45 in FIG. 4).

.. The execution result comparison unit 16 compares the execution result of the information processing device 20 with the simulation result of the simulator unit 15 (step 46 in FIG. 4). Then, the comparison counter is incremented by one.

If the comparison results are in agreement, nothing is done and the process proceeds to the following process (step 49 in FIG. 4). If the comparison result does not match, the error information including the instruction string and the initial value of the data and the execution result is output to the list via the error information output unit 18 (step 48 in FIG. 4), and the following process (see FIG. 4) is performed. Proceed to step 49).

.. The comparison counter is checked (step 49 in FIG. 4), and if the preset number of comparisons has been reached, the above process (step 4 in FIG. 4) is performed.
Return to 1). If the preset number of comparisons has not been reached, the process returns to the above process (step 42 in FIG. 4).

Next, the third operation of this embodiment will be described with reference to the flowchart of FIG.

.. When the test apparatus 10 is activated, the parameter setting unit 17 sets the test target instruction in the instruction table unit 11A using a pseudo random number, and sets the register constraint condition, that is, the register selectable range of the register used in the test target instruction. The memory operand constraint condition is set in the condition unit 11B, that is, the start boundary address limit on the memory for the memory operand used in the test target instruction, its length limit, and the allocation position limit on the memory are specified. Set to (Step 5 in FIG. 5)
1). At the same time, start the timer.

.. The instruction sequence generation unit 12 selects a test instruction of a predetermined number of instructions by referring to the instruction table unit 11A, the register constraint condition unit 11B, and the memory operand constraint condition unit 11C using the pseudo random number, An instruction string is generated so as to meet the memory operand constraint condition (step 52 in FIG. 5).

.. The data generator 13 uses pseudo-random numbers to generate data used in the instruction sequence (step 53 in FIG. 5).

.. The instruction sequence activation unit 14 includes the instruction sequence generation unit 1
The instruction sequence generated in 2 and the data generated in the data generation unit 13 are transferred to the information processing device 20.

The information processing device 20 stores the transferred instruction sequence and data in the main storage device 22.

The instruction sequence activation unit 14 activates the information processing device 20.

The information processing apparatus 20 stores the instruction sequence from the main memory 22 in the register of the arithmetic processing unit 21, and the arithmetic processing unit 21 executes the instruction sequence.

When the execution is completed, the instruction sequence starting unit 14
Is a register of the arithmetic processing unit 22 and a main storage unit 23.
The execution result stored in is read and saved (step 54 in FIG. 5).

.. The simulator unit 15 uses the same instruction sequence and data transferred to the information processing device 20,
A simulation is performed and an expected value of the execution result is generated (step 55 in FIG. 5).

.. The execution result comparison unit 16 compares the execution result of the information processing device 20 with the simulation result of the simulator unit 15 (step 56 in FIG. 5).

If the comparison results are in agreement, nothing is done and the process proceeds to the following (step 59 in FIG. 5). If the comparison result does not match, the error information including the instruction string and the initial value of the data and the execution result is output to the list via the error information output unit 18 (step 58 in FIG. 5), and the above-described processing (in FIG. 5) Return to step 51).

.. The timer is checked (step 59 in FIG. 5), and if the preset time has elapsed, the process returns to the above process (step 51 in FIG. 5). If the preset time has not elapsed, the process returns to the above process (step 52 in FIG. 5).

The processing of each unit in this embodiment can be realized by software. In that case, the processing program is stored in the external storage device provided in the test apparatus 10 and the above processing is performed.

[0055]

Since the present invention is constructed and functions as described above, according to this, it is possible to automatically and randomly execute a parameter when generating a test instruction sequence, which is effective. It is possible to provide an unprecedented excellent test system capable of performing a wide range of tests with good reproducibility.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a detailed configuration of a test apparatus in the embodiment of FIG.

FIG. 3 is a flowchart for explaining the first operation of the present invention.

FIG. 4 is a flowchart for explaining a second operation of the present invention.

FIG. 5 is a flowchart for explaining a third operation of the present invention.

[Explanation of symbols]

 10 test device 11 parameter storage unit 12 instruction sequence generation unit 13 data generation unit 14 instruction sequence activation unit 15 simulator unit 16 execution result comparison unit 17 parameter setting unit 18 error information output unit 20 information processing device 21 arithmetic processing unit 22 main storage device

Claims (2)

[Claims] 1. A test system comprising an information processing device for performing various information processing and a test device for testing the information processing device, wherein the test device stores a test target instruction and various constraint conditions. A parameter storage unit, a parameter setting unit that creates a test target instruction and various constraint conditions based on a pseudo random number and stores them in the parameter storage unit, and a test instruction sequence by referring to the parameter storage unit based on a pseudo random number. An instruction sequence generation unit to generate, a data generation unit to generate data based on a pseudo random number, a test instruction sequence generated by the instruction sequence generation unit and data generated by the data generation unit to the information processing device. A simulation is performed based on the instruction sequence activation unit that is transferred and executed, the test instruction sequence created by the instruction sequence generation unit, and the data created by the data generation unit. An error information is output when the comparison result in the mutator section, the execution result comparison section that compares the execution result in the information processing device with the simulation result in the simulator section, and the comparison result in this execution result comparison section A test system equipped with an error information output section. 2. The parameter storage unit stores an instruction table unit that stores a test target instruction, a register constraint condition unit that stores a selectable range of a register used by the test target instruction, and a memory operand used by the test target instruction. 3. A memory operand constraint condition part for storing a start boundary address limit on the memory, its length limit, and allocation position limit on the memory.
Test system described.