JPH0642551B2 - Non-volatile semiconductor memory - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory having a write load circuit with improved write characteristics.

(Prior Art) A non-volatile semiconductor memory device, particularly an EPROM using a double-gate type non-volatile memory element having a floating gate structure as a memory cell, can rewrite data. It is used in various systems including the beginning. The double-gate type non-volatile memory device has two gate electrodes, a floating gate and a control gate, as is well known. Then, if electrons are injected into the floating gate, its threshold voltage is increased, so that a high level voltage is applied to the control gate,
For example, even if 5V is applied, the memory element does not conduct. On the other hand, if electrons are not injected into the floating gate and it is in a neutral state, the threshold voltage remains at its original low value, and if a high level voltage is applied to the control gate, the memory element becomes conductive. In this way, the conduction / non-conduction state of the memory element when a high level voltage is applied to the control gate is changed to “1” or “0” of data.
The data is stored by corresponding to. Also, the normal power supply voltage (5V) is applied to the floating gate and drain.
Electrons are injected by applying a voltage sufficiently higher than the above, for example, a voltage of 12.5V to 21V. By applying such a high voltage, the impact ionization (Impact Ionizat
ion) is generated, and the electron generated by this, and the electron of the hole pair are injected into the floating gate. Since the electrons once injected into the floating gate remain in the floating gate unless the erase operation is performed, the stored data is retained in a non-volatile manner.

FIG. 3 is a circuit diagram showing a schematic configuration of a general EPROM using the above nonvolatile memory element as a memory cell. In the figure, WL1 to WLm are row decoders 1
01 is the row line to which the decode output from
L1 to COLn are column selection lines to which the decode output from the column decoder 102 is supplied. The above n column selection lines CO
L1 to COLn include n column selection transistors C1 to C
n gates are connected, and these column selection transistors C1 to Cn correspond to the corresponding column selection lines COL1 to COL1.
It is driven by the signal of COLn. One end of each of the column selection transistors C1 to Cn is commonly connected to a node 103, and the other end thereof is connected to each of n column lines BL1 to BLn provided so as to intersect with the row lines WL1 to WLm. Has been done. Further, memory cells M11 to Mmn composed of double gate type MOS transistors having a floating gate and a control gate structure are provided at positions where the row lines WL1 to WLm intersect the column lines BL1 to BLn. . The control gates of the memory cells M11 to Mmn are connected to the corresponding row lines WL1 to WLm, the drains are connected to the corresponding column lines BL1 to BLn, and all the sources are applied to a predetermined voltage, for example, 0V ground. Voltage VS
It is connected to the. The source of the MOS transistor 104 is connected to the node 103. The drain of the transistor 104 is connected to the external program voltage VP and is connected to the output node of the gate data write circuit 105. The data writing circuit 105 is
The write data DIN set to the VS voltage or the high voltage is output according to the data "1" and "0" to be programmed. Further, the sense amplifier circuit 1 is connected to the node 103.
06 is connected to the node 10 when reading data.
The data corresponding to the potential of 3 is the sense amplifier circuit 106.
Detected in.

In the EPROM having the above-mentioned configuration, when data “0” is written in one memory cell, for example, M11, the signal DIN output from the data write circuit 105 is set to a high voltage, and the decode output of the column decoder 102 outputs the column select line. COL1 is brought to a high voltage. The high voltage on DIN causes the transistor 104 to conduct, and the column select line C
Due to the high voltage of OL1, the column selection transistor C
1 becomes conductive, and the external program voltage VP is output to the column line BL1. At this time, the decode output of the row decoder 101 sets the row line WL1 to a high voltage, and the high voltage is applied to both the control gate and the drain of the selected memory cell M11. As a result, electrons due to impact ionization as described above are injected into the floating gate of the memory cell M11, and data "0" is written. On the other hand, when data “1” is written in the memory cell M11, the DIN output from the data write circuit 105 becomes O.
It becomes VS of V. At this time, the transistor 104 is turned off, so that the external program voltage VP is not output to the column line BL1. Therefore, the selected memory cell M1
The floating gate of 1 keeps the neutral state.

(Problems to be solved by the invention) By the way, recently, in order to achieve high integration, the nonvolatile memory element as described above has been miniaturized, and with this miniaturization,
The external program voltage VP is also lowered. Therefore, it is common to write data in the avalanche region, which has a high program efficiency, in consideration of shortening the program time and operating margin.

FIG. 4 (a) shows the write circuit of one memory cell M11 of FIG. 3 as a representative, and FIG. 4 (b) shows E of FIG.
In the PROM, a high voltage is applied to the gates of the MOS transistor 104 and the MOS transistor C1 and the high voltage is applied to the memory cell M1.
1 programming characteristics of the memory cell M11 when a high voltage for programming is applied to the control gate of the memory cell 1 (drain voltage VD
-Drain current ID characteristic). Fig. 4 (b)
The curve a in the middle shows the drain current dependence of the drain voltage of the memory cell M11, the straight line d shows the load characteristics of the load circuit consisting of the MOS transistor 104 and the MOS transistor C1 under the above conditions, and the writing at this time is the curve a. The drain voltage and the drain current are generated at the point A where the straight line d intersects. By the way, it is known that the channel length of the memory cell M11 always varies within a certain range in the manufacturing process. The drain current dependency of the drain voltage of the memory cell M11 when the channel length becomes longer than the specified value becomes a curve b, and when the channel length becomes shorter than the specified value, it becomes a curve c. The operating point at the time of writing when the channel length becomes long is the point B where the curve b and the straight line d intersect. Therefore, in this case, writing in the avalanche region becomes difficult and the write margin is reduced. On the other hand, the operating point at the time of writing when the channel length becomes short is the point C where the curve c and the straight line d intersect. In this case, writing is sufficiently performed in the avalanche region, but the drain current increases significantly.

Operates in saturation region like transistor 104, C1
The drain current ID of the MOSFET can be expressed by the following equation (1).

As can be seen from the equation (1), the drain current ID is the difference between the gate voltage VG and the threshold value VTH, that is, "VG-V".
Since it changes squared with respect to the change of “TH”, the slope becomes steeper, and if the characteristic lines a and d are crossed at the point A in FIG. 4, the curve b and c of the memory cell current changes. , The intersection changes greatly with B and C. In addition to the above squared characteristic of the current, the point at which the current flows is the threshold voltage VTH.
Since it becomes lower than VP by an amount corresponding to the threshold voltage, if an attempt is made to cross at the point A, it is more disadvantageous than that from VP by the threshold voltage VTH, that is, the slope of the load line d becomes steeper and the memory cell characteristic There is a drawback that the writing characteristics greatly vary depending on the change.

Therefore, in order to perform stable writing even when the channel lengths of the memory cells vary and to make the drain current value almost constant, it is necessary to make the operating points at the time of writing almost the same. Therefore, for this purpose, the slope of the load characteristic may be reduced, for example, the straight line e.

The present invention has been made in view of the above circumstances, and by making the slope of the load line small and linear, the nonvolatile property is less likely to deteriorate the write property with respect to the process property variation of the memory cell. An object is to provide a semiconductor memory.

[Configuration of the Invention] (Means and Actions for Solving Problems) The present invention relates to a power supply, a nonvolatile memory cell, and at least a gate connected between the power supply and the nonvolatile memory cell for input data. A load transistor controlled by
A wiring layer that is connected in series to the load transistor between the power supply and the memory cell, is formed of polysilicon or a diffusion layer, and has a resistance value larger than the on-resistance value of the load transistor. This is the first feature. The present invention also provides a power supply, a non-volatile memory cell, a load transistor connected between the power supply and the non-volatile memory cell, at least a gate of which is controlled by input data, and between the power supply and the memory cell. A plurality of write circuits each having a wiring layer connected in series with the load transistor and formed of polysilicon or a diffusion layer and having a resistance value larger than the ON resistance value of the load transistor. A second feature is that the wiring layer is arranged in the field region between the column select transistors provided between the cells. That is, in the nonvolatile semiconductor memory of the present invention, the load line is not a MOSFET whose current changes by the square of the change of "VG-VTH" as in the above equation (1), but a resistor made of polysilicon or a diffusion layer. The object is achieved by making the inclination small and linear as determined by. Further, by providing the wiring layer in the field region between the column selection transistors, it is possible to prevent an increase in area due to the installation of the wiring layer.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a program (write) circuit diagram of the same embodiment. However, these are examples of cases corresponding to the above-mentioned conventional ones, and therefore, corresponding parts will be denoted by the same reference numerals and description thereof will be omitted. Then, the characteristic points will be explained. In FIG. 1 (a), a resistor R, which is an essential part of the present invention, is inserted in series between the power supply VP and the load transistor 104, and in FIG. 1 (b), a resistor R is connected between the transistor 104 and the column selection transistor C1. R is inserted in series, and a resistor R is inserted in series between the memory cell BL1 and the column selection transistor C1 in the same figure (c).

FIG. 2 (a) is a pattern plan view of a main part of a non-volatile memory formed by using the above program circuit, and FIG. 2 (b) is the same figure (a).
2 is a cross-sectional view taken along the line aa ′ in FIG. 1, 1 is a semiconductor substrate, 2 is a source or drain of a column selection transistor, 3 is a gate electrode wiring, and 4 is a field insulating film. Fig. 2 (a)
The circuit forming the pattern is shown in the case of using FIGS. 1B and 1C, and the polysilicon layer is used as the resistor R, but it may be a diffusion layer. Wiring contact 11
Aluminum is used for the wirings 12 to 14, 103, etc. connected to the gate electrodes, and polysilicon is used for the gate electrode 3.

As described above, in this embodiment, the load line of FIG.
As in the equation (1), the resistance R made of polysilicon or a diffusion layer is used instead of the MOSFET in which the current changes squared with respect to the change of "VG-VTH". That is, the first
As shown in FIGS. (A), (b) and (c), a resistor R is inserted in series between the power supply VP and the drain of the memory cell, and the resistor R
Is set so that the load line is decided dominantly. Then, the load line can be set to a value close to the straight line e in FIG. 4 (b). However, it is not necessary to completely determine the load line with the resistance R, and the resistance R
It is only necessary to reduce the characteristic that the current ID changes in the square with respect to the change of "VG-VTH" of the MOSFET. Therefore, it is effective only to compare the load resistance of the MOSFET and the load resistance R of the polysilicon or the diffusion layer near the point A and set the latter resistance value to a large value.

Further, conventionally, in order to reduce the change in the square of the current ID of the MOSFET, the gate inputs DIN and CO are changed as shown in FIG.
The potential of L is boosted (above VP + VTH), and FIG.
As shown in f of (b), there is a type in which the write characteristic is improved by reducing the inclination of the load line, and the present invention is also applied to such a type by inserting the resistor R in series as in the above. By doing so, the load line indicated by g in FIG. 5 (b) can be realized,
Writing characteristics are further improved.

As shown in FIG. 2 (b), when the resistor R is placed at the locations shown in FIGS. 1 (b) and 1 (c), the resistor R is provided during the formation of the column selection transistors C1 to Cn (field region). Therefore, the area occupied by the pattern does not increase due to the resistance R.

[Effects of the Invention] According to the present invention as described above, the inclination of the load line at the time of writing is determined mainly by the resistance. It is possible to provide a nonvolatile semiconductor memory in which the degree of deterioration of the pattern is small and the pattern occupying area is made advantageous.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 (a) is a pattern plan view of the essential part, and FIG. 2 (b) is a sectional view taken along line aa 'in FIG. 1 (a). FIG. 3 is a circuit configuration diagram of a conventional nonvolatile memory, FIG. 4 (a) is a partial circuit diagram of the same configuration, FIG. 4 (b) is a characteristic diagram of the circuit (a) and the above embodiment, FIG. FIG. 5 (a) is a partial circuit diagram of a conventional improved memory, and FIG. 5 (b) is a characteristic diagram of the circuit and another embodiment of the present invention. 4 ... Field insulating film, 104 ... Load transistor, R
... resistance, VP ... power supply, M11 ... memory cell, C1 ... column selection transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Innovator Hidenobu Minagawa 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki, Kanagawa 1 Toshiba Microcomputer Engineering Co., Ltd. (72) Yuichi Tatsumi 25-1 Ekimaehonmachi, Kawasaki, Kanagawa Microcomputer Engineering Co., Ltd. (56) Reference JP 62-145871 (JP, A) JP 56-34190 (JP, A) JP 58-53864 (JP, A)

Claims (2)

[Claims] 1. A power supply, a non-volatile memory cell, a load transistor connected between the power supply and the non-volatile memory cell, at least a gate of which is controlled by input data, and the power supply and the memory cell. A non-volatile semiconductor memory comprising a pure resistance made of polysilicon or a diffusion layer having a resistance value larger than the on resistance value of the load transistor and connected in series with the load transistor. 2. A power supply, a non-volatile memory cell, a load transistor connected between the power supply and the non-volatile memory cell, at least a gate of which is controlled by input data, and the power supply and the memory cell. A plurality of write circuits, each of which is connected in series to the load transistor and has a pure resistance made of polysilicon or a diffusion layer having a resistance value larger than the ON resistance value of the load transistor, are arranged in parallel, and the load transistor and the memory are connected. A nonvolatile semiconductor memory, wherein the pure resistor is arranged in a field region between column select transistors provided between a cell and the cell.