JPH0640558B2 - Electronic component device - Google Patents

Electronic component device

Info

Publication number
JPH0640558B2
JPH0640558B2 JP60223393A JP22339385A JPH0640558B2 JP H0640558 B2 JPH0640558 B2 JP H0640558B2 JP 60223393 A JP60223393 A JP 60223393A JP 22339385 A JP22339385 A JP 22339385A JP H0640558 B2 JPH0640558 B2 JP H0640558B2
Authority
JP
Japan
Prior art keywords
thick film
film conductor
electronic component
component device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60223393A
Other languages
Japanese (ja)
Other versions
JPS6281722A (en
Inventor
広 高林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP60223393A priority Critical patent/JPH0640558B2/en
Publication of JPS6281722A publication Critical patent/JPS6281722A/en
Publication of JPH0640558B2 publication Critical patent/JPH0640558B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は電子部品装置に係り、特に低耐熱性構造体上へ
の実装に適した電子部品装置に関する。
The present invention relates to an electronic component device, and more particularly to an electronic component device suitable for mounting on a low heat resistant structure.

[従来技術] 従来、この種の電子部品実装(以下、IC実装を例に取
り説明する)に際しては一般的にAu,Al等の細線を
用いるワイヤボンディング方式を用いていたが、ICチ
ップが入手し易い等の汎用性がある反面、Au細線の熱
圧着および超音波併用の熱圧着のボンディングでは基板
を約150℃〜350℃に加熱する必要があり液晶素子
等の低耐熱性構造上へのIC実装には不向きであった。
また前記ワイヤボンディング方式は多数配線時の配線不
良率が高い、配線作業に時間がかかる、修正,修理に手
間がかかる、配線ピッチが粗く高密度実装には不向きで
ある、配線ループの高さと配線保護の封止剤により薄型
実装が不可能である等の欠点があった。
[Prior Art] Conventionally, a wire bonding method using a fine wire such as Au or Al is generally used for mounting electronic components of this type (hereinafter, IC mounting will be described as an example). Although it has general versatility, such as thermocompression bonding of Au thin wires and thermocompression bonding using ultrasonic waves, it is necessary to heat the substrate to about 150 ° C to 350 ° C, and it is necessary to apply it to a low heat resistant structure such as a liquid crystal element. It was not suitable for IC mounting.
Further, the wire bonding method has a high wiring defect rate when a large number of wiring lines are formed, takes a lot of time for wiring work, is troublesome to correct and repair, has a coarse wiring pitch, and is not suitable for high-density mounting. There is a defect that thin mounting is impossible due to the protective sealant.

これらの解決方法としてフィルムキャリアボンディン
グ、フリップチップボンディング等のギャングボンディ
ング方式があるが、これらの方式はワイヤボンディング
方式の欠点を多くの点で解決している反面、ICチップ
上の取り出し電極にバリア金属、バンプ金属等の特殊な
処理をする必要があるため、ICチップのコストアップ
や入手が難しい等汎用性に乏しいという欠点があった。
また、フィルムキャリアボンディング方式では銅箔等を
パターニングしたポリイミド等のフィルムを使用するた
めコストがアップしてしまう欠点が有り、フリップチッ
プボンディング方式ではバンプ電極に5Sn−95Pb
のはんだを使用するため接合時の温度が高くなってしま
う等の欠点があった。
Gang carrier bonding methods such as film carrier bonding and flip chip bonding are available as solutions to these problems, but these methods solve many of the drawbacks of the wire bonding method, but on the other hand, a barrier metal is used for the extraction electrode on the IC chip. However, since it is necessary to perform a special treatment on the bump metal or the like, there is a drawback that the versatility is poor such that the cost of the IC chip is high and it is difficult to obtain the IC chip.
In addition, the film carrier bonding method has a drawback that the cost is increased because a film made of polyimide or the like in which copper foil or the like is patterned is used. In the flip chip bonding method, 5Sn-95Pb is used for the bump electrode.
However, there is a drawback in that the temperature at the time of joining becomes high because the above solder is used.

ワイヤボンディング方式やギャングボンディング方式の
欠点のうち低温プロセス化,不良チップの取り換えのし
やすさを改善して液晶パネルガラス基板にICチップを
実装する手段として導体を選択的に配列したゴムコネク
ターを介して回路基板とICチップとを接続する方法が
公知である。
Among the shortcomings of wire bonding method and gang bonding method, low temperature process, improvement of easiness of replacement of defective chip and mounting of IC chip on liquid crystal panel glass substrate via rubber connector with conductors selectively arranged A method of connecting a circuit board and an IC chip is known.

[発明が解決しようとする問題点] しかしながら、上記方式ではICチップ上の取り出し電
極にバンプ金属等の特殊な処理が必要であり、また導体
を配列したゴムコネクターを用いているため回路基板,
ゴムコネクター,ICチップの位置合せが必要で作業性
が悪く、位置合せ後にバネ性を持った押え金具で固定す
るため構造が複雑でコストアップにつながるという問題
点があった。
[Problems to be Solved by the Invention] However, in the above-mentioned method, a special treatment such as bump metal is required for the extraction electrode on the IC chip, and a rubber connector in which conductors are arranged is used.
Since the rubber connector and the IC chip need to be aligned with each other, the workability is poor, and since they are fixed with a retainer having a spring property after the alignment, the structure is complicated and the cost is increased.

[問題点を解決するための手段] 以上の問題点は、絶縁基板上に形成した表面に凸部を有
する厚膜導体を有する回路基板と、この回路基板上に配
置した電子部品とが、前記厚膜導体の凸部と該電子部品
の取り出し電極との位置が合わされ、異方性導電接着層
を介して電気的接続されている事を特徴とする本発明の
電子部品装置によって解決される。
[Means for Solving the Problems] The above-mentioned problems are caused by the above-mentioned problems in that the circuit board having the thick film conductor having the convex portion on the surface formed on the insulating substrate and the electronic component arranged on the circuit board are The problem is solved by the electronic component device of the present invention, in which the projections of the thick film conductor and the extraction electrodes of the electronic component are aligned with each other and are electrically connected through the anisotropic conductive adhesive layer.

[実施例] 以下、本発明の実施例を図面を用いて詳細に説明する。EXAMPLES Examples of the present invention will be described below in detail with reference to the drawings.

第1図は本発明の電子部品装置の一実施態様を示すIC
装置の断面図で、1は回路基板でガラス,セラミック等
の絶縁基板2の上に第1の厚膜導体3と第2の厚膜導体
4とを形成している。厚膜導体としては、Au,Au−
Pd,Ag−Pd等の貴金属系、Cu,Ni系等の材料
が用いられるが、第1の厚膜導体3と第2の厚膜導体4
とは同一材料,同種材料,異種材料のいずれの組み合わ
せであっても良い。5は異方性導電接着層で絶縁樹脂6
の中にAu,Ag,Cu,Ni,C等の導電体7を分散
しており、8はICチップ,抵抗体,コンデンサ等の電
子部品でここではICチップとする。9はICチップ8
上に形成された取り出し電極である。回路基板1の作成
方法はまず絶縁基板2のほぼ全面に第1の厚膜導体を形
成するペーストを印刷,スピンコート等の方法で供給
し、レベリング、乾燥後焼成する。次に第2の厚膜導体
を形成するペーストを印刷,スピンコート等の方法で所
望の位置に供給し、レベリング、乾燥後焼成する。第1
及び第2の厚膜導体を形成するペーストの焼成は同時に
行うことも可能である。更にフォトレジストを前述の焼
成したペースト上に塗布し、露光、現像した後フォトレ
ジストをマスクとしてペーストをエッチングすることに
より、前記第1及び第2の厚膜導体を形成する。この時
第2の厚膜導体はICチップ8の取り出し電極9とピッ
チを合わせて突起状又は凸状に作製される。厚膜導体は
前述したようなフォトプロセスによらず印刷法によって
直接パターンを作製することも可能である。
FIG. 1 is an IC showing an embodiment of the electronic component device of the present invention.
In the cross-sectional view of the device, reference numeral 1 is a circuit board in which a first thick film conductor 3 and a second thick film conductor 4 are formed on an insulating substrate 2 such as glass or ceramic. As a thick film conductor, Au, Au-
A noble metal-based material such as Pd or Ag-Pd or a material such as Cu or Ni-based material is used, but the first thick film conductor 3 and the second thick film conductor 4 are used.
May be the same material, the same kind of material, or a combination of different kinds of materials. 5 is an anisotropic conductive adhesive layer, and insulating resin 6
Conductors 7 made of Au, Ag, Cu, Ni, C, etc. are dispersed therein, and 8 is an electronic component such as an IC chip, a resistor and a capacitor, which is an IC chip here. 9 is an IC chip 8
It is an extraction electrode formed on the top. In order to make the circuit board 1, first, a paste for forming the first thick film conductor is supplied on almost the entire surface of the insulating substrate 2 by a method such as printing, spin coating, leveling, drying and firing. Next, the paste for forming the second thick film conductor is supplied to a desired position by a method such as printing or spin coating, leveled, dried and baked. First
The firing of the paste for forming the second thick film conductor can also be performed at the same time. Further, a photoresist is applied on the above-mentioned baked paste, exposed and developed, and then the paste is etched using the photoresist as a mask to form the first and second thick film conductors. At this time, the second thick film conductor is formed in a projecting shape or a convex shape at the same pitch as the extraction electrodes 9 of the IC chip 8. It is also possible to directly form a pattern for the thick film conductor by a printing method instead of the photo process as described above.

次に接続方法について説明する。Next, the connection method will be described.

回路基板1上に硬化後に異法性導電を示す導電性接着剤
(前記した様に絶縁性樹脂接着剤中に金属粉末等の導電
性粉末が分散されている)を所望の位置に印刷する。回
路基板1上に突起状又は凸状に形成された第2の厚膜導
体4とICチップ8上に形成された取り出し電極9との
位置を略合せて回路基板上にICチップ8を搭載した後
ICチップ8側からヒータ(図示せず)にて加熱しなが
ら加圧すると絶縁樹脂6が回路基板1とICチップ8間
に熱融着して固定されるとともに突起状又は凸状の第2
の厚膜導体4によって押圧された部分が導電体7を介し
てICチップ8の取り出し電極9と接触し電気的に導通
する。ICチップ8の固定は絶縁樹脂6によるだけでな
く、補強用の接着剤を用いても良いしまたは押え金具を
つけることも可能である。更にICチップ8の封止をよ
り強固にすることも兼ねて別の絶縁樹脂を用いてICチ
ップ8全体を被覆することも当然可能である。上記接続
方法の説明においては、異方性導電接着剤の作製方法と
して液状の導電性接着剤を用いた場合を示したが、その
他例えば絶縁性を有する固形接着剤中に金属粉末等の導
電性粉末を分散させ、シート状に成型した固形接着剤を
用いても良い。
On the circuit board 1, a conductive adhesive that exhibits an anisotropic conductivity after curing (conductive powder such as metal powder is dispersed in the insulating resin adhesive as described above) is printed at a desired position. The IC chip 8 was mounted on the circuit board 1 by substantially aligning the positions of the second thick film conductor 4 formed on the circuit board 1 in a protruding shape or the convex shape with the extraction electrode 9 formed on the IC chip 8. When pressure is applied from the side of the rear IC chip 8 while heating with a heater (not shown), the insulating resin 6 is heat-fused and fixed between the circuit board 1 and the IC chip 8 and the second protrusions or protrusions are formed.
The portion pressed by the thick film conductor 4 comes into contact with the extraction electrode 9 of the IC chip 8 through the conductor 7 and is electrically conducted. The fixing of the IC chip 8 is not limited to the insulating resin 6, but an adhesive for reinforcement may be used or a metal fitting may be attached. Further, it is naturally possible to cover the entire IC chip 8 with another insulating resin while also strengthening the sealing of the IC chip 8. In the above description of the connecting method, the case where a liquid conductive adhesive is used as a method for producing an anisotropic conductive adhesive is shown. However, in addition, for example, a solid adhesive having an insulating property such as a metal powder having a conductive property is used. You may use the solid adhesive which disperse | distributed powder and shape | molded in the shape of a sheet.

第2図は上記IC装置の実施態様を示す断面図で液晶表
示パネルガラス基板上にICチップを実装した図であ
り、10は下側基板、11は上側基板、12は液晶、1
3はシール剤で下側基板10上には前述の作製方法で第
1及び第2の厚膜導体3,4を形成するが、より好適に
は第1の厚膜導体3はシール剤13を塗布する略中間位
置まで形成し、液晶を駆動するためのITO、Al等で
形成される薄膜導体14と接続する。第1の厚膜導体3
をシール剤13の位置まで形成することによって薄膜導
体14の保護を省くことができる。
FIG. 2 is a cross-sectional view showing an embodiment of the IC device in which an IC chip is mounted on a liquid crystal display panel glass substrate, 10 is a lower substrate, 11 is an upper substrate, 12 is a liquid crystal, 1
Reference numeral 3 is a sealant, and the first and second thick film conductors 3 and 4 are formed on the lower substrate 10 by the above-described manufacturing method. More preferably, the first thick film conductor 3 includes the sealant 13. It is formed up to a substantially intermediate position to be applied and is connected to the thin film conductor 14 made of ITO, Al or the like for driving the liquid crystal. First thick film conductor 3
It is possible to omit the protection of the thin film conductor 14 by forming the sealing agent 13 up to the position of the sealing agent 13.

ICチップ8は前述の接続方法と同一の方法で下側基板
10に接続,封止されるが液晶12を加熱昇温させるこ
となく実装が可能であり、そのことによって下側基板1
0からの液晶駆動用の取り出し電極(図示せず)の数を
大幅に減少することが可能となる。
The IC chip 8 is connected and sealed to the lower substrate 10 by the same method as the above-mentioned connecting method, but the IC chip 8 can be mounted without heating the liquid crystal 12 so that the lower substrate 1 can be mounted.
The number of extraction electrodes (not shown) for driving the liquid crystal from 0 can be significantly reduced.

実施例 ガラス基板(コーニング社製#7059、幅10mm×長
さ20mm×厚さ1.1mm)上にAuペースト0.6μm
の厚さで配線パターンを形成するとともに、この配線パ
ターンの一部に突起電極をAuペースト10μmの厚さ
で形成した。突起電極は200μmピッチ、幅100μ
m×長さ200μmの形状で幅4mm×長さ10mm角の内
部に形成した。前記ガラス基板上に異方製導電接着剤ペ
ースト(大阪曹達製モーフィットHM−2000)を2
0μm厚に印刷しシリコン基板を搭載し、150℃,1
0kg/cm2,15秒間の条件にて加熱加圧して熱融着し
た。シリコン基板はテスト用導体パターンと取り出し電
極とをAlで形成し、取り出し電極は200μmピッ
チ、幅120μm×長さ250μmの形状とし外形寸法
は4mm×10mmとした。ガラス基板とシリコン基板との
異方製導電接着剤ペーストを介しての接続抵抗(接触抵
抗)は20Ω〜50Ωの値となり、平均40Ωであっ
た。前記接続抵抗は電圧駆動型のIC例えば液晶駆動用
ICの実装においては問題のないことが確認された。
Example 0.6 μm Au paste on a glass substrate (# 7059 manufactured by Corning, width 10 mm x length 20 mm x thickness 1.1 mm)
The wiring pattern was formed with a thickness of 10 μm, and the protruding electrode was formed with a thickness of 10 μm of Au paste on a part of the wiring pattern. Projection electrodes are 200 μm pitch, width 100 μ
It was formed in a shape of m × 200 μm in length and 4 mm in width × 10 mm in length. 2 on the glass substrate, an anisotropic conductive adhesive paste (Morfit HM-2000 manufactured by Osaka Soda).
Printed to a thickness of 0 μm and mounted with a silicon substrate, 150 ° C, 1
It was heated and pressed under the conditions of 0 kg / cm 2 and 15 seconds for heat fusion. The silicon substrate had a test conductor pattern and lead electrodes formed of Al, and the lead electrodes had a 200 μm pitch, a width of 120 μm × a length of 250 μm, and outer dimensions of 4 mm × 10 mm. The connection resistance (contact resistance) between the glass substrate and the silicon substrate via the anisotropic conductive adhesive paste was a value of 20Ω to 50Ω, and was 40Ω on average. It has been confirmed that the connection resistance has no problem in mounting a voltage drive type IC, for example, a liquid crystal drive IC.

なお、実装完了後にICチップや回路基板の不良又は接
続時の位置合せ不良等による接続不良が発見されたこと
を想定して酢酸カルビトール溶剤を用い、繰り返して接
続と剥離を行ったが数回の繰り返し回数では全く問題が
なく、本実実装構造が修理性にも優れていることが確認
された。
It should be noted that, assuming that a defective connection such as a defective IC chip or a circuit board or a defective alignment at the time of connection was found after the completion of mounting, carbitol acetate solvent was used to repeatedly connect and separate, but several times. It was confirmed that there was no problem in the number of times of repeating and the actual mounting structure was excellent in repairability.

[発明の効果] 以上詳細に説明したように、本発明の電子部品装置によ
れば、次のような効果が得られる。
[Effects of the Invention] As described in detail above, according to the electronic component device of the present invention, the following effects can be obtained.

(1)低温接続プロセスであるために部品,材料,構成
等の制約をうけない。
(1) Since it is a low temperature connection process, there are no restrictions on parts, materials, configurations, etc.

(2)修理が可能である。(2) Repair is possible.

(3)一括ボンディング方式であるため、接続ピン数が
多くても短時間で接続でき、かつ封止を兼ねた構造なの
で生産性に優れている。
(3) Since it is a batch bonding method, it can be connected in a short time even if the number of connection pins is large, and it has excellent productivity because it has a structure that also serves as sealing.

(4)薄型,高密度実装が可能である。(4) Thin and high-density mounting is possible.

本発明の電子部品装置は特に液晶表示パネル等の低耐熱
性構造体上へのIC実装を可能とし、その実用的効果は
多大である。
The electronic component device of the present invention enables IC mounting especially on a low heat resistant structure such as a liquid crystal display panel, and its practical effects are great.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の電子部品装置の一実施態様を示すIC
装置の断面図である。 第2図は上記IC装置の実施態様を示す断面図である。 1,10……回路基板 3……第1の厚膜導体 4……第2の厚膜導体 5……異方性導電接着層 6……絶縁樹脂 7……導電体 8……ICチップ 9……取り出し電極
FIG. 1 is an IC showing an embodiment of the electronic component device of the present invention.
It is sectional drawing of an apparatus. FIG. 2 is a sectional view showing an embodiment of the IC device. 1, 10 ... circuit board 3 ... first thick film conductor 4 ... second thick film conductor 5 ... anisotropic conductive adhesive layer 6 ... insulating resin 7 ... conductor 8 ... IC chip 9 ...... Ejection electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板上に形成した表面に凸部を有する
厚膜導体を有する回路基板と、この回路基板上に配置し
た電子部品とが、前記厚膜導体の凸部と該電子部品の取
り出し電極との位置が合わされ、異方性導電接着層を介
して電気的接続されている事を特徴とする電子部品装
置。
1. A circuit board having a thick film conductor having a convex portion on a surface formed on an insulating substrate, and an electronic component arranged on the circuit board, wherein the convex portion of the thick film conductor and the electronic component An electronic component device characterized in that it is aligned with a lead-out electrode and is electrically connected through an anisotropic conductive adhesive layer.
【請求項2】液晶駆動用ガラス基板のシール部の近傍に
前記厚膜導体を設け、該厚膜導体を液晶駆動用薄膜導体
と接続させた特許請求の範囲第1項記載の電子部品装
置。
2. The electronic component device according to claim 1, wherein the thick film conductor is provided in the vicinity of the seal portion of the liquid crystal driving glass substrate, and the thick film conductor is connected to the liquid crystal driving thin film conductor.
【請求項3】前記厚膜導体は、前記絶縁基板上に形成し
た第1の厚膜導体と該厚膜導体上に凸状に形成した第2
の厚膜導体とで構成されている特許請求の範囲第1項記
載の電子部品装置。
3. The thick film conductor includes a first thick film conductor formed on the insulating substrate and a second thick film conductor formed in a convex shape on the thick film conductor.
The electronic component device according to claim 1, wherein the electronic component device is formed of the thick film conductor according to claim 1.
【請求項4】前記第1及び第2の厚膜導体は同質の材料
で構成されている特許請求の範囲第3項記載の電子部品
装置。
4. The electronic component device according to claim 3, wherein the first and second thick film conductors are made of the same material.
JP60223393A 1985-10-07 1985-10-07 Electronic component device Expired - Lifetime JPH0640558B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60223393A JPH0640558B2 (en) 1985-10-07 1985-10-07 Electronic component device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60223393A JPH0640558B2 (en) 1985-10-07 1985-10-07 Electronic component device

Publications (2)

Publication Number Publication Date
JPS6281722A JPS6281722A (en) 1987-04-15
JPH0640558B2 true JPH0640558B2 (en) 1994-05-25

Family

ID=16797439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60223393A Expired - Lifetime JPH0640558B2 (en) 1985-10-07 1985-10-07 Electronic component device

Country Status (1)

Country Link
JP (1) JPH0640558B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192244A (en) * 1987-02-04 1988-08-09 Semiconductor Energy Lab Co Ltd Method of mounting semiconductor chip
US20240080992A1 (en) * 2022-09-01 2024-03-07 Reophotonics, Ltd. Methods for printing a conductive pillar with high precision

Also Published As

Publication number Publication date
JPS6281722A (en) 1987-04-15

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