JPH0640418B2 - Noise eliminator - Google Patents

Noise eliminator

Info

Publication number
JPH0640418B2
JPH0640418B2 JP59277106A JP27710684A JPH0640418B2 JP H0640418 B2 JPH0640418 B2 JP H0640418B2 JP 59277106 A JP59277106 A JP 59277106A JP 27710684 A JP27710684 A JP 27710684A JP H0640418 B2 JPH0640418 B2 JP H0640418B2
Authority
JP
Japan
Prior art keywords
output
circuit
signal
input
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59277106A
Other languages
Japanese (ja)
Other versions
JPS61150163A (en
Inventor
清一 橋本
正一 西野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59277106A priority Critical patent/JPH0640418B2/en
Priority to US06/773,673 priority patent/US4730165A/en
Priority to KR1019850006564A priority patent/KR910000368B1/en
Priority to EP85111498A priority patent/EP0175275B1/en
Priority to DE8585111498T priority patent/DE3574550D1/en
Priority to CN 85106804 priority patent/CN1011185B/en
Publication of JPS61150163A publication Critical patent/JPS61150163A/en
Publication of JPH0640418B2 publication Critical patent/JPH0640418B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G7/00Volume compression or expansion in amplifiers
    • H03G7/007Volume compression or expansion in amplifiers of digital or coded signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/76Television signal recording
    • H04N5/91Television signal processing therefor
    • H04N5/92Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N5/923Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback using preemphasis of the signal before modulation and deemphasis of the signal after demodulation

Description

【発明の詳細な説明】 産業上の利用分野 本発明はVTRやビデオディスク装置等に応用して、ビ
デオ信号に含まれる微小な特定域の雑音成分を軽減する
ビデオ信号の雑音除去装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal noise eliminator which is applied to a VTR, a video disc device or the like to reduce a noise component in a minute specific area contained in a video signal. is there.

従来の技術 従来の雑音除去装置としては、例えば特開昭58−96
473号公報に示されている。
2. Description of the Related Art As a conventional noise eliminator, for example, JP-A-58-96 is used.
No. 473 publication.

第4図はこの従来の雑音除去装置のブロック図を示すも
のであり、1はビデオ信号の入力端子、2は入力端子1
から入力されたビデオ信号から高域周波数成分を分離す
る微分回路(これは低域を遮断し、特定域の高域を通過
するフィルタ特性を持つものでも良い)、3は微分回路
2出力信号を増幅する増幅器、4は振幅制限器、5は増
幅器3で増幅され、振幅制限器4で一定振幅に制限され
た信号を適当なレベルに減衰する減衰器、6は前記入力
端子1から入力されたビデオ信号と前記減衰器5の出力
信号を互いに逆相で混合する混合器、7は混合器6の出
力信号すなわち雑音が軽減されたビデオ信号を出力する
出力端子、8は振幅制限器4の動作を検出して微分回路
2の充放電流を増大させる充放電回路である。
FIG. 4 is a block diagram of this conventional noise eliminator, in which 1 is an input terminal of a video signal and 2 is an input terminal 1.
Differentiating circuit for separating high frequency components from the video signal input from (which may have a filter characteristic that cuts off the low frequency band and passes the high frequency band of a specific band), 3 is an output signal of the differential circuit 2 An amplifier for amplifying, 4 is an amplitude limiter, 5 is an attenuator for amplifying the signal amplified by the amplifier 3 and limited to a constant amplitude by the amplitude limiter 4 to an appropriate level, and 6 is input from the input terminal 1. A mixer for mixing the video signal and the output signal of the attenuator 5 in opposite phases, 7 is an output terminal for outputting the output signal of the mixer 6, that is, a video signal with reduced noise, 8 is an operation of the amplitude limiter 4. Is a charging / discharging circuit for increasing the charging / discharging current of the differentiating circuit 2.

第5図は微分回路2、振幅制限器4、充放電回路8の具
体回路図であって、容量9、抵抗10は微分回路2を構
成し、抵抗11、トランジスタ12、13および電圧源
14は振幅制限器4を構成し、抵抗15およびトランジ
スタ16は充電回路を、抵抗17、トランジスタ18は
放電回路を構成している。電圧源19は充放電回路8の
出力を適当にバイアスするためのものであって、これは
また増幅器3の入力バイアス電源を兼ねることができ
る。
FIG. 5 is a specific circuit diagram of the differentiating circuit 2, the amplitude limiter 4, and the charging / discharging circuit 8. The capacitor 9, the resistor 10 constitutes the differentiating circuit 2, and the resistor 11, the transistors 12, 13 and the voltage source 14 are The amplitude limiter 4 is formed, the resistor 15 and the transistor 16 form a charging circuit, and the resistor 17 and the transistor 18 form a discharging circuit. The voltage source 19 is for properly biasing the output of the charging / discharging circuit 8, and can also serve as the input bias power source of the amplifier 3.

以上のように構成された従来の雑音除去装置について、
以下第6図要部波形図を用いて説明する。ここでは簡単
のため入力信号として、第6図aに示すようにt=0で
レベルVに変化するステップ信号を用い、これに微小
レベルの高周波のノイズNが重畳しているものとする。
今、容量9の容量値をC、抵抗10の抵抗値をRとする
と微分回路2の伝達特性は、SRC/(SRC+1)とな
る(Sはラプラス変換変数)。この微分回路に第6図a
に示すステップ信号が入力された場合、充放電回路が動
作しない時第6図bに実線で示す信号が出力される。す
なわち入力信号がステップ状に一定レベルだく変化した
時、変化の瞬間微分回路の出力も同じレベルだけ変化
し、その後入力信号の変化の正負にしたがって放電また
は充電電流が流れ、微分回路の出力電位は抵抗10の一
端が結合されている基準点の電位に向って変化する。な
お、ここでは容量9から抵抗10の方向へ電流が流れる
場合を放電、これとは逆に容量9へ電流が流れる場合を
充電と表現している。この場合の充放電の時定数はRC
である。そして微分回路出力信号を増幅し、振幅制限を
加えた場合の波形は第6図cの実線のようになる。いま
入力信号に対して振幅制限されるレベルをV、増幅器
3の増幅度をKとすると、振幅制限器4の出力波形は微
分回路2出力がVを越える部分については振幅制限さ
れるのでレベルがKVのフラット信号となる。このフ
ラット部分の時間幅は入力信号の変化レベルと微分回路
の時定数で決定される。たとえば時刻t=0でレベルV
だけ変化するステップ信号を仮定すると、微分回路の
出力電圧 となり、これが振幅制限レベルVに達する時間t
は、 t=RC ln(V/V) …………(2) となる。すなわち、この時間間隔だけ微分信号は振幅制
限される。第6図dの実線は振幅制限された出力を減衰
器5で所定のレベルに減衰して入力信号と逆位相の関係
で混合器6により混合した出力波形である。
Regarding the conventional noise eliminator configured as described above,
This will be described below with reference to FIG. Here, for the sake of simplicity, it is assumed that a step signal that changes to the level V A at t = 0 as shown in FIG. 6A is used, and a minute level high-frequency noise N is superposed on the step signal.
Now, assuming that the capacitance value of the capacitor 9 is C and the resistance value of the resistor 10 is R, the transfer characteristic of the differentiating circuit 2 is SRC / (SRC + 1) (S is a Laplace transform variable). This differentiating circuit is shown in FIG.
When the step signal shown in FIG. 6 is input, the signal shown by the solid line in FIG. 6b is output when the charge / discharge circuit does not operate. That is, when the input signal changes stepwise by a constant level, the output of the differentiating circuit also changes by the same level, and then the discharge or charging current flows according to the positive or negative of the change in the input signal, and the output potential of the differentiating circuit changes. The resistance of the resistor 10 changes toward the potential of the reference point to which one end of the resistor 10 is coupled. Note that, here, the case where a current flows from the capacitance 9 to the resistor 10 is expressed as discharge, and the case where a current flows to the capacitance 9 on the contrary is expressed as charge. The charging / discharging time constant in this case is RC
Is. Then, the waveform when the differential circuit output signal is amplified and the amplitude is limited is as shown by the solid line in FIG. 6c. If the amplitude-limited level of the input signal is V B and the amplification degree of the amplifier 3 is K, the output waveform of the amplitude limiter 4 is amplitude-limited at the portion where the output of the differentiating circuit 2 exceeds V B. The level becomes a KV B flat signal. The time width of this flat portion is determined by the change level of the input signal and the time constant of the differentiating circuit. For example, at time t = 0, level V
Assuming a step signal that changes by A , the output voltage of the differentiation circuit Is And the time t at which this reaches the amplitude limit level V B
1 becomes t 1 = RC ln (V B / V A ) ... (2). That is, the amplitude of the differential signal is limited by this time interval. The solid line in FIG. 6d is the output waveform obtained by attenuating the output whose amplitude has been limited to a predetermined level by the attenuator 5 and mixing by the mixer 6 in a phase opposite to the input signal.

つぎに、入力信号に第6図aのように高周波のノイズN
が重畳している場合を考えると、微分回路の出力にもそ
の通過帯域に応じてノイズNが重畳する。このノイズN
のうち振幅制限器4でリミットされない部分は第6図c
のように残り、混合器6においてキャンセルされる。
Next, a high-frequency noise N is added to the input signal as shown in FIG. 6a.
Considering the case where is superimposed, noise N is also superimposed on the output of the differentiating circuit according to its pass band. This noise N
The part of the amplitude limiter 4 which is not limited is shown in FIG. 6c.
, And is canceled in the mixer 6.

しかしながら、このノイズ成分のうちリミットされる部
分についてはクリップされてノイズを取り出すことがで
きないため、混合器6の出力ではノイズがキャンセルさ
れず、第6図dのN´のようになる。しかもこのリミッ
トされた部分は一定の直流レベルを持っているので、混
合器6の出力において、直流成分が減少、言いかえると
信号成分が減少してしまう。要するに、この雑音除去装
置は、入力信号のフラットな部分については雑音が除去
されるが、直流レベルが変化する部分、大振幅の交流成
分を持つ部分については雑音除去効果がなく、逆に信号
成分が減少するという欠点がある。さらに、微分回路2
の出力信号がリミットされフラットとなる部分の時間幅
は微分回路2の時定数RCに比例し、低周波のノイ
ズを通過させるためにはRCを大きくしなければなら
ず、そのため時間幅tが大きくなってしまう。
However, since the limited part of this noise component is clipped and noise cannot be extracted, the noise is not canceled at the output of the mixer 6, and the noise becomes as shown by N ′ in FIG. 6D. Moreover, since the limited portion has a constant DC level, the DC component in the output of the mixer 6 decreases, in other words, the signal component decreases. In short, this noise eliminator removes noise in the flat portion of the input signal, but has no noise elimination effect in the portion where the DC level changes and the portion having a large amplitude AC component, and conversely the signal component. Has the drawback of being reduced. Furthermore, the differentiating circuit 2
The time width t 1 of the portion where the output signal of the signal is limited and becomes flat is proportional to the time constant RC of the differentiating circuit 2, and RC must be increased in order to pass low-frequency noise. Therefore, the time width t 1 gets bigger.

これに対して充放電回路8が動作する時、微分回路2の
出力レベルの絶対値が振幅制限器4のリミッタレベルV
を越えている時充放電回路8が動作して、微分回路2
の出力が正の時は放電回路を、また負の時は充電回路を
それぞれ動作させて、第6図dの破線で示すように充放
電速度が速くなる。その結果、時間tより短かい時間
でレベルVに達する。微分回路2の出力レベルが
に達すると、放電は微分回路2で決る時定数RCと
なり、第6図cの破線のように振幅制限器4の出力には
時間tだけリミットされた信号が取り出されることに
なる。
On the other hand, when the charge / discharge circuit 8 operates, the absolute value of the output level of the differentiating circuit 2 becomes equal to the limiter level V of the amplitude limiter 4.
When it exceeds B , the charging / discharging circuit 8 operates and the differentiation circuit 2
When the output of is positive, the discharge circuit is operated, and when it is negative, the charging circuit is operated to increase the charge / discharge speed as shown by the broken line in FIG. 6d. As a result, the level V B is reached at time t 2 which is shorter than time t 1 . When the output level of the differentiating circuit 2 reaches V B , the discharge has a time constant RC determined by the differentiating circuit 2, and the output of the amplitude limiter 4 is limited to the time t 2 as shown by the broken line in FIG. 6c. Will be taken out.

なお、第5図の振幅制限器4のリミッタ特性は、抵抗1
1とトランジスタ12,13の導通および遮断特性によ
り決り、トランジスタ12または13の導通時には振幅制
限器出力が一定レベルにリミットされると同時に充電回
路を構成する抵抗15、トランジスタ16または放電回
路を構成する抵抗17、トランジスタ18のいずれかが
動作する。
The limiter characteristic of the amplitude limiter 4 shown in FIG.
It is determined by the conduction and interruption characteristics of 1 and the transistors 12 and 13, and when the transistor 12 or 13 is conducting, the output of the amplitude limiter is limited to a constant level, and at the same time, the resistor 15, the transistor 16 or the discharging circuit which constitutes the charging circuit is constituted. Either the resistor 17 or the transistor 18 operates.

発明が解決しようとする問題点 しかしながら上記のような構成では、充放電回路8の充
放電電流を大きくしてtを十分に小さくしても、第6
図cに示すようなKVのレベルから零に向って減衰す
る成分が残り、これによる信号の欠除が避けられない、
すなわち、VTRにおいてはエッジ部分のS/Nがもと
もと悪く、少しでも良くしたいという要求があるにもか
かわらず従来の雑音除去装置ではこの部分のS/Nを逆
に悪くしていたという問題点、さらに、tを小さくす
るため充放電電流を大きくしたり、より低周波帯域の雑
音を除去するため微分回路2の時定数を大きくすると、
微分回路2を介して入力端子1に流れる充放電電流が大
きくなるため、入力信号に及ぼす影響が大きくなり、出
力信号が歪みやすくなるため、設計が非常に困難になる
という問題点を有していた。
Problems to be Solved by the Invention However, in the above configuration, even if the charging / discharging current of the charging / discharging circuit 8 is increased and t 2 is sufficiently reduced, the sixth
There remains a component that attenuates from the level of KV B toward zero as shown in FIG.
That is, in the VTR, the S / N at the edge portion is originally bad, and although there is a demand to improve the SNR as much as possible, the conventional noise eliminator adversely deteriorates the S / N at this portion. Further, if the charging / discharging current is increased to reduce t 2 , or the time constant of the differentiating circuit 2 is increased to remove noise in a lower frequency band,
Since the charging / discharging current flowing to the input terminal 1 via the differentiating circuit 2 becomes large, the influence on the input signal becomes large, and the output signal easily becomes distorted, which makes the design very difficult. It was

本発明はかかる点に鑑み、第6図aのステップ信号のよ
うな大レベルの信号には信号の欠除が発生せず、エッジ
部分の雑音除去効果も大きく、低周波帯域の雑音まで除
去しても波形の歪みが極めて少ないビデオ信号の雑音除
去装置を提供することを目的とする。
In view of such a point, the present invention does not cause signal loss in a high level signal such as the step signal of FIG. 6a, has a large noise removal effect at the edge portion, and removes even low frequency band noise. Even so, it is an object of the present invention to provide a noise elimination device for video signals with extremely little waveform distortion.

問題点を解決するための手段 本発明は入力信号の所定の時間当りの変化分を取り出す
差分回路と、入力レベルが小さい時出力が入力に略比例
または入力レベルに応じて非線形に圧縮し、入力レベル
が大きい時出力が十分に小または零となる非線形回路
と、この非線形回路の出力を上記所定の時間遅延する遅
延回路と、この遅延回路の出力と前記差分回路の出力と
を加えて前記非線形回路に入力する加算器と、前記非線
形回路の出力に所定の値を乗ずる乗算器と、前記差分回
路に入力した信号から前記乗算器の出力を差し引く減算
器を備えた雑音除去装置である。
Means for Solving the Problems The present invention relates to a difference circuit for extracting a change amount of an input signal per predetermined time, and when the input level is small, the output is approximately proportional to the input or non-linearly compressed according to the input level. A non-linear circuit whose output is sufficiently small or zero when the level is large, a delay circuit which delays the output of this non-linear circuit by the predetermined time, and the non-linear circuit which adds the output of this delay circuit and the output of the difference circuit. It is a noise eliminator comprising an adder input to a circuit, a multiplier that multiplies an output of the nonlinear circuit by a predetermined value, and a subtracter that subtracts an output of the multiplier from a signal input to the difference circuit.

作 用 本発明は前記した構成により、入力信号レベルが小さい
時、非線形回路出力端子における出力信号は非線形回路
のゲインで決る時定数を有する高域通過特性を示し、入
力信号レベルが大きくなると圧縮,振幅制限特性を示
し、さらに入力レベルが大きくなると出力レベルが小さ
くなって、大振幅の入力信号の時は信号の欠除、すなわ
ちS/Nの劣下のない出力が得られ、信号エッジ部分ま
で雑音除去効果があり、かつS/N劣下が少なく低周波
領域まで雑音除去を行なっても波形歪の少ない雑音除去
を行なう。
Operation According to the present invention, when the input signal level is small, the output signal at the output terminal of the non-linear circuit exhibits a high-pass characteristic having a time constant determined by the gain of the non-linear circuit and compresses when the input signal level increases. It exhibits amplitude limiting characteristics, and when the input level becomes higher, the output level becomes lower, and when the input signal has a large amplitude, the signal is eliminated, that is, the S / N is not degraded and the output is obtained. It has a noise removal effect, and has a low S / N ratio, and even if the noise is removed even in the low frequency region, the noise is removed with less waveform distortion.

実施例 第1図は本発明の第1の実施例における雑音除去装置の
ブロック図を示すものである。第1図において、20は
標本化周期Tでディジタル化されたビデオ信号の入力端
子、21はディジタル化されたビデオ信号の標本化周期
Tのn倍(nは正の整数)の時間当りの変化分を取り出
す差分回路であって、遅延時間nTを有する遅延回路2
2と、遅延回路22の入力信号からその出力信号を減じ
る減算器23で構成される。24は非線形回路であっ
て、入力レベルが小さい時は略比例または単調増加の特
性を示し、入力レベルが大きくなると出力レベルは逆に
減少して零となる負の特性を示す。25は差分回路21
を構成する遅延回路22と同じ遅延時間nTを有する遅
延回路、26は差分回路21出力信号と遅延回路25出
力信号を加える非線形回路24に入力する加算器、27
は非線形回路24の出力信号に所定の乗数を乗じる乗算
器、28は差分回路21入力信号から乗算器27出力信号
を減じる減算器、29は出力端子で、減算器28の出力
信号すなわち雑音が軽減されたディジタル化されたビデ
オ信号を出力する。
First Embodiment FIG. 1 shows a block diagram of a noise removing device according to a first embodiment of the present invention. In FIG. 1, reference numeral 20 is an input terminal of a video signal digitized at a sampling period T, and 21 is a change per unit time n times (n is a positive integer) the sampling period T of the digitized video signal. A delay circuit 2 for extracting a minute and having a delay time nT
2 and a subtractor 23 that subtracts the output signal from the input signal of the delay circuit 22. Reference numeral 24 denotes a non-linear circuit, which exhibits a substantially proportional or monotonically increasing characteristic when the input level is small, and exhibits a negative characteristic in which the output level conversely decreases and becomes zero when the input level increases. 25 is a difference circuit 21
, A delay circuit having the same delay time nT as that of the delay circuit 22 constituting the above, 26 is an adder for inputting to the nonlinear circuit 24 for adding the output signal of the difference circuit 21 and the output signal of the delay circuit 25,
Is a multiplier that multiplies the output signal of the non-linear circuit 24 by a predetermined multiplier, 28 is a subtractor that subtracts the output signal of the multiplier 27 from the input signal of the difference circuit 21, 29 is an output terminal, and the output signal of the subtractor 28, that is, noise is reduced. And outputs the digitized video signal.

以上のように構成された本実施例の雑音除去特性につい
て、以下その動作を離散システムを表わすZ変換式を用
いて説明する。
The operation of the noise elimination characteristic of the present embodiment configured as described above will be described below by using the Z-transform equation representing a discrete system.

まず、差分回路21は簡単のため遅延回路22の遅延時
間がT(n=1)であって、入力信号の1単位時間T当
りの変化分を取り出すものとする。その結果遅延回路2
5もまた信号を1単位時間T遅延するものとなる。ま
た、非線形回路24によって信号が圧縮される係数をR
とし、乗算器27によって乗ぜられる乗数をKとする。
ここで、第1図の雑音除去装置の伝達関数H(Z)ろ、以
上のR,KおよびZ-1(Z変換における単位遅延演算
子)を使い、Rを一定値と見なしてZ変換式で表わす
と、 となる。上式右辺第2項は高域通過フィルタとなるの
で、H(Z)は高域のみを減衰させる特性を有する。ま
た、このときの時定数はRにより決る。
First, for simplification, it is assumed that the difference circuit 21 has a delay time T (n = 1) of the delay circuit 22 and extracts a change per unit time T of the input signal. As a result, the delay circuit 2
5 also delays the signal by one unit time T. The coefficient by which the signal is compressed by the non-linear circuit 24 is R
Let K be the multiplier multiplied by the multiplier 27.
Here, using the transfer function H (Z) of the noise eliminator shown in FIG. 1 and the above R, K and Z −1 (unit delay operator in Z conversion), R is regarded as a constant value and the Z conversion formula is obtained. When expressed by Becomes Since the second term on the right side of the above equation is a high-pass filter, H (Z) has a characteristic of attenuating only the high band. The time constant at this time is determined by R.

第2図は非線形回路24の入力信号レベルをVi、出力信
号レベルをVとし、非線形特性Rの一例を実線で示し
たものである。ここで、V=RVである。ディジタ
ル信号処理ではROM(読み出し専用メモリ)を使用し
て、任意のRの特性を得ることが出来る。破線は、Rの
他の例であって、実線で示した特性の折線近似特性でも
ある。折線特性は乗算器または加減算器および切換回路
で簡単に得ることが出来る。以下、この折線特性を用い
て動作を説明する。折線特性はV<VでR=a,V
<VでV=aV,VでV=0
とすると入力端子20にt=nT<0で0,t=nT
0でVなるステップ信号が入力される時、差分回路2
1出力にはt=0の時V,t≠0の時0なる信号が現
われる。ここで、V<Vの時、非線形回路24出力
端子にはt<0で0,t=nT0でan+1なる出
力が得られる。これはa<1の場合、時間T毎にa倍に
減衰する信号であって式(1)と対比して時定数は−T/l
n aである。一方、V<V<Vの時、非線形回路
24出力はt=0でaVとなって、以下、時間T毎に
a倍で減衰する信号となる。また、V>Vの時、非
線形回路24出力は常に0となって、出力は発生しな
い。
FIG. 2 shows an example of the non-linear characteristic R with a solid line, where the input signal level of the non-linear circuit 24 is V i and the output signal level is V 0 . Here, V 0 = RV i . In digital signal processing, ROM (read-only memory) can be used to obtain an arbitrary R characteristic. The broken line is another example of R and is also a polygonal line approximation characteristic of the characteristic shown by the solid line. The broken line characteristic can be easily obtained by a multiplier or an adder / subtractor and a switching circuit. The operation will be described below by using this polygonal line characteristic. The broken line characteristic is V i <V B and R = a, V
When B V i <V C , V 0 = aV B , and when V i V C , V 0 = 0
Then, when t = nT <0, 0 at the input terminal 20, t = nT
When a step signal of V S is input at 0, the difference circuit 2
At 1 output, a signal V S appears when t = 0, and a signal 0 appears when t ≠ 0. Here, when V S <V B , the output of the nonlinear circuit 24 is 0 when t <0 and a n + 1 V S when t = nT0. This is a signal that attenuates a times at every time T when a <1, and the time constant is −T / l in comparison with the equation (1).
na. On the other hand, when V B <V S <V C , the non-linear circuit 24 outputs become aV B at t = 0, hereinafter, the signal decays at a times every time T. Further, when V S > V C, the output of the nonlinear circuit 24 is always 0, and no output is generated.

本発明の非線形回路24の特性の特徴は雑音とみなすべ
き微小入力信号に対してはほ比例する特性を示し、所定
の値を越えると圧縮特性を示し、信号とみなすべき大入
力信号に対しては出力が0となることにある。ここで、
圧縮特性は特に不可欠のものではなく、一定入力レベル
まで比例、それ以上の信号に対しては出立が零となる特
性であっても良い。ただし、この場合、入力レベルの変
化に対し、雑音除去する場合としない場合が急激に切り
換るので、入力信号によって不自然さが発生する可能性
があるので第2図実線で示した様な特性が望ましいし、
破線で示す特性で欠点は緩和される。なお、第2図実線
のRの特性において、出力が最大となる入力信号レベル
をVとすると、非線形回路24の出力信号はV
以下の微小入力信号に対しては−T/lnRの時定数で減
衰し、V以上の入力信号に対しては非線形特性Rで決
るレベルに瞬時に圧縮され、その後、−T/lnRの時定
数で減衰する。この圧縮されたレベルは入力レベルが大
きくなる程小さくなることになる。
The characteristic feature of the nonlinear circuit 24 of the present invention is that it is proportional to a minute input signal that should be regarded as noise, exhibits compression characteristics when it exceeds a predetermined value, and indicates a large input signal that should be regarded as a signal. Is when the output becomes 0. here,
The compression characteristic is not particularly indispensable, and it may be a characteristic in which the compression ratio is proportional to a constant input level, and the standing-out is zero for signals higher than that. However, in this case, since the case of removing noise and the case of not removing noise are rapidly changed with respect to the change of the input level, there is a possibility that unnaturalness may occur due to the input signal. Therefore, as shown by the solid line in FIG. Characteristics are desirable,
The characteristics shown by the broken line alleviate the drawbacks. Incidentally, in the characteristic of Figure 2 the solid line R, the input signal level V i output is maximum and V D, the output signal of the nonlinear circuit 24 is V D
The following minute input signals are attenuated with a time constant of −T / lnR, and input signals of V D and above are instantaneously compressed to a level determined by the nonlinear characteristic R, and then, when −T / lnR. Decays with a constant. This compressed level decreases as the input level increases.

以上のように本実施例によれば、入力レベルが小さい時
出力が入力に略比例または圧縮し、入力レベルが大きい
時出力が十分に小または零となる非線形回路を、入力信
号の所定の時間当りの変化分を取り出す差分回路と遅延
回路の出力を加算する加算器の出力と上記遅延回路の入
力の間に設け、上記非線形回路の出力に雑音成分を取り
出すようにして雑音除去装置を構成することにより、大
レベルで変化する入力信号に対し非線形回路に出力が発
生せず、信号のエッジ部分での信号の欠除、すなわちS
/Nの劣下が発生せず、エッジ間際までS/N改善効果
があり、かつその動作が回路の時定数に左右されず、低
周波帯域の雑音まで除去しても波形の歪を少なくするこ
とが出来る。しかも、ディジタル信号処理であるため、
応答が瞬時に行なわれ、信号圧縮に伴なうアナログの様
な過渡特性,信号の歪は発生しない。
As described above, according to the present embodiment, when the input level is small, the output is substantially proportional to or compressed by the input, and when the input level is large, the output is sufficiently small or zero. A noise removing device is constructed by providing a noise component from the output of the non-linear circuit, which is provided between the output of the adder for adding the outputs of the differential circuit and the delay circuit for extracting the variation of the hit and the input of the delay circuit. As a result, no output is generated in the non-linear circuit for an input signal that changes at a large level, and the signal is eliminated at the edge portion of the signal, that is, S
/ N is not deteriorated, S / N is improved up to just before the edge, and its operation is not affected by the time constant of the circuit. Even if noise in the low frequency band is removed, waveform distortion is reduced. You can Moreover, since it is digital signal processing,
The response is instantaneous and the analog-like transient characteristics and signal distortion that accompany signal compression do not occur.

第3図は第1図に示す本発明の実施例で使用する差分回
路21に振幅制限器30を設けたものである。同図にお
いて、振幅制限器30は延走回路22、減算器23で構
成される差分回路の出力レベルを制限するもので、後段
の加算器26の入出力ダイナミックレンジ、非線形回路
24の入力ダイナミックレンジを小さくすることができ
る。すなわち、非線形回路24により遅延回路25の出
力レベルが一定値例えばaVに制限されること、非線
形回路24の入力レベルが一定値(Vとする)を越え
ると出力が一定値零になることにより、差分回路21か
らの加算器26への入力が一定値aV+Vを越える
と必ず非線形回路24の出力が零となって、差分回路2
1の出力にこれ以上のダイナミックレンジが不必要とな
るためである。
FIG. 3 shows the difference circuit 21 used in the embodiment of the present invention shown in FIG. 1 provided with an amplitude limiter 30. In the figure, the amplitude limiter 30 limits the output level of the difference circuit composed of the extension circuit 22 and the subtractor 23. The input / output dynamic range of the adder 26 in the subsequent stage and the input dynamic range of the nonlinear circuit 24 are shown. Can be made smaller. That is, the output level of the delay circuit 25 is limited to a constant value, for example, aV B by the non-linear circuit 24, and the output becomes a constant value of zero when the input level of the non-linear circuit 24 exceeds a certain value (V E ). As a result, when the input from the difference circuit 21 to the adder 26 exceeds a constant value aV B + V E , the output of the non-linear circuit 24 becomes zero, and the difference circuit 2
This is because the output of 1 does not need a dynamic range larger than this.

以上のように、本実施例によれば差分回路21に振幅制
限器30を設けることにより、後段の加算器26、特に
非線形回路24をROMで構成する場合の規模を小さく
することができる。
As described above, according to the present embodiment, by providing the amplitude limiter 30 in the difference circuit 21, it is possible to reduce the scale when the adder 26 in the subsequent stage, particularly the nonlinear circuit 24, is composed of a ROM.

発明の効果 以上説明したように、本発明によれば、大レベルの信号
が入力された時には信号のエッジ部分での信号の欠除す
なわちS/Nの劣下が発生せず、エッジ間ぎわまで雑音
除去効果があり、低周波帯域の雑音まで除去しても波形
の歪みが極めて少ないビデオ信号の雑音除去装置を提供
することができ、その実用的効果は大きい。
EFFECTS OF THE INVENTION As described above, according to the present invention, when a high level signal is input, the signal lacking at the edge portion of the signal, that is, the S / N inferior does not occur, and even between the edges It is possible to provide a noise elimination device for video signals that has a noise elimination effect and has extremely little waveform distortion even if noise in the low frequency band is eliminated, and its practical effect is great.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明における一実施例の雑音除去装置のブロ
ック図、第2図は本発明における雑音除去装置を構成す
る非線形回路の入出力特性図、第3図は本発明の他の実
施例の雑音除去回路を構成する差分回路のブロック図、
第4図,第5図,第6図はそれぞれ従来の雑音除去装置
のブロック図,具体回路図,要部波形図である。 20……入力端子、21……差分回路、22……遅延回
路、23……減算器、24……非線形回路、25……遅
延回路、26……加算器、27……乗算器、28……減
算器、29……出力端子。
FIG. 1 is a block diagram of a noise eliminator of one embodiment of the present invention, FIG. 2 is an input / output characteristic diagram of a non-linear circuit constituting the noise eliminator of the present invention, and FIG. 3 is another embodiment of the present invention. Block diagram of the difference circuit that constitutes the noise elimination circuit of
FIG. 4, FIG. 5, and FIG. 6 are a block diagram, a concrete circuit diagram, and a waveform diagram of a main part of a conventional noise eliminator, respectively. 20 ... Input terminal, 21 ... Difference circuit, 22 ... Delay circuit, 23 ... Subtractor, 24 ... Non-linear circuit, 25 ... Delay circuit, 26 ... Adder, 27 ... Multiplier, 28 ... … Subtractor, 29… Output terminal.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】入力信号の所定の時間当りの変化分を取り
出す差分手段と、入力レベルが小さい時出力が入力に略
比例または入力レベルに応じて非線形に圧縮し、入力レ
ベルが大きい時出力が十分に小または零となる非線形手
段と、前記非線形手段の出力を前記所定の時間遅延させ
る遅延手段と、前記差分手段出力と前記所定の時間遅延
した非線形手段出力の加算信号を前記非線形手段に入力
する手段と、前記非線形手段の出力に所定の値を乗ずる
乗算手段と、前記差分手段に入力した信号から前記乗算
手段の出力を差し引く減算手段とを備えたことを特徴と
する雑音除去装置。
Claim: What is claimed is: 1. A difference means for extracting a variation of an input signal per predetermined time, and when the input level is small, the output is approximately proportional to the input or nonlinearly compressed according to the input level, and when the input level is large, the output is A non-linear means that is sufficiently small or zero, a delay means that delays the output of the non-linear means by the predetermined time, and an addition signal of the differential means output and the non-linear means output delayed by the predetermined time is input to the non-linear means. Means for multiplying the output of the non-linear means by a predetermined value, and subtraction means for subtracting the output of the multiplying means from the signal input to the difference means.
【請求項2】差分手段がその出力レベルが所定の値を越
える時その出力レベルを制限する振幅制限手段を備えた
ことを特徴とする特許請求の範囲第1項記載の雑音除去
装置。
2. A noise eliminating device according to claim 1, further comprising an amplitude limiting means for limiting the output level of the difference means when the output level exceeds a predetermined value.
JP59277106A 1984-09-12 1984-12-24 Noise eliminator Expired - Lifetime JPH0640418B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP59277106A JPH0640418B2 (en) 1984-12-24 1984-12-24 Noise eliminator
US06/773,673 US4730165A (en) 1984-09-12 1985-09-09 Non-linear signal processing apparatus
KR1019850006564A KR910000368B1 (en) 1984-09-12 1985-09-09 Non-linear signal processor apparatus
EP85111498A EP0175275B1 (en) 1984-09-12 1985-09-11 Non-linear signal processing apparatus
DE8585111498T DE3574550D1 (en) 1984-09-12 1985-09-11 PROCESSING DEVICE FOR NON-LINEAR SIGNALS.
CN 85106804 CN1011185B (en) 1984-12-24 1985-09-12 Nonlinear signal processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59277106A JPH0640418B2 (en) 1984-12-24 1984-12-24 Noise eliminator

Publications (2)

Publication Number Publication Date
JPS61150163A JPS61150163A (en) 1986-07-08
JPH0640418B2 true JPH0640418B2 (en) 1994-05-25

Family

ID=17578860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59277106A Expired - Lifetime JPH0640418B2 (en) 1984-09-12 1984-12-24 Noise eliminator

Country Status (2)

Country Link
JP (1) JPH0640418B2 (en)
CN (1) CN1011185B (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124023A (en) * 1977-04-06 1978-10-30 Sony Corp Noise deletion circuit
JPS5797787A (en) * 1980-12-10 1982-06-17 Mitsubishi Electric Corp Picture reproducing device

Also Published As

Publication number Publication date
JPS61150163A (en) 1986-07-08
CN85106804A (en) 1986-06-10
CN1011185B (en) 1991-01-09

Similar Documents

Publication Publication Date Title
EP0175275B1 (en) Non-linear signal processing apparatus
US4852034A (en) Digital filter
JPH0640418B2 (en) Noise eliminator
EP0254512B1 (en) Recording and reproducing device for video signal
US5276403A (en) Nonlinear preemphasis-deemphasis system
JP2691851B2 (en) Digital signal processor
SE444750B (en) METHOD OF ELECTRONICALLY ASTADCOM MAKING EXPLANATION OF SOUND OR IMAGE INFORMATION EQUIPMENT FOR EXECUTING THE METHOD
EP0178936B1 (en) Variable emphasis circuit
JP3166353B2 (en) Noise reduction device
JPH0773357B2 (en) Video signal processor
JPH0216076B2 (en)
JPH06105861B2 (en) Non-linear signal processor
JP2674027B2 (en) Amplitude compression / expansion circuit
Macleod Performance analysis of simple non-linear recursive smoothing filters
JP3743003B2 (en) Digital filter
JP3538539B2 (en) Active filter circuit
JP3439078B2 (en) Digital bus boost circuit
RU2058663C1 (en) Active rc-filter
JP3041858B2 (en) Digital high-pass filter
JPS643223Y2 (en)
JPS6150535B2 (en)
KR200141208Y1 (en) Contour signal generating circuit for camcorder
JPH10190408A (en) Digital filtering means
JPH0758650A (en) Noise canceller
JPH0773356B2 (en) Video signal processor