JPH0640315B2 - Central processing unit allocation control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a central processing unit (hereinafter referred to as CPU) allocation control system, and more particularly to a computer having a mechanism for sharing finite CPU resources among a plurality of tasks in a time-sharing manner. C in the system
The present invention relates to a PU allocation control method.

[Prior Art] A conventional CPU allocation method of this type includes a schedule control table having a task pointer that designates the head of a chain of tasks waiting for CPU allocation for each priority of a task, and a CPU allocation request is issued from a certain task. If so, this schedule control table is referenced from the task pointer with the highest priority to the task pointer with the lowest priority, and the CPU is assigned to the task only when the task pointer for the task with a higher priority is empty.
I am trying to allocate.

[Problems to be solved by the invention]

In the above-mentioned conventional method, only the priority of the task is taken into consideration when allocating the CPU, and if the task with the high priority is waiting for the CPU allocation, the CPU with the low priority cannot be given the priority. When a high-frequency task continues to request the CPU due to a program loop, etc., the low-priority task will not be permanently given the CPU, causing a delay in the response of the terminal or a delay in the job throughput. , C that shares limited CPU resources in a time-sharing manner
This is a problem on the PU schedule.

[Means for solving problems]

According to the method of the present invention, in a central processing unit allocation control method in a computer system having a mechanism for sharing a central processing unit among a plurality of tasks in a time-division manner, a tie pointer for designating a task waiting for allocation of the central processing unit is preset. A schedule control upper limit counter that holds the upper limit value of the number of allocations of the central processing unit, a current schedule counter that holds the current allocation number, and a schedule control table that has a schedule suppression flag corresponding to the priority of the task, and the central processing unit CPU schedule control means for allocating the central processing unit to the task designated by the task pointer, which is the highest priority within which the schedule suppression flag is reset for the allocation request, and the current schedule counter for each allocation of the central processing unit. Walk through A CPU scheduling inhibition control means so that as compared with the schedule deterrence upper counter sets a schedule inhibition flag as a result of the comparison is, CPU scheduling release means for periodically unschedule inhibition flag, and having a city.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, in this embodiment, the CPU schedule control means 1, the CPU schedule inhibition control means 2, the CPU
It can be seen that the schedule release control means 3 and the schedule control table 4 are included.

FIG. 2 shows details of the schedule control table 4 together with tasks T ₁ , T ₂ , T ₃ ... T _n waiting for CPU allocation.

In FIG. 2, the schedule control table 4 has a schedule inhibition flag S _{1 to} S _n and a schedule inhibition upper limit counter M for each of the _n priority levels P ₁ , P ₂ , ... P _{n.
It has 1 to} M _n , current schedule counters C _{1 to} C _n , and task pointers R _{1 to} R _n .

The task pointer R ₁ has priority P ₁ (highest)
Of the CPU allocation waiting task T _1
1 designates a similar task T ₂ . Task pointer R ₂
Is the task T ₃ waiting for CPU allocation having the second highest priority P ₂ , and the task pointer R _n is the lowest priority P 3.
of _n, respectively specify the CPU allocation tasks waiting _{T n.}

The schedule inhibition upper limit counters M _{1 to} M _n hold the values set for the _respective priorities P _{1 to} P _n at the time of system generation, etc., and the current schedule counters C _{1 to} C _n
n holds the number of times the CPU has been assigned to the task group having the priorities P _{1 to} P _n up to the present time.

In addition, schedule inhibition flag _S 1 ~S _n, the priority P
_{1 to} P _n , whether or not to suppress CPU allocation to the task even if there is a CPU allocation waiting task is displayed. In the present embodiment, the current schedule counters C _{1 to} C _n are displayed. When the contents held in the schedule inhibition upper limit counters M _{1 to} M _n are exceeded, the corresponding schedule inhibition flags S _{1 to} S _n are set.

Next, the operation of this embodiment will be described with reference to the flow chart shown in FIG.

First, if there is a CPU allocation request from a task, the CPU
The schedule control means 1 is called. The CPU schedule control unit 1 refers to the task pointers R _{1 to} R _n of the schedule control table 4 in order from the task with the highest priority, and whether there is a task waiting for CPU allocation including the currently requested task. Check whether or not (step 3)
0,35,32).

For a task waiting for CPU allocation, the schedule suppression flag corresponding to the priority of the task is checked (step 31), and when the suppression display is displayed, CPU allocation is not performed and the process proceeds to step 35 via step 32. Migrate to investigate next priority.

When it is found from the result of this investigation that all the priorities have fallen into the schedule suppression state, the schedule suppression is exceeded, and the task is queued out (step 33), that is, the highest priority among the tasks waiting for CPU allocation. The first task in the task group is removed from the task chain, and the CPU is assigned to the task (step 34).

When the inhibition display is not displayed in step 31, the task is queued out (step 36), and the CPU schedule control means 1 transfers the control right to the CPU schedule inhibition control means 2.

Next, the CPU schedule inhibition control means 2 performs step 3
In step 6, the current schedule counter corresponding to the priority to which the task skewed out belongs is incremented (step 37), and the schedule inhibition upper limit counter and the current schedule counter are compared to determine whether the current schedule counter exceeds the schedule inhibition upper limit counter. Check (Step 3
8).

If it is found in step 38 that the control has not been exceeded, the control right is returned to the CPU schedule control means 1, and the CPU queued out in step 36 is assigned a CPU (step 34). In order to suppress, after setting the schedule suppression flag (step 39), the control right is returned to the CPU schedule control means 1 and the CPU is assigned to the task queued out in step 36 (step 34).

It should be noted that the release of the schedule inhibition is performed by periodically activating the CPU schedule releasing means 3 and releasing the schedule inhibition flag from the inhibition state.

〔The invention's effect〕

As is clear from the above description, according to the present invention, by detecting an abnormally large number of CPU allocations for a task with a high priority and temporarily suppressing the CPU allocation for such a task, Since the priority of the task to be assigned decreases, it becomes possible to occasionally assign the CPU to the task with the low priority, and it is possible to improve the throughput and the response time of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a detailed view of a schedule control table in the present embodiment, and FIG. 3 is a flow chart of the present embodiment. 1 ... CPU schedule control means, 2 ... CPU schedule inhibition control means, 3 ... CPU schedule cancellation control means, 4 ... Schedule control table, P _{1 to} P
_n ...... _priority, S 1 ~S _n ...... schedule inhibition _flag, M 1 ~M _n ...... schedule suppression limit counter, C
_{1 ~C n} ...... current schedule _counter, R 1 _{~R n} ......
Task pointers, T _{1 to} T _n ... Tasks.

Claims (1)

[Claims] 1. A central processing unit allocation control method in a computer system having a mechanism for sharing a central processing unit among a plurality of tasks in a time-sharing manner, wherein a task pointer for designating a task waiting for allocation of said central processing unit is preset. A schedule control upper limit counter holding an allocation count upper limit value of the central processing unit, a current schedule counter holding a current allocation count, and a schedule control table having a schedule suppression flag for task priority correspondence, and a central processing from the task CPU schedule control means for allocating the central processing unit to the task specified by the task pointer at the highest priority within which the schedule inhibition flag is reset in response to a device allocation request, and the central processing unit allocation Every time A CPU scheduling inhibition control means the current schedule counter is incremented as compared to the schedule deterrence upper counter sets the schedule inhibition flag as a result of the comparison, CPU periodically release the schedule inhibition flag
A central processing unit allocation control method comprising: a schedule canceling unit.