JPH0640311B2 - Register saving method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of use) The present invention relates to a register saving method capable of efficiently saving the contents of registers required when a context is switched by a program in an electronic computer system. Regarding

(Prior Art) In a CPU of an electronic computer, data that is being calculated and information necessary for executing the program, such as an operating state of the computer and a pointer of a stack, are usually held by using a general-purpose or dedicated register. There is. These pieces of information held in the registers are necessary for reproducing the state of the program currently being executed. Particularly in a multi-programming environment, context switching activated by, for example, an interrupt is performed, so that the contents of the register immediately before the switching is stored in a predetermined area on the memory. When the context is restarted, the contents of the register are restored by using the information stored in the memory to maintain the continuity of the program execution.

Saving and reading of register contents accompanying such context switching are generally executed when a context switching command is given by a software procedure using a store / multiple instruction or load / multiple instruction. . These instructions are very effective in reducing the processing load on the programmer and can be executed relatively easily. However, generally, due to restrictions on the data bus and the like, saving and reading the contents of a register takes a processing time proportional to the number of registers. Therefore, in the case where a program is executed using a large number of registers, it is undeniable that the context switching process takes time and the processing speed is significantly reduced. Therefore, for a microprocessor equipped with a large number of general-purpose registers, it is becoming a serious problem in terms of how to efficiently store and read the register contents accompanying context switching.

Therefore, in the past, a large number of registers were prepared in the CPU in advance, and when switching contexts, a register different from the register being used was allocated for execution of a new context, and this made it possible to estimate the processing time to save the register contents. A method of eliminating it is being considered. However, even if this method is adopted, since the number of registers that can be incorporated in the CPU is substantially limited, there is a similar problem when handling a plurality of contexts exceeding that number. Moreover, when dealing with contexts that exceed the number of registers, software assistance is required as in the above-described example, which causes a problem that the processing load on the software becomes heavy and the processing speed decreases. Furthermore, despite the large number of registers, only a limited number of registers can be used as a programming model, so the number of memory accesses of the program increases, resulting in a decrease in the processing speed. There was also a problem such as doing.

On the other hand, in JP-A-63-208128, a CPU is provided with a register save area, and a flag indicating whether or not the contents are saved in the register save area is provided for each of a plurality of registers. By reference, a method for obtaining the register contents before destruction from the register save area when the register is restored is disclosed. According to such a method, there is an advantage that the register contents indicating the execution state of the previous context can be restored very effectively when the context is switched.

However, in terms of how to efficiently save the register contents in the register save area, the same problem as in the case of selectively using the plurality of registers described above remains.

(Problems to be solved by the invention) As described above, in the related art, in order to efficiently perform context switching, the contents of the register being executed are saved, and the contents of the saved register are read out to In restoring and reproducing the register contents in context execution,
A problem remains in how to efficiently store the contents of registers.

The present invention has been made in consideration of such circumstances, and the purpose thereof is that the number of registers that can be handled is virtually unlimited, and the contents of these registers can be efficiently stored to save the context. It is to provide a register saving method that enables high-speed switching processing.

[Structure of the Invention] (Means for Solving the Problem) According to the present invention, a background save instruction and a save area address are specified at the beginning of a program including a subroutine, and a multiple save instruction is executed immediately before the subroutine in the program. And a register storing method of a computer for sequentially executing a program instruction sequence in which a storage area address is designated, wherein the contents of the registers are stored in a plurality of registers for holding information necessary for executing the program. A flag that is reset when updated is provided separately, and when the background save instruction is executed, the presence or absence of a reset flag is sequentially checked, and if there is a reset flag, the contents of the register Was stored in the memory according to the storage area address, and this storage was successful. Each of the processes for setting the flag at the same time as the execution of the program from immediately after the background save instruction to immediately before the multiple save instruction, using a free time that does not prevent the execution of the program. When performing the multiple save instruction, the presence or absence of the reset flag is sequentially checked,
Stores the contents of the register in the memory according to the storage area address when there is a reset flag,
The feature is that the flag is set when the storage is successful.

(Operation) According to the present invention for controlling the storage of the register contents as described above, by designating the background save instruction and the save area address at the beginning of the program including the subroutine, the multiple save is performed immediately after the background save instruction. In parallel with the execution of the program until immediately before the save instruction, for example, it is possible to detect the vacancy of the memory bus and save the register contents sequentially in the background processing. It is not necessary to perform the storage process, the processing load can be reduced, and the processing time can be shortened. Moreover, since the free time that does not hinder the execution of the program is used, the register contents can be saved without adversely affecting the original execution of the program, which is necessary for the context switching process. The processing time can be significantly reduced.

In addition, the flag attached to the register is used to indicate whether or not the contents of the register have been saved. By referring to this flag, only the contents of the register that have not been saved are saved. Thus, it is possible to improve the processing efficiency by avoiding the unnecessary storage process for the register whose contents have been stored.

(Embodiment) Hereinafter, a register saving method according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a schematic internal configuration of a central processing unit (CPU) configured by applying the embodiment system. This CPU is basically configured by connecting a register file (RF) 3 having, for example, 16 registers, an arithmetic operation unit (ALU) 4, etc. to the internal buses 1 and 2. A
The LU 4 receives the control of the controller (CONT) 5 and executes a predetermined arithmetic process according to a given program while using the register file 3.

Data writing to and reading from the memory (MRY) 6 are performed by detecting the vacancy of the memory bus 8 under the control of the memory controller (MCONT) 7 which operates under the control of the controller 5. That is, when writing data to the memory 6, the write address for the memory 6 is specified according to the memory address set in the memory address register (MARN) 9 and the memory data register (MDRN) is set to the corresponding address.
Data stored in 10 is transferred via the memory bus 8 and written in the memory 6.
Data can be read from the memory 6 by reading the data written at the address designated by the memory address register (MARN) 9 through the memory bus 8 and storing it in the memory register (MSR) 11. Done. The data stored in the memory register (MSR) 11 is transferred to the ALU 4 via the internal buses 1 and 2.
Or by loading data into the register buffer 3,
Information processing using the data written in the memory 6 is executed.

Here, the feature of this embodiment is that each of a plurality of registers prepared in the register file 3 is provided with a flag characterizing the present invention, and a counter (C
The data stored in the register file 3 under the control of (TR) 12 is processed in the background process A described above.
The point is that the program is stored and saved in the memory 6 one after another in parallel with the execution of the program by the LU 4.

The data storage of the register file 3 by the background processing is performed by storing the data stored in the register in the internal bus 2 when the background processing is designated as described later by the selection designation of the register by the counter 12. Memory data register (MD
The data is transferred to the RR) 13 and stored therein, and at the same time, under the control of the address controller (ACONT) 14, the address data to be set in the memory address register (MARR) 15 is set. And this memory address register (M
This is done by addressing the memory 6 according to the address data set in the ARR) 15 and writing the data stored in the memory data register (MDRR) 13 to the specified address of the memory 6.

This background processing is performed by activating a background saving function using a program command as shown in FIG. 2, for example. This background saving is equivalent to the program execution process from a software point of view, but the background register content saving process in this embodiment is performed in hardware in parallel with the execution of the program described above. It is controlled and executed by.

That is, in this embodiment, the user calls a subroutine in his / her own program to switch the context, and as shown in FIG. 2, at the beginning of the program, the register contents in the background are changed. It is designated to save.

That is, here, the save area address [SAVE-ADDRESS] in the memory 6 for saving the register contents is designated by the "save-background instruction". In the example shown in FIG. 2, all of the general-purpose registers are implicitly designated as the data storage target registers.
For example, when a register to be saved can be selectively designated by a bitmap or the like like a commercial microprocessor, it is possible to designate the register by using an operand.

Further, in the software shown in FIG. 2, the "save-multiple instruction" is given before the context is switched, and the "save-background instruction" is left in the registers other than the background-saved registers. Data is forcibly saved.

When the background saving is completed for all the registers, the above-mentioned "save-multiple instruction" is regarded as a "no-operation instruction".

After that, when the control returns again due to the context switching, the register contents saved and stored in the memory 6 are read by the "load-multiple instruction", and the register file 3 is restored.
Also in this case, the save area address [SAVE
-ADDRESS] specifies in which context the register contents are restored.

Next, the operation of the CPU internal circuit shown in FIG. 1 described above in association with the execution of the program shown in FIG. 2 will be described with reference to FIG.

When the background process is designated by the "save-background instruction", the controller 5 for the background process is activated, and the operation of each unit related to the background process is controlled. However, by starting this background processing, first, the above-mentioned "save-backg
The save area address [SAVE-ADDRESS] in the memory 6 designated by the "round instruction" is set in the address controller (ACONT) 14 from the ALU 4 via the internal bus 2. At the same time, the counter 12 is initialized (step a), and the counter operation for sequentially designating a plurality of registers prepared in the register file 3 is started.

The access of the register file 3 by the data generated by the counter 12 is performed while the register file 3 is not accessed by the program being executed by the ALU 4. In other words, the access of the register file 3 by the ALU 4 is determined prior to the access of the register file 3 by the counter 12, and the ALU 4 preferentially uses the register file 3 to execute a predetermined program. Has become. The counter 12 accesses the register file 3 only when the empty state of the register file 3 is detected, thereby activating the register saving process in parallel with the execution of the above-mentioned program.

When the register file 3 is accessed by the counter 12, the counter value is first read into the address controller (ACONT) 14 (step b). At the same time, the information of the flag provided attached to the register designated by the counter value is read from the register file 3 via the internal bus 2. The address controller 14 refers to a flag attached to the register to check whether the storage of the contents of the register in the memory 6 is completed (step c). That is, the flag provided to the register is set when the content of the register is stored and saved in the memory 6 by the background processing as described later, and when the content of the register is updated by the execution of the program. Alternatively, it is reset when the register contents are destroyed (updated) before the memory saving of the register contents by the background processing is successful, and the flag "1" indicates that the storage and saving of the register contents are completed. It has become a thing.

The address controller (ACONT) 14 refers to such a flag to copy the contents of the register to the memory 6
Controls whether to save to. By the way, if the flag is already set to "1", it is completely useless to save the register content in the memory 6 again. Therefore, according to the information of the flag "1" Store and save processing is prohibited. Then, under the control of the controller 5, the value of the counter 12 is updated (step d), and the content saving process for the next register is started.

When the flag of the register designated by the counter 12 is “0”, the address controller (ACONT) 14 sets the counter 12 to the save area address [SAVE-ADDRESS] designated by the ALU 4. The value specified by is added, and the address value of the memory 6 obtained by this is set in the memory address register (MARR) 15 (step e). That is, the absolute address for storing the register data in the memory 6 is obtained by adding the relative address to the register designated by the counter 12 to the save area address [SAVE-ADDRESS], and this is stored in the memory address register (MARR) 15. set. With the setting of the address data in the memory address register 15, the contents of the register designated by the counter 12 are read from the register file 3 via the internal bus 2 and stored in the memory data register (MDRR) 13. (Step f).

Then, when the address data for the memory 6 is set in the memory address register (MARR) 15 and the register content to be written at this address is stored in the memory data register (MDRR) 13, the memory controller (MCONT) 7 is sent. An access request for the memory 6 is issued. In response to this access request, the memory controller 7 waits for a free space on the memory bus 8 and permits writing of the register contents to the memory 6. This memory 6
The order of access requests for writing the contents of the register to is set to the lowest so as not to hinder the execution of the program. Therefore, only when the memory bus 8 has a space, the memory controller (MCONT)
Under the control of the memory address register (MAR
The register contents stored in the memory data register (MDRR) 13 are written to the address of the memory 6 designated by R) 15 (step g).

The writing of such register contents to the memory 6 is performed for a predetermined time. If the writing is successful (step h), the register file 3 is notified of the successful saving under the control of the controller 5, and the flag provided as "1" is attached to the register. Is set to "" (step i). After that, the count value of the counter 12 is increased as described above (step d), and the process proceeds to the storage process of the next register contents.

The process of storing and saving the register contents in the memory 6 is sequentially and repeatedly executed according to the selection and designation of the register by the counter 12 and the value of the flag attached to the designated register. Moreover, in parallel with the execution of the program,
The register contents are saved in the background process using a free time that does not hinder the execution of the program.

On the other hand, when such background processing is being executed, the program is executed in the main routine regardless of this background processing (step A). However, the controller 5 monitors whether or not the contents of the register are changed in accordance with the execution of the program (step B). When the contents of the register are changed, the controller 5 is attached to the register. It is checked whether the flag indicating that the flag is set is set (step C). When the flag of the register is "1", the contents already stored in the memory 6 differ from the contents actually stored in the register. Therefore, the new contents should be stored in the memory 6 as described above. Reset the flag (step D).

By the processing procedure as described above, the setting / resetting of the flags respectively attached to the registers is controlled, and only the registers for which the contents are not stored in the memory 6 are excluded, except for the registers for which the flags are set. The storage process to the memory 6 is performed according to the information of "0". Moreover, independently of the context switching instruction, the register is used in the background during the execution of the program in the background while the register file 3 is not being accessed by the execution of the program, the free time of the memory bus 8 or the like. The contents are stored in the memory 6.
Furthermore, only for registers that have not been saved, or only for registers that have been updated,
The contents are stored in the memory 6.

As a result, when the context switching instruction is given, the memory 6 is processed by the background processing described above.
Only the registers whose contents have not been saved to are checked from the flag, and only the contents of the register indicated by this flag are saved according to the above-mentioned "save-multiple instruction", and all the register contents are saved in a short time. It becomes possible to save efficiently. Therefore, it is possible to perform the register content saving process associated with the context switching very efficiently and speed up the switching process.

Further, according to such a register content saving process, the register contents are sequentially saved in the memory 6 in the background process while executing the program, so that even when the number of registers prepared in the CPU is large. , The contents of registers to be saved do not increase so much when switching contexts. Therefore, the context switching process can be efficiently performed regardless of the number of registers.

Further, since it is different from the conventional one in which a plurality of registers are selectively used to execute a context, the number of contexts that can be handled is not practically limited, and the memory 6 can be effectively used for each context. There is an advantage that the contents of the register corresponding to can be saved.

The present invention is not limited to the above embodiment. Here, the "save-background instruction" was explained as being executed for all general-purpose registers, but after specifying the registers to be saved, "save-backgroun"
It is also possible to select the register to be saved by giving "d instruction". Further, in the embodiment, the memory address register 13 for register saving and the memory address register 10 for normal data saving are separate, and the data register 15 for register saving and the data register 9 for normal data saving are also provided. Although they are separate, the hardware amount may be reduced by sharing them under a certain constraint condition. It is also possible to read the data and the flag from the register file 3 and control the data storage by the flag by using the associative memory corresponding to the register. Needless to say, not only the contents of the general-purpose registers are saved, but also the saving process may be performed for various register groups for restoring the context. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] According to the present invention as described above, the contents of the registers are sequentially saved in the background processing with respect to the execution of the program. In addition, the processing can be simplified and the processing can be substantially eliminated. Therefore, the context switching can be performed very efficiently. Further, since the storage of the register contents is controlled by using the flag, there is a practically great effect that the register contents can be efficiently saved without causing waste of processing.

[Brief description of drawings]

FIG. 1 shows a register saving method according to an embodiment of the present invention. FIG. 1 is a diagram schematically showing an internal configuration of a central processing unit configured by applying the embodiment method, and FIG. FIG. 3 is a diagram showing a program example for register saving processing used in the example method, and FIG. 3 is a diagram showing a procedure flow of register saving processing in the example method. 3 ... Register file (RF), 4 ... Arithmetic operation unit (ALU), 5 ... Controller (CONT), 6 ... Memory (MRY), 7 ... Memory address controller (MCONT) 12 ... Counter (CTR) ), 13 ... Data register (MDRR), 14 ... Address controller (ACONT), 15 ... Address register (MARR).

Claims (1)

[Claims] 1. A program instruction sequence in which a background save instruction and a save area address are designated at the beginning of a program including a subroutine, and a program instruction sequence in which a multiple save instruction and a save area address are designated immediately before the subroutine in the program is sequentially performed. A method for saving registers of a computer to be executed, wherein a plurality of registers for holding information necessary for executing a program are each provided with a flag that is reset when the contents of the register are updated by executing the program. When executing the background save command, the presence or absence of a reset flag is sequentially checked, and if there is a reset flag, the contents of the register are stored in the memory according to the save area address, and this storage is performed. Each process that sets the flag when In parallel with the execution of the program from immediately after the background save instruction to immediately before the multiple save instruction, the free time that does not hinder the execution of the program is used, and when the multiple save instruction is executed, It is characterized in that the presence or absence of a reset flag is sequentially checked, the contents of the register are stored in the memory according to the storage area address when there is a reset flag, and the flag is set when the storage is successful. How to save registers.