JPH0640308B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to an information processing apparatus capable of processing a first-order predicate logical language at high speed.

(2) Prior Art In recent years, there has been proposed a first-order predicate logical expression which regards a predicate logical expression as a program and a calculation of proof. For example, if the first-order predicate logic language is limited to the Horn clause, PROG [Kowalski, Kowalski,
R .: “Predicate Logic as Programming Language”, Pro
c-IFIP 74, pp.569-574 (1974)], etc. have been developed.

PROLOG has been attracting attention as a language for the next-generation computer due to its non-deterministic processing and its parallelizability, but its execution procedure is realized by a trial-and-error control mechanism called back-tracking, and this back-tracking is currently used. The king control mechanism has not yet been realized by hardware, but is realized by software, and most of the program execution is a control overhead by this software, and a practical processing speed cannot be obtained.

For this reason, some proposals have been made as hardware for executing PROLOG, but the effect of parallel processing is small in spite of the complicated configuration, and the synchronization of variable values is unsolved. There was a problem.

(3) Object of the invention The present invention has been made in view of the above-mentioned problems of the prior art. The object of the invention is to process a first-order predicate logical language in parallel,
An object of the present invention is to provide an information processing device that reduces the overhead of backtracking and performs high-speed processing.

(4) Example Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

As Figure 1 illustrates the apparatus of this embodiment is a plurality of unit processing means connected to the common bus 3 is a data transmission unit input and output processing unit 1 and the n unit processing apparatus 2 _1, 2
_-2 , ..., 2-n. The common bus 3 is used to load a program into a unit processing device (hereinafter abbreviated as UPm) 2-m, or an input / output processing device (hereinafter abbreviated as IOP) 1
And UPm (2-m) are used for communication between each other. In the apparatus of this embodiment, as a communication method between the processing apparatuses, a transmission right cycle method is used in which the transmission right is sequentially transferred to each processing apparatus by the control line 4 which is the transmission right transfer means.

Also, 5 is a keyboard (KB) for the operator to input a question,
6 is a display device (CRT) for displaying the progress of processing, and 7 is an external storage device (hereinafter referred to as DIS) in which programs and the like are stored.
Denoted by K) and 8 are printers for outputting processing progress, processing results, and the like.

Next, details of IOP1 are shown in FIG. 5-8 in the figure is the first
The configuration is the same as that shown in the figure.

The functions of the IOP 1 are mainly for accepting questions from the operator, outputting (displaying) answers to the questions, loading programs, etc. The CPU 10 and the memory 12 are connected to the local bus 11 connected via the common bus 3 and the interface 13. ,
The I / O control unit 50 is connected to the I / O control unit 50.
A keyboard 5 and a CRT 6 are connected to the. A DISK 7 and a printer 8 are also connected to the local bus 11. The interface 13 is connected with a control line 401 to the _first UP ₁ (2-1) corresponding to the control line 4 in FIG. ₁ and a control line 4n0 from the last UPn (2-n) for transmission. The right transfer means is controlled.

Next, details of UPm (2-m) are shown in FIG.

The function of UPm (2-m) is to receive a target and return an answer to the target. Each UPm (2-m) has a UPCPU 2m0 connected to a local bus 2m1 connected to a common bus 3 via an UP interface 2m3. It has a configuration in which the UP memory 2m2 is connected, and the UP interface 2
Control line 4 ( _m-1 ) from the previous UP _{m-1 for} m3
m and control line 4m ( _{m + 1} ) from the next UP _{m + 1}
With and.

However, when m = 1, the previous UP (m = 0) is IOP1.
When m = n, the next UP (m = _{n + 1} ) is I
It is OP1.

The details of the interface (13, 2m1) with the common bus 3 in each processing unit (IOP, UPm) are shown in FIG.

The interface 13 and the UP interface 2m1 have the same configuration, and the UP interface 2m1 will be described below as an example.

The interface unit is the bus control unit 31, the transmission buffer 3
2, a reception buffer 33, a common switching unit (hereinafter referred to as SWC) 34, a local switching unit (hereinafter referred to as SWL) 35,
An UP number setting unit 36 that sets the own UP number, a comparison unit 37 that compares destination designations, and a gate 38.

In the bus control unit 31, the control line 4 (from the previous UP _m-1
m-1 ) m is input, and the control line 4m ( _{m + 1} ) to the next UP _{m + 1} is output. However, IOP1
Before UP is UPn (2-n) and the next UP is UPn
₁ (2 _1).

Next, the data transfer between the processing devices via the common bus 3 will be described.

FIG. 5 is a diagram showing a communication format of a data frame at the time of data transfer, and 51 is a destination U of the data frame.
If the UP number is negative at the destination indicating the P number, no destination is specified and all UPs receive this data frame. Reference numeral 52 is a sender indicating the sender UP number, and 53
Is a target number, 54 is a function code, “Y” is the answer to the target “YES”, “N” is “NO”,
A "?" Means that this data frame is the target. Further, since "L" indicates that the transmitted data frame is a program sentence, this data frame is loaded as a program sentence in the memory (12, 2m2) which is the program sentence holding means.

Further, 55 is a predicate, 56 is communication data main body TEXT, 57
Is an EOF indicating the end of data.

For data transmission / reception, each processing device to which the transmission right has been transferred from the control line transmits / receives data to / from the common bus 3 via the interface (13, 2m3).

The operation of this interface (13, 2m3) will be described first with reference to the flow chart of FIG.

Taking the interface 2m3 of UPm as an example, it is increasingly monitored in step S1 whether the transmission right has been transferred from the previous UP, that is, UP _m-1 through the control line 4 ( _m-1 ) m, and the transmission right is transferred. If not, proceed to step S2,
It is checked whether or not there is a data frame (received data) shown in FIG. 5 on the common bus 3. If there is no data frame to be received, the process returns to step S1 and waits for the transmission right to be transferred. If there is a data frame on the common bus 3, the process proceeds to step S3, where the destination 51 shown in FIG.
The comparison unit 37 compares the set value in the number setting unit 36, that is, whether the data frame is addressed to its own UP, or whether the destination 51 is negative and there is no destination designation. If the destination 51 of the comparison in the comparison unit 37 is addressed to its own UP or is negative, the data frames on the common bus 3 are sequentially stored in the reception buffer 33 via the gate 38 in step S4. Destination 51 is positive and other UP
In the case of addressing, the gate 38 is not permitted and the data frame is not stored in the reception buffer 33 and the process returns to step S1.

Control line 4 ( _m-1 ) from UP _m-1 at step S1
When the transmission right is transferred by m, the process proceeds to step S5 to check whether there is data in the transmission buffer 32 or the reception buffer 33. If there is data, the SWC 34 is transmitted to the transmission buffer 32 and the common bus 3 in step S6. SWL35 to receive buffer and local bus 2
Switch so that m1 is connected. And step S
7, S8 and steps S9, S10 are processed in parallel.

First, in step S7, the UPCPU2 of the transmission buffer 32
When the data frame stored by m0 is transmitted to the common bus 3 and all the data in the transmission buffer 32 is transmitted, the contents of the transmission buffer 32 are cleared in step S8 and the process proceeds to step S11. At the same time as step S7, if there is a received data frame in the reception buffer 33 at step S9, this reception data frame is transferred to the UP memory 2m2, and the reception buffer 33 is cleared at step S10 to prepare for the next data frame reception. And step S11
Proceed to.

In step S11, the SWC 34 and the SWL 35 are switched, the reception buffer 33 is connected via the common bus 3, the comparison unit 37, and the gate 38, and the local bus 2m1 and the transmission buffer 32.
And connect the control line 4 at step S12.
Transfer the transmission right to the next UP _{m + 1} by m ( _{m + 1} ),
Return to step S1.

When the transmission right is transferred in step S5, the transmission buffer 3
If there is no data in both 2 and the reception buffer 33, the process proceeds to step S12 and immediately transfers the transmission right to UP _{m + 1} .

In the above description, the UPm interface 2m1 is taken as an example, but the operation is the same for other UP and IOP1 interfaces.

Next, the loading of the program from IOP1 to each UPn will be described.

First, the IOP 1 reads the program statement recorded in the DISK 7 into the memory 12. Then, the first program statement is transferred to the transmission buffer of the interface 13 (corresponding to 32 in FIG. 4), and the transmission right transfer from UPn is awaited. Then, when the transmission right is transferred, it is transmitted to the common bus 3.
When the transmission is completed, the transmission right is transferred to UP _1, and if there is the next program statement, the program statement is sent to the transmission buffer, waiting for the transmission right to be transferred. Send a program statement. By repeating this, all program statements are sequentially transmitted.

In this case, the data frame format sets the program statement number as the destination UP number in the destination 51, and the FC5
4 is set to "L".

The program statement sent out on the common bus 3 is received by each UP designated by the destination 51, and is sent as a program by the U
It is loaded into the P memory 2m2.

When the program sentence is loaded in each UP corresponding to the sentence number, the operator waits for input of a question.

When a question is input, the IOP 1 executes logical operation processing on the question and outputs the (temporary) target to the common bus 3. When the question is a conjunctive (logical product) of predicates, the first predicate is the immediate goal, and if the unifac- tion for this goal is successful, the result is substituted into the original question, and the next The above predicate is used as the next goal, and the same processing is performed until there is no next goal. The question is true if the process proceeds until there are no more predicates, and the uniform result at that time gives the value of the variable in question. When a question consists of one predicate, it is a special case of collocation.

The target data format transmitted by the IOP1 is a destination 51 is negative, a source 52 is "0", a target number 53 is "0", an FC54 is "?", A predicate 55 is a target predicate, T
EXT56 is the target argument. The IOP 1 creates this data frame and sends it to the common bus 3 when the transmission right is transferred.

The relationship between the question, the goal, and the corresponding data frame is held in the execution history list of the memory 12, which is history holding means, to prepare for the subsequent execution processing of the program statement.

The target sent to the common bus 3 is received by all the UPs, and each UP transfers the target to the work area of the UP memory 2m2 from the reception buffer 32 except when it receives the transmission right. Performs pattern matching by comparing the predicate (which may be multiple) with the head of its own program statement. This matching is performed by the algorithm of the uni-facility in the logic programming language.

When the pattern matches, when the corresponding sentence is a fact, FC54 is set to "Y" and the matched argument value is T.
Write it in the transmission buffer 32 as EXT56. At this time,
The destination 51 is the number of the UP (or IOP) that issued the target, and the source 52 is the set value in its own UP number setting unit 36.

When the sentence in charge is a rule, the logical operation processing is executed on the body of the sentence, and the (immediate) target is written in the transmission buffer 32. This logical operation processing is the same as the processing for the question described above. At this time, the transmission source 52 is its own UP number, the target number 53 is the target UP (stack) number, the FC 54 is “?”, The predicate 55 is the predicate, and the TEXT 56.
Is an argument. Then, when the next transmission right is received, it is output to the common bus 3.

The relationship between the transmitted / received target and the corresponding data frame is held in the execution history list of the memory 12, which is history holding means, to prepare for the subsequent execution processing of the program statement.

When the received data has a reply to its own UP, the target corresponding to the reply is searched by the inquiry of the target number in the execution history list which is the history holding means, and the suspended logical operation processing is restarted. . If FC54 is "Y", the value of the univariable variable is substituted, and if there is a next target, it is written as communication data in the transmission buffer 32, and if not, the target that has become the basis of the logical operation processing is issued. The reply to the UP is written in the transmission buffer 32 as communication data in which FC54 is "Y". When a target in charge is further received while a logical operation is on hold, the pending logical operation, which is the execution history of the logical operation process that executed the logical operation halfway, is placed in a list, that is, on the hold. The execution history list holding the execution history of the logical operation being executed is recorded, and a new target logical operation process is executed. In a computational model that considers a proof in first-order predicate logic as execution of a program, the list of logical expressions generated during the proof becomes the execution list of the program.

In this embodiment, each target is structured so that it can be referred to by the target number, so that it is possible to easily refer to the proof result obtained by another processor. The execution history list of the target (logical operation processing), which is the history holding means, identifies the target by the target number (data format, target number 53), and when a reply is received, the target is executed. Search the history list and restart the process.

In the above processing, one UP handles a plurality of data frames for both transmission and reception. This is because if multiple targets are pending, multiple replies may be returned at the same time while the transmission right is transferred.

By repeating the above process, when the logical operation processing of IOP1 is completed, IOP1 outputs the answer (the result of the uniformization to the target) to CRT6.

Details of the logical operation processing by the IOP 1 described above will be described below with reference to the logical operation processing execution flow chart of FIG.

First, in step S20, the question from the keyboard KB5 is read to obtain the leftmost predicate expression of the question sentence. Then, in step S21, this predicate expression is written in the transmission buffer as a target for each UP, and is sent to the common bus 3 when the transmission right is acquired. The data format at this time shows that the destination 51 is negative and that the destination is undetermined, and the source 52 is IO.
The target number 53 is "0" indicating P1, "0" at the beginning, and FC54 is "?" Meaning the target.

Then, when the failure of the uniformity to the target is received not by the time-out method but by the answer “N”, the reception confirmation from each UP is received in step S22. In the time-out method of determining "N" when the answer of "Y" is not received even after a lapse of a certain time, reception confirmation and the following processing are unnecessary.

Then, each time the reception confirmation from the UP is received, the UP number for the target number is incremented by one. Then, in step S23, it is checked whether or not the UP number for the target number is "0", and if it is "0", the process proceeds to step S31 described later.
If it is not "0", the process proceeds to step S25 to receive the answer from UP. Then, the UP number for the target number is decremented by 1, and if the answer is "YES", it is added to the answer list for the target number in the execution history list which is the history holding means.

After that, the program goes to step S26 to check if there is an answer in the answer list, and if there is an answer in the answer list, go to step S27 to check if there are any remaining questions. If there are no remaining questions, go to step S29 to send the answer to CRT6. Display and end the logical operation processing. Step S if there are any remaining questions
At 28, the first answer (value of the variable) in the answer list is substituted into the remaining question sentence to make the next question, the target number is incremented by 1, and the process returns to step S20. The answers that have been entered this time are deleted from the answer list.

If there is no answer in the answer list in step S26, the process proceeds to step S30 to check whether the UP number for the target number is "0". If it is not "0", the process returns to step S24 and waits for an answer. If the number of UPs is "0", it means that there is no answer to the target, and the process proceeds to step S31.

In step S31, it is checked whether there is a previous question. This is determined by whether the target number is "0". Then, if the target number is "0" and there is no previous question, the process proceeds to step S32, the answer NO is displayed on the CRT 6, and the process ends. The target number is not "0" (that is, not the original question)
At this time, if the UP number for the target number is "0" and there is no answer in the answer list, the process proceeds to step S33, the target number is decreased by 1, the previous question is returned, and the step S2 is performed.
Proceed to step 6 and check the answer list. If there is no further answer here and the number of UPs is "0", the process sequentially returns until the target number becomes "0".

Here, the IOP1 is described as an example, but each UP also performs the same processing on the other UP and executes the logical operation processing.

Next, the execution of the target when the target is received will be described with reference to the flow charts of FIGS. 8 (A) and 8 (B).
FIG. 8 (A) is a flow chart showing the target reception processing. In step S50, the target frame from IOP1 or another UP has a negative destination 51, and therefore all the common buses 3
The data is received by the connection device and stored in the reception buffer 33.
Then, it is transferred to the UP memory 2m2, and it is checked in step S51 whether or not the target predicate and the predicate of the program statement received by the own UP match. If they do not match, the process proceeds to step S52 to clear the received target and returns to step S50 to wait for the next target to be sent. If the target predicate matches with the target predicate, the process proceeds to step S53,
The received target is added to the target list of the UP memory 2m2 which is a history holding unit. Then, in step S54, a reception confirmation response is transmitted to the transmission source. The data frame at this time has the same destination 51 as the source 52 of the received frame,
The source 52 is the own UP number of the UP number setting unit 36, and the target number 53 and FC 54 are the same as the received frame. Then, the process returns to step S50.

The targets received in this way are sequentially added to the processing waiting target list.

If your self-confidence is your goal, write it directly in the goal list without communicating.

Next, the process of reading the target list and executing the target will be described with reference to the target execution flow chart of FIG. 8 (B).

First, in step S60, the target list is read. (The read target is deleted from the target list.) Then, in step S61, the head argument of the sentence in charge and the target argument are matched, and in step S62, it is checked whether or not the matching has been achieved. This matching is performed by the algorithm of the uni-facility in the logic programming language.

When the argument matching cannot be taken, the process is impossible, so the answer is NO in step S63, the destination 51 is the target sender number, the sender is the self UP number, and the process returns to step S60 to return to the next target list. Take action on the goal.

When the matching of the argument is taken in step S62, the process proceeds to step S64, and it is checked whether the sentence in charge is a fact. If the sentence is a fact, in step S65 the sentence is directly assigned as a value to the variable along with the argument, and in step S66 the answer is Y.
Other than ES, the same format as step S63 is returned. Then, the process returns to step S60.

If the fact is not true in step S64 (the part in charge is a rule), the process proceeds to step S67, the matched argument value is substituted into the main body, and a question sentence is generated. Subsequently, in step S68, the question sentence is subjected to the same processing as the logical operation processing of IOP1 shown in FIG. 7, and if the answer obtained in step S69 is "Y", the value of the obtained variable is obtained. If the answer is “N”, then NO is sent. The destination and source in this case are the same as in step S63.

In this way, in executing the target, the UP that responded with a receipt confirmation
Each will execute and return an answer, which will be the goal that cannot be answered without confirmation of receipt.

As a result, the answer to a certain goal is recorded in a multiple answer list, and if there is backtracking, the next answer can be immediately retrieved from the answer list and the next answer can be executed.

The parallel processing in the present embodiment as described above is particularly effective in a program having OR parallelism as described below. That is, for example, when there are a plurality of closes each having the predicate P in its head, the sequential processing sequentially checks the closes one by one, and therefore the number of closes takes time. On the other hand, in this embodiment described above,
Since this processing can be executed in parallel, the time required for this is constant regardless of the number of closes.

It is known that in the execution of the first-order predicate logic program, most of the calculation time is spent on the processing of the unifacility, and the time required to search the predicate is relatively short. In the present embodiment, the search for the predicate is performed by the so-called broadcast transmission, but the frequency of data transmission / reception in the entire process is small (that is, since most of the time is uniformization), there is a communication overhead. Is not a problem for the overall processing.

Also, not all processors are active, and there are quite a few processors that are waiting for the answers of other processors, so the communication volume does not reach the exponential order of the number of processors.

The great advantage of allocating only one close to one processor is that the effect is sufficiently brought out when the frequency of communication is low as a result and OR parallelism is required as described above. On the other hand, in the method of allocating multiple closes to one processor, the communication volume should be reduced if there are necessary closes in one processor, but in general, a program cannot be configured in this way. Also, if all the processing is performed by one processor, parallelism does not occur and OR parallelism cannot be utilized. Therefore, the present embodiment described above is effective in that OR parallel can be drawn out.

(5) Effects of the Invention As described above, according to the present invention, since the processing of each sentence of the first-order predicate logic language such as PROLOG is allocated to each processing unit in advance, the predicate search and the program statement are performed. In addition to reducing the overhead for allocation of data, high-speed processing is possible, and the unit processing on the receiving side is also performed when data is transferred from the unit processing unit to another unit processing unit without specifying the destination with a fixed priority. By configuring the processing data to be selected by means, selection of which program statement is in which unit processing means is unnecessary, and further efficiency can be further improved.

Also in this case, it is possible to provide an information processing apparatus that does not cause an explosion in the number of processes and has improved processing efficiency without providing a special control structure for parallel processing.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a block configuration diagram showing details of IOP of the embodiment apparatus shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a block configuration diagram showing details of UP of the apparatus of the present embodiment, FIG. 4 is a block configuration diagram showing details of an interface section of the apparatus of the present embodiment, and FIG. 5 is a data frame in case of data transfer of the apparatus of the present embodiment. FIG. 6 is a flow chart showing the operation of the interface section shown in FIG. 4, FIG. 7 is a flow chart showing the logical operation processing of the apparatus of this embodiment, and FIG. FIG. 8B is a flow chart showing the target receiving process of the apparatus of this embodiment, and FIG. 8B is a flow chart showing the target executing processing of the apparatus of this embodiment. In the figure, 1 ... IOP, 2m ... UPm, 3 ... common bus, 4,401-4n1 ... control line, 5 ... keyboard KB, 6 ... CRT, 7 ... DISK, 8 ... printer, 10 ... CPU, 11, m1 ... local bus, 12 ... memory, 13, 2 m3 ... interface, 31 ... bus control unit, 32 ... transmission buffer, 33
...... Reception buffer, 34 ...... SWC, 35 ...... SWL,
36 ... UP number setting section, 37 ... comparing section, 38 ... gate, 50 ... I / O control section, 2m0 ... UPCPU,
2m2 ... UP memory.

Claims (1)

[Claims] 1. An information processing apparatus comprising: a plurality of unit processing means for executing a program statement of a first-order predicate logical language; and a transmission right transfer means for sequentially transferring transmission rights to the unit processing means according to a predetermined priority. The unit processing means includes a data transmission means for transmitting and receiving data from the unit processing means that has acquired the transmission right to another arbitrary unit processing means, and a statement holding means for holding the program statement. And a history holding unit that holds the execution history of the program sentence held in the sentence holding unit to independently execute the program sentence of the first-order predicate logical language, each program of the first-order predicate logical language Allotment of sentence processing is assigned to the plurality of unit processing means in advance, the unit processing means holds the assigned program sentence in the sentence holding means, and each of the unit processing means performs the program processing. The information processing apparatus characterized by a first-order logic language and enables parallel distributed processing by emitting questions and answers which result from executing the ram to another unit processor.