JPH0640277B2 - Pattern matching circuit on the frequency axis - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pattern matching circuit on a frequency axis in a pattern matching circuit of a voice recognition device, and in particular,
The present invention relates to a pattern matching circuit that uses features by linear prediction (LPC) analysis.

(Prior Art) As a conventional pattern matching circuit on the frequency axis, a band pass filter (BPF) is used to handle the frequency.
There is one that performs pattern matching using.

(Problems to be solved by the invention) However, in the pattern matching circuit on the frequency axis using the BPF, (i) it is difficult to accurately handle the pattern on the frequency axis, (ii) the filter However, there is a problem that the scale of the circuit becomes enormous due to the order, accuracy, and so on.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a frequency-axis pattern matching circuit capable of performing accurate pattern matching and having a simple circuit configuration.

(Means for Solving Problems) In order to solve the above problems, the pattern matching circuit on the frequency axis of the present invention includes (a) a first fixed value sequence corresponding to the value of a parameter that determines the frequency conversion amount. Has a first storage means for storing, and performs frequency conversion by a product-sum operation of the linear prediction coefficient of the input pattern and the first fixed value sequence, and
A first circuit for calculating a distance from a linear prediction coefficient of a standard pattern subjected to frequency conversion in advance, (b) having a second storage means for storing a second fixed value sequence corresponding to the value of the parameter, A second circuit for calculating the amount of change in the frequency-converted linear prediction coefficient with respect to the parameter by sum-of-products calculation of the linear prediction coefficient of the input pattern and the second fixed value sequence;
(c) Updating the parameters so that the distance is minimized based on the outputs of the first circuit and the second circuit, and outputting a pattern matching residual on the frequency axis based on the minimum distance. The circuit of FIG.

(Operation) According to the present invention, since the pattern matching circuit on the frequency axis is configured as described above, the technical means operates as follows. The first circuit (for example, a frequency conversion / distance calculation circuit to be described later) uses the first prediction means corresponding to the linear prediction (LPC) coefficient of the input pattern and the parameter value set by the third circuit. The frequency-converted LPC coefficient is calculated by the product-sum operation with the first fixed value sequence of, and the distance from the frequency-converted standard pattern LPC coefficient is calculated and output. On the other hand, at the same time, in the second circuit, the sum of products operation of the LPC coefficient of the input pattern and the second fixed value sequence from the second storage means corresponding to the value of the parameter set by the third circuit. Thus, the change amount of the frequency-converted LPC coefficient for the parameter is calculated and output. The third circuit (for example, the residual detection circuit, the α update circuit, the determination circuit, and the switch) minimizes the distance based on the distance output from the first circuit and the change amount output from the second circuit. Thus, the parameters of the first and second storage means are updated. As a result, the first and second
The storage means outputs the first and second fixed value sequences corresponding to the updated parameter values. When the updated calculation result becomes the minimum, the residual based on the minimum distance is output as the residual on the frequency axis. In this way, the storage means has the first and second fixed value sequences corresponding to the parameter values, and the frequency-converted LPC coefficient, distance and Since the pattern matching on the frequency axis is performed by calculating the amount of change and adaptively controlling the parameters, the circuit configuration can be simplified and downsized, and the pattern matching on the frequency axis can be performed accurately. Is possible.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 is a circuit diagram of a pattern matching circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram explaining the principle of the present embodiment. 3 and 4 are circuit diagrams for explaining the principles of the frequency conversion circuit and the .alpha.-update change amount detection circuit, respectively.

First, the principle of the present invention will be described with reference to FIG. In the figure, 1 is an input terminal of an LPC coefficient of an input signal (input pattern), 2 is a frequency conversion / distance calculation circuit, 3 is a change amount detection circuit for α update, 4 is a residual detection circuit, and 5 is an α update circuit. , 6 is a decision circuit (DEC), 7 is a switch (SW), 8 is an output terminal, 9 is an input terminal for inputting an LPC coefficient of a reference signal (standard pattern), and 10 is a frequency conversion circuit. Time series of LPC coefficient of input signal from input terminal 1 FIR in which the delay element part of the FIR filter (acyclic filter) with tap coefficient is replaced by a first-order all-pass filter
It passes through a filter (FIG. 3), that is, a frequency conversion circuit of the frequency conversion / distance calculation circuit 2 which performs frequency conversion corresponding to a parameter that defines an all-pass filter
Output impulse response To get

Also, the time series of the LPC coefficient of the reference signal The frequency conversion circuit performs only the frequency conversion To get At this time, the parameter defining the all-pass filter is α _O , which is a fixed value.

Next, in the distance calculation circuit of frequency conversion / distance calculation circuit 2, LPC coefficient after frequency conversion The distance Is output.

Also, at this time, when moving the parameter α Represents the change amount of Obtains the impulse response g from the .alpha.-updating change detecting circuit 3 including an FIR filter (FIG. 4) similar to the frequency converting circuit.

Where the distance The parameter α is sequentially updated so as to minimize. The parameter α and the distance d when updated n times are α (n), Then, the updated parameter α (n + 1) is Given in. This calculation is performed by the α update circuit 5. The initial value of α is the LPC coefficient of the reference signal. Is the α _O used when the frequency was converted.

When the parameter α (n) and the updated parameter α (n + 1) become | α (n + 1) / α (n) | <ε (ε is a threshold value) by the determination circuit 6, the residual detection circuit 4 is the switch 7 for the calculation result of the following formula
Output via.

This d _e is the input LPC coefficient And reference LPC coefficient This is the residual when the frequency control is adaptively performed so that the distance is minimized, that is, the residual when the pattern matching is performed on the frequency axis.

The principle of the frequency conversion circuit in the frequency conversion / distance calculation circuit 2 will be described with reference to FIG.

11 is a parameter α input terminal that determines the frequency conversion amount, 12
Is a unit impulse train {1, 0, ... 0} input terminal, 13 _O ~ 1
3 _P is the input signal LPC coefficient input terminal, 14 _{O to} 14 _P are multipliers,
15 _I to 15 _P are all-pass filters, 16 _{I to} 16 _P are adders, 17
Is an output terminal.

The all-pass filters 15 _I to 15 _P are 111 adders and 11
It consists of 2 delay devices, 113 multipliers, 114 multipliers and 115 adders.

To describe the operation of the frequency conversion circuit configured as above, first, the fixed value α is input from the input terminal 11,
Impulse train (1, 0, ... 0) from input terminal 12 is P + 1
Sample input. Therefore, the point A becomes a unit impulse train, and the points B, C, ... E become a fixed value train consisting of a fixed value α and a unit impulse train.
Multipliers 14 _O , 14 _I ..., 14 _P and adders 16 ₁ , 16 ₂ calculate the sum of products of the fixed values at points C, ... E and the input signals input from terminals 13 _O , 13 _I ..., 13 _P. ..., carried out using a 16 _P, the output terminal 17
Is output from. As you can see from this, A, B,
Since points C, ... E are fixed value sequences, frequency conversion can be performed by a simple product-sum operation using a ROM circuit.

LPC coefficient for parameter α Change of The change amount detection circuit 3 for updating α for obtaining can be configured as shown in FIG. 4, for example. That is, it can be configured by providing the differential filter 19 in the preceding stage of the FIR filter 18 configured similarly to the frequency conversion circuit. Since the output of this differential filter 19 is a fixed value corresponding to the input unit impulse and the input parameter α, the amount of change is calculated by a simple product-sum operation using the ROM circuit, similar to the frequency conversion circuit. Can be asked.

The pattern matching circuit on the frequency axis of FIG. 1 constructed based on the principle of the present embodiment described above will be described. In the figure, the same reference numerals as those in FIG. 2 denote the same components. The memory (MEM) 10a stores the reference signal.
LPC coefficient LPC coefficient with frequency conversion Is calculated and stored in advance. Since distance calculation is performed, Is output with. The frequency conversion / distance calculation circuit 2 includes a parameter memory (MEM) 21, a multiplier (MPY) 22, an adder (ADD) 23, and a register (REG) 24. Also,
The α update change amount detection circuit 3 is a parameter memory (ME
M) 31, multiplier (MPY) 32, adder (ADD) 33 and register (RE
G) 34.

The residual detection circuit 4 comprises a multiplier (MPY) 41, an adder (ADD) 42 and a register (REG) 43. The α updating circuit 5 is composed of multipliers (MPY) 51, 54, adders (ADD) 52, 55, 58, registers (REG) 53, 56, 59 and a divider (DIV) 57.

Next, the operation of this embodiment will be described.

First, the time series a of the LPC coefficient of the input signal is input from the input terminal 1 to the frequency conversion / distance calculation circuit 2. This circuit 2
Is a fixed value sequence output from MEM 21 (created from parameter α and the impulse system as described above) and the input LPC coefficient, which is performed by MPY 22, ADD 23, and REG 24.
At this time, the reference data stored in the MEM 10a and frequency-converted If is entered as the initial value in REG 24, the result of the above product-sum operation is the distance Becomes

At the same time, the LPC change amount detection circuit 3 is connected to the LPC.
The coefficient is input. In this circuit 3, the product-sum calculation of the fixed value sequence output from MEM 31 and the input LPC sequence is performed by MPY32, ADD33.
And REG34, change amount Is output. The initial value of REG34 at this time is "0" 20.

Next, in the residual detection circuit 4, the α update change amount detection circuit 3
Distance from While squared the time series of MPY 41 with ADD 42 and REG 43 (initial value “0”), the residual sum d _e is obtained. However, if the value of α does not converge, the residual does not become a true matching.
This control will be described later.

Next, in the α update circuit 5, the distance Output of change amount detection circuit 3 for time series and α update Multiply and by multiplying and by MPY51, ADD52 and REG53 Ask for. At the same time, the output of the change amount detection circuit 3 for α update Squared with MPY54 and summed with ADD55 and REG56 Ask for. Then with DIV57 Then, add the previous α (initial value at start) stored in REG59 with ADD58 to obtain a new α value.

The determination circuit 6 determines whether or not the value of α obtained in this way has converged. If it is determined that the value of α has not converged, the values of MEM21 and MEM34 are changed using the updated value of α. At this time α
If the range of the value of is specified, it is sufficient to enter the value calculated for each selectable value of α in each memory.
MEM21 and MEM34 can be achieved by ROM circuits.

In this way, the above operation is repeated until the value of α converges. When a determination circuit 6 converges to determine, closes switch 7 for output control, output d _e of this time is calculated by determining the value of α residual detection circuit 4, the pattern matching on the frequency axis Is output from the output terminal 8 as the residual of.

(Effect of the Invention) As described above in detail, according to the present invention, the storage means has first and second fixed value sequences corresponding to the values of the parameters that determine the frequency conversion amount, and these fixed value sequences are stored. And the LPC coefficient as the feature quantity
Since the pattern matching on the frequency axis is performed by calculating the LPC coefficient, distance, and the amount of change and adaptively controlling the parameters, the circuit can be made simpler and smaller, and more accurately on the frequency axis. Pattern matching can be performed. Therefore, it is possible to provide a voice recognition device with improved recognition at low cost.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a block diagram explaining the principle of the present embodiment, and FIG. 3 is a circuit diagram explaining the principle of a frequency conversion circuit of the present embodiment. FIG. 4 is a circuit diagram for explaining the principle of the .alpha.-update change amount detection circuit of this embodiment. 1 ... Input terminal, 2 ... Frequency conversion / distance calculation circuit, 3
.. .alpha. Update change amount detection circuit, 4 .. residual error detection circuit, 5
...... α update circuit, 6 …… decision circuit (DEC), 7 …… switch (SW), 8 …… output terminal, 10a, 21, 31 …… memory (MEM), 22, 32, 41, 51, 54 ...... Multiplier, 23, 32, 4
2, 52, 55, 58 ... Adder, 24, 34, 43, 53, 56, 59 ...
… Register (REG), 57 …… divider.

Claims (1)

[Claims] (A) A first storage means for storing a first fixed value sequence corresponding to a value of a parameter that defines a frequency conversion amount is provided, and a linear prediction coefficient of an input pattern and a first fixed value sequence are provided. A first circuit for performing frequency conversion by a product-sum operation of (1) and calculating a distance from a linear prediction coefficient of a standard pattern that has been frequency-converted in advance, (b) a second fixed value sequence corresponding to the value of the parameter A second circuit having a second storage unit for storing the linear prediction coefficient of the input pattern and a second fixed value sequence, and calculating a change amount of the frequency-converted linear prediction coefficient with respect to the parameter. , (C) The parameters are updated so that the distance is minimized based on the outputs of the first circuit and the second circuit, and the residual of pattern matching on the frequency axis based on the distance that is the minimum is output. A third circuit, and Pattern matching circuit on the frequency axis, characterized in that.