JPH0638577B2 - Signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as MO
S Tr.)) In the integrated circuit using the signal generation circuit.

[Conventional technology]

FIG. 3 shows an integrated circuit using N-channel MOS Tr., In particular, a conventional signal generation circuit in a dynamic random access memory (RAM). Generally, in an integrated circuit, it is necessary to generate many signals from one external input signal, so that the signal generating circuits as shown in FIG. 3 are configured by cascade connection.

In FIG. 3, φ ₁₁ is an input signal, φ _p11 is a precharge signal for charging the connection point (node) to initialize the circuit, φ
₁₂ is an output signal. Further, 11 is a delay unit of the signal generating circuit, and 12 is a signal generating unit.

The input signal phi _11, is often output signal of the preceding stage of the signal generating circuit of the cascade connection is added, before the input signal phi ₁₁ is activated, each node of the signal generating circuit from Purichiyaji signal phi _{pi 1} Initialized, node N ₁₀₁
And N ₁₀₄ are set to the GND level, the nodes N ₁₀₂ and N ₁₀₃ are set to the high level, and the output φ ₁₂ is set to the GND level.

When the precharge signal φ _p11 goes to the GND level and the input signal φ ₁₁ goes from the GND level to the high level, the node N
_The capacitance C ₁₀₁ having ₁₀₄ and N ₁₀₅ at both ends is charged through the MOS Tr.Q ₁₀₆ by the input signal φ ₁₁ . Here MOS Tr.
The gate electrode of Q ₁₀₆ rises above the power supply voltage due to the self-boot strap effect. Therefore, the MOS Tr.Q ₁₀₅
As long as the voltage of the node N ₁₀₂ does not decrease, the MOS Tr.Q ₁₀₆ is conducting, and thus the node N ₁₀₂ of the capacitor C ₁₀₁ is charged with the maximum level voltage.

On the other hand, when the input signal changes from the GND level to the high level, the voltage of the node N ₁₀₁ changes from the GND level to the high level,
Therefore, the voltage of the node N ₁₀₂ drops to the GND level. The time at which the voltage of the node N ₁₀₂ , which is the output of the delay unit of the signal generating circuit, changes to the GND level, that is, the delay time can be set arbitrarily by selecting the size of the transistors Q _{101 to} Q ₁₀₄ .

When the voltage of the node N ₁₀₂ drops to the GND level, the node N ₁₀₃ becomes the GND level and the MOS Tr.Q ₁₀₆ becomes OF.
It becomes the F state, and the MOS Tr. Q ₁₀₈ and Q ₁₁₀ also become the OFF state.

The MOS Tr.Q ₁₀₇ , Q ₁₀₈ and the capacitor C _{101 form} a boot strap circuit, and when the MOS Tr.Q ₁₀₈ is turned off, the node N ₁₀₄ has a voltage higher than the power supply Vcc + V _TH . Since the gate electrode of the MOS Tr.Q ₁₀₉ is connected as a load transistor of the output driver section to the node N _104, MOS Tr.Q ₁₀₉ drives the output phi ₁₂ to the power supply voltage Vcc.

Here, the reason why this signal generating circuit delay unit is required is that it takes time to sufficiently charge the potential of the node N ₁₀₄ connected to one end of the capacitor C ₁₀₁ .

Therefore, in the conventional signal generating circuit as described above, the voltage of the node N ₁₀₂ becomes GND from the time when the input signal φ ₁₁ is applied.
Both the load transistor and the drive transistor of the output driver, Q ₁₀₉ and Q ₁₁₀ , are kept in the ON state until the time when the voltage drops to the level (see FIG. 4).

In particular, when the load of the signal generating circuit is large, it is necessary to have a large transistor capability of the MOS Tr. Q ₁₀₉ and Q ₁₁₀ to drive it, and if each transistor is in the ON state, a large current will be generated in the power supply Vcc. There was a problem that it would flow between the and GND.

[Problems to be solved by the invention]

In order to solve such a problem, it is necessary to surely turn off the drive transistor before the load transistor forming the output part of the signal generation circuit is turned on. However, such an operation cannot be performed with the configuration of the conventional signal generating circuit. That is, for example, the third
In the conventional signal generating circuit shown in the figure, if the gate signal of Q ₁₁₀ is φ _P11 , the following problems will occur.

Considering the time of resetting the output signal, at this time, before the load transistor of the output section is turned off, the drive transistor Q
There is a problem that ₁₁₀ is turned on because φ _P11 is activated and the load transistor and the drive transistor are simultaneously turned on in the output section, resulting in an increase in power consumption.

The present invention has been proposed in view of the problems of the above-mentioned conventional example, and an object thereof is to provide a signal generation circuit with low power consumption.

[Means for solving problems]

According to the present invention, a signal is generated by a signal generation circuit having a delay circuit in a cascade connection and generated by a signal generation circuit before the one signal generation circuit used after the second stage of the signal generation circuit group. And a circuit for deactivating the transistor that sets the potential of the output terminal to the ground potential before the transistor that connects the output terminal and the power supply in the output section of the one signal generation circuit is activated. , To obtain the provided signal generation circuit group.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram in which signal generating circuits according to an embodiment of the present invention are cascade-connected in two stages.

Reference numeral 21 denotes a signal generating circuit in the previous stage, 22 denotes a signal generating circuit in the next stage, φ ₂₁ is an input signal of the signal generating circuit 21, φ ₂₂ is an output signal of the signal generating circuit 21 in the previous stage,
Input signal, φ ₂₃ is the output signal of the next stage signal generation circuit 22,
φ _p21 and φ _p22 are precharge signals of the signal generating circuits 21 and 22, respectively.

In the embodiment, the node N ₂₀₂ which is the output of the delay unit of the signal generating circuit 21 in the previous stage is connected to the gate electrode of the drive transistor MOS Tr.Q ₂₂₀ of the output driver of the signal generating circuit 22 in the next stage.

Next, the operation of the embodiment circuit of FIG. 1 will be described with reference to the signal waveform diagram of FIG. The signal generating circuits 21 and 22 are first initialized by φ _p21 and φ _p22, and operate by applying the input signal φ ₂₁ to the signal generating circuit 21. The operation of the signal generation circuit 21 is the same as that of the conventional signal generation circuit (the third
The description is omitted because it is similar to FIG. Although the operation of the next stage of the signal generating circuit 22 is substantially the same, since the node N ₂₀₂ is the output of the preceding delay unit to the gate electrode of the MOS Tr.Q ₂₂₀ is connected, the previous stage circuit to the signal generating circuit 22 21
When the output signal φ ₂₂ is input from the GND level to the high level, the MOS Tr.Q _{220 is} almost in the OFF state. As a result, the ON-ON state of the MOS Tr. Q ₂₁₉ and Q ₂₂₀ disappears, and the power consumption can be greatly reduced.

Although the example of adding the signal of the delay unit at the preceding stage to the gate electrode of the drive transistor of the signal generating circuit has been shown in the embodiment, the invention is not limited to this. That is, another signal may be used as long as it is a signal that turns off the drive transistor of the output section before the load transistor of the output section of the signal generation circuit turns on. Further, the present invention is not limited to the signal generation circuit having the N-channel MOS Tr. Structure, but can be similarly applied to the P-channel MOS Tr. Structure or the CMOS structure.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the load transistor and the drive transistor of the output driver from being simultaneously turned on immediately before driving the output.
Useless power consumption due to ON-ON current between the power supply and ground can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram in which signal generating circuits according to an embodiment of the present invention are cascade-connected in two stages, and FIG. 2 is a signal waveform diagram for explaining the operation of the circuit of FIG. FIG. 3 is a circuit diagram of a signal generating circuit according to a conventional example, and FIG. 4 is a signal waveform diagram for explaining the operation of the circuit of FIG. 11 ...... delay unit, 12 ...... signal generation unit, 21 ...... pre-stage of the signal generating circuit, 22 ...... next stage of the signal generating circuit, phi ₁₁ to [phi] ₂₃ input and output signals of the ...... signal generating circuit (or their ), Φ _{p11 to} φ _p22 ...... Precharge signal of signal generation circuit, Q _{101 to} Q ₂₂₀ ...... MOS Tr., N _{101 to} N ₂₁₅ ...... Node (connection point).

Claims (1)

[Claims] 1. A first transistor connected between a first power supply terminal and an output terminal, a second transistor connected between the output terminal and a second power supply terminal, a first power supply terminal and a first transistor. A third transistor connected to the node, and a fourth transistor connected to the first node and the second power supply terminal
It has a transistor, an input signal terminal and a precharge signal terminal, and outputs a high level to the second node during the precharge period, and when the input signal is applied after the precharge period, the second signal is output.
Circuit means for outputting a low level to a node, a fifth transistor whose gate is connected to the first power supply terminal, and a gate which is connected between the input signal terminal and a third node and is the fifth transistor
A sixth node connected to the second node via a transistor
A first and a second signal generating circuit each including a transistor and a capacitor connected between the third node and the first node, wherein the first and third signal generating circuits are provided in the first signal generating circuit. The gate of the transistor is connected to the third node, the gates of the second and fourth transistors are connected to the second node, and the gates of the first and third transistors in the second signal generating circuit are connected to the third node. A gate of the fourth transistor is connected to the second node, and the output terminal of the first signal generating circuit is connected to the input signal terminal of the second signal generating circuit. A signal generating circuit in which a gate of the second transistor of the signal generating circuit is connected to the second node of the first signal generating circuit.