JPH0638510B2 - Method for manufacturing diode array - Google Patents

Description

The present invention relates to a method for manufacturing a diode array.

(Prior Art) Conventionally, a diode array having a repeating pattern has been proposed (Japanese Utility Model Publication No. 58-49452).

In this type of diode array, since the area per diode element and the interval between the elements are constant, the area of one chip changes depending on how many dots (also called bits) per chip.

In manufacturing this type of diode array, conventionally,
As shown in FIG. 3, a scribe line, that is, an isolation pattern for defining one chip area is formed before the diffusion process for the substrate 10 (FIG. 3 (A)), and thereafter, in this one chip area 11. Each diode element 13 was formed by performing diffusion, vapor deposition, etc. using a dedicated mask pattern corresponding to the number of dots to be accommodated (FIG. 3 (B)).

(Problems to be solved by the invention) Therefore, in the conventional method, when the number of dots per one chip area 11 of the diode array is changed, the glass mask pattern for forming the diode element 13 is formed in all steps. There was a problem that a diode array with the number of dots according to the design could not be manufactured unless changed.

Further, in the conventional method, as shown in FIG. 3 (C), when a wafer crack 14 occurs, this wafer cannot be used.

An object of the present invention is to provide a method of manufacturing a diode array having an arbitrary number of dots / chip by changing only an isolation mask used for forming a scribe line even when the number of dots per one chip area is different. To provide.

(Means for Solving the Problems) In order to achieve this object, according to the method for manufacturing a diode array of the present invention, regardless of the difference in the number of dots / chip, first, the surface of the first conductivity type substrate is formed. A large number of diffusion layers are formed by using the provided diffusion mask, and thereafter, first electrodes that make ohmic contact with these diffusion layers are formed.

In the present invention, the scribe line is formed using an isolation mask at an appropriate process step after the formation of the first electrode, and is divided into chip areas corresponding to the number of dots / chip according to the design.

(Operation) In this way, the diode array can be manufactured in the same process up to the first electrode formation process regardless of the difference in the number of dots / chips, and only at an arbitrary process stage after the formation of the first electrode. The scribe line can be formed using an isolation mask corresponding to the number of dots according to the design. Also, the scribe line can be formed on the diffusion layer. Therefore, the diode arrays having different numbers of dots in one chip area can be easily formed separately only by changing the isolation mask.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the dimensions, shapes, and positional relationships of the respective constituent components to the extent that the present invention can be understood.

FIG. 1 is a process explanatory view for explaining an embodiment of a method for manufacturing a diode array of the present invention, and FIGS. 2 (A) and 2 (B).
FIG. 3 is a plan view schematically showing a wafer state in main process steps. In the figure, the same components as those shown in FIGS. 3 (A) to (C) are designated by the same reference numerals.

First, an n-type GaAsP substrate is prepared as the first conductivity type substrate 10, and an insulating film such as an Al ₂ O ₃ film is formed on the surface of this substrate 10 as a diffusion mask by a CVD method or a sputtering method. Then, patterning is performed by a lingraphy method which is an ordinary semiconductor manufacturing technique to form a diffusion mask (step 1 in FIG. 1).

Next, after the wafer having the diffusion mask is ampoule-sealed, p-type impurity ions such as Zn are diffused into the substrate 10 at a temperature of, for example, 750 ° C. A large number of diffusion layers 13 (FIG. 2 (A)) are formed (first
Step 2) in the figure. In this example, these diffusion layers 13 and the substrate
10 and 10 form a diode pn junction.

Next, on the surface of the substrate 10 on which the diffusion layer 13 is formed, for example, A
After vapor deposition of l, patterning is performed using a normal lithographic method, and then heat treatment is performed at a temperature of 500 to 600 ° C. to obtain a first electrode in ohmic contact with the diffusion layer 13, in this case, an Al electrode ( Sunstep 3 in Figure 1).

Next, after lapping the back surface of the substrate 10 to a substrate thickness of 200 to 300 μm, a metal layer of Au-Ge, Ni, Au or the like is deposited on the lapping surface by a vacuum deposition method. Then, heat treatment is performed to form ohmic contact between the metal layer and the substrate, thus forming an n-type electrode as the second electrode (step 4 in FIG. 1).

Next, a scribe line is formed using an isolation mask suitable for the number of dots / chip according to the design,
The chip area 11 is divided (step 5 in FIG. 1). This wafer state is shown in FIG. 2 (B). In this case, the portions of the Al electrode and the insulating film where scribing is performed are sequentially removed by etching.

When a wafer crack 14 is formed during the formation of the scribe line, the scribe line 12 may be formed at a portion including the wafer crack 14 as shown in FIG. 2 (B).

Obviously, the invention is not limited to the embodiments described above.

For example, in the above-described embodiment, an example in which the scribe line is formed at the final stage has been described, but this scribe line formation can be performed at any suitable stage as long as it is a stage after the formation of the first electrode.

Further, in the present invention, the size, shape and arrangement relationship of each of the above-mentioned constituents can be arbitrarily set according to the design. Further, the first electrode may be p-type and the second conductivity type diffusion layer may be n-type, and the semiconductor material to be used including the substrate material can be arbitrarily selected.

(Effects of the Invention) As is apparent from the above-described embodiments, according to the present invention, any suitable step after forming the diffusion layer forming the pn junction of the diode and the first electrode in ohmic contact therewith In the above, since the scribe line is formed to divide into chip areas such that the number of dots / chip corresponds to the design, the necessary diffusion and vapor deposition until the formation of the scribe line can be performed with different numbers of dots / chip. There is an advantage that a common glass mask pattern can be used for the diode array.

Further, according to the present invention, there is an advantage that various diode arrays having different numbers of dots / chips can be produced by changing only the isolation pattern. Also, the scribe line can be formed on the diffusion layer.

Further, according to the present invention, even if a wafer crack partially occurs during the wafer process, the scribe line can be formed including the wafer crack portion, so that the wafer having the wafer crack portion can be effectively used. Available.

Therefore, according to the present invention, there is an advantage that the manufacturing process of the diode array having different numbers of dots / chips can be simplified and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the steps of one embodiment of the method for manufacturing a diode array of the present invention, and FIGS. 2 (A) and 2 (B) are main manufacturing processes used for explaining the method of manufacturing a diode array of the present invention. FIGS. 3A to 3C are plan views schematically showing a wafer state at a main manufacturing stage for explaining a conventional method for manufacturing a diode array. is there. 10 …… First conductivity type substrate, 11 …… Chip area 12 …… Scribe line, 13 …… Diffusion layer 14 …… Wafer crack.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masato Kawahara 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References Japanese Patent Publication No. 51-27985 (JP, B1)

Claims (1)

[Claims] 1. A step of forming a diffusion mask on the surface of a first conductivity type substrate, a step of forming a large number of second conductivity type diffusion layers on the substrate, and a step of forming a first electrode on the diffusion layer. And a step of forming a second electrode on the back surface of the substrate, and a step of forming a scrape line for dividing into a plurality of chip regions for each of the plurality of diffusion layer groups. A method for manufacturing a diode array, characterized in that the scrape line is formed by using an isolation mask in a step after forming the first electrode on the diffusion layer by using a mask.