JPH0638259U - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JPH0638259U JPH0638259U JP073377U JP7337792U JPH0638259U JP H0638259 U JPH0638259 U JP H0638259U JP 073377 U JP073377 U JP 073377U JP 7337792 U JP7337792 U JP 7337792U JP H0638259 U JPH0638259 U JP H0638259U
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor element
- control
- temperature
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】 電力半導体素子に過熱異常が発生した場合、
その熱による素子破壊を防ぐことができる機能を有し、
絶縁性及び信頼性が高く、しかも安価な電力半導体装置
を提供する。
【構成】 電力半導体素子から発生する熱は金属細線に
よって制御用ＩＣに伝達され、その伝達された熱による
温度を検知する温度検知手段と、その検知された温度が
所定以上である場合には電力半導体素子に供給すべき電
流及び電圧を遮断するための過熱保護回路とを設ける。
(57) [Summary] [Purpose] When an overheating abnormality occurs in a power semiconductor device,
It has a function to prevent element destruction due to the heat,
(EN) Provided is a power semiconductor device which has high insulation and reliability and is inexpensive. [Structure] Heat generated from a power semiconductor element is transferred to a control IC by a thin metal wire, and temperature detection means for detecting a temperature due to the transferred heat, and power when the detected temperature is equal to or higher than a predetermined value. An overheat protection circuit for cutting off the current and voltage to be supplied to the semiconductor element is provided.
Description
【０００１】[0001]
本考案は電力半導体装置に関し、更に詳しくは電力半導体素子とその制御用Ｉ Ｃが１つの基板に搭載された電力半導体装置に関する。 The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device in which a power semiconductor element and its control IC are mounted on one substrate.
【０００２】[0002]
図４及び図５は従来例を示す図で、（ａ）は平面図、（ｂ）はその側面図を示 す。 4 and 5 are views showing a conventional example, in which (a) is a plan view and (b) is a side view thereof.
【０００３】 電力半導体素子４１と制御用ＩＣ４２は放熱板４３に搭載されており、樹脂４ ７によって樹脂封止されている。この電力半導体素子４１は熱を発生するため、 電気的接続と熱伝導性の良いハンダを介して放熱板４３に搭載されている。一方 制御用ＩＣ４２は、半導体素子４１を搭載した放熱板４３の電位と制御用ＩＣ４ ２の裏面の電位が異なる場合、放熱板４３と制御用ＩＣ４２とを絶縁する必要が あり、例えば図４に示すような絶縁ぺースト４０や、図５に示すような絶縁フィ ルム５０の他、絶縁テープやセラミックスやセラミックス等の絶縁物を介して、 この制御用ＩＣ４２と放熱板４３とが固着されている。また、電力半導体素子４ １と制御用ＩＣ４２と外部出力端子４９とは金属細線４４によって電気的に接続 されている。そこで、電力半導体素子４１に過大な電流が流れたり、放熱が不十 分であった場合に、電力半導体素子４１が異常発熱が起こると、放熱板４３から 絶縁物を通して制御用ＩＣ４２に熱が伝わるが、ある一定以上の温度上昇があっ た場合、制御用ＩＣ４２内部に形成されている過熱保護回路（図示せず）が作動 し、電流電圧が遮断されるようになっている。The power semiconductor element 41 and the control IC 42 are mounted on a heat dissipation plate 43, and are resin-sealed with a resin 47. Since the power semiconductor element 41 generates heat, it is mounted on the heat dissipation plate 43 via electrical connection and solder having good heat conductivity. On the other hand, the control IC 42 needs to insulate the heat dissipation plate 43 and the control IC 42 from each other when the potential of the heat dissipation plate 43 on which the semiconductor element 41 is mounted is different from the potential of the back surface of the control IC 42. For example, as shown in FIG. In addition to the insulating paste 40 and the insulating film 50 as shown in FIG. 5, the control IC 42 and the heat dissipation plate 43 are fixed to each other through an insulating tape or an insulator such as ceramics or ceramics. Further, the power semiconductor element 41, the control IC 42, and the external output terminal 49 are electrically connected by the thin metal wire 44. Therefore, if an excessive current flows through the power semiconductor element 41 or if the heat radiation is insufficient, if the power semiconductor element 41 causes abnormal heat generation, heat is transferred from the heat dissipation plate 43 to the control IC 42 through the insulator. However, when the temperature rises above a certain level, the overheat protection circuit (not shown) formed inside the control IC 42 is activated, and the current voltage is cut off.
【０００４】[0004]
ところで、電力半導体素子を搭載した放熱板と制御用ＩＣとの間に高い絶縁が 要求される場合、放熱板と制御用ＩＣとを固着させる絶縁物の厚さを厚くする必 要があり、絶縁ペーストでは高い絶縁が得られない。この場合、絶縁テープで絶 縁物を厚くすることによって高い絶縁性が得られるものの、電力半導体素子から の熱がこの絶縁物により遮られるため、電力半導体素子から生じる熱が、制御用 ＩＣに的確に伝わらず、この電力半導体素子が異常発熱したときに、制御用ＩＣ 内部に形成されている過熱保護回路が働かず、そのため素子が破壊するといった 問題が生じていた。また、セラミックス等の絶縁性及び熱伝導性に優れた絶縁物 は高価なため、製造コストが上昇するという問題もあった。 By the way, when high insulation is required between the heat dissipation plate on which the power semiconductor element is mounted and the control IC, it is necessary to increase the thickness of the insulator that fixes the heat dissipation plate and the control IC. High insulation cannot be obtained with paste. In this case, although high insulation can be obtained by thickening the insulator with an insulating tape, the heat generated from the power semiconductor element is blocked by this insulator, so that the heat generated from the power semiconductor element can be accurately applied to the control IC. However, when this power semiconductor element abnormally heats up, the overheat protection circuit formed inside the control IC does not work, which causes a problem that the element is destroyed. In addition, since insulators such as ceramics having excellent insulating properties and thermal conductivity are expensive, there is a problem that the manufacturing cost is increased.
【０００５】 本考案は以上の問題点を解決するためになされたもので、電力半導体素子に過 熱異常が発生した場合でも、その熱による素子破壊を防ぐことができる機能を有 し、絶縁性及び信頼性が高く、しかも安価な電力半導体装置を提供することを目 的とする。The present invention has been made in order to solve the above problems, and has a function of preventing element damage due to heat even if an overheat abnormality occurs in a power semiconductor element. In addition, it is an object of the present invention to provide a highly reliable and inexpensive power semiconductor device.
【０００６】[0006]
上記の目的を達成するために、本考案の電力半導体装置は、放熱板上に、ハンダ を介して電力半導体素子が電気的に接続され、かつ、上記電力半導体素子を制御 するための制御用ＩＣが絶縁物を介して固着されてなる半導体装置において、そ の制御用ＩＣと電力半導体素子とが金属細線を介して電気的に接続されていると ともに、上記制御用ＩＣ内に、当該制御用ＩＣの温度を上記金属細線の接続点近 傍で検知する温度検知手段と、その温度検知手段による検知結果に基づいて上記 電力半導体素子に供給すべき電流及び電圧を遮断するための過熱保護回路とを備 えたことによって特徴付けられる。 In order to achieve the above object, the power semiconductor device of the present invention is a control IC for controlling a power semiconductor element, in which a power semiconductor element is electrically connected via a solder to a heat sink. In a semiconductor device in which the control IC and the power semiconductor element are electrically connected to each other through a thin metal wire, the control IC and the power semiconductor element are electrically connected to each other in the control IC. A temperature detecting means for detecting the temperature of the IC near the connection point of the thin metal wire, and an overheat protection circuit for cutting off the current and voltage to be supplied to the power semiconductor element based on the detection result of the temperature detecting means. It is characterized by having.
【０００７】[0007]
従来、電力半導体素子から生じる熱は、制御用ＩＣの過熱保護回路に伝達され るが、このときに検知される温度は放熱板上の絶縁物を介して伝達される温度で あり、特にこの絶縁物が厚い場合は電力半導体素子から生じる熱と検知される温 度との相関性が劣るものであった。本考案では、電力半導体素子に発熱した熱は 、金属細線を介して制御用ＩＣ内に形成されている温度検知手段に伝達され、電 力半導体素子に発熱した熱と検知された温度とは相関する。この温度検知手段に よって検知された検知結果は、過熱保護回路に伝達され、その温度が所定以上で ある場合には電力半導体素子に供給すべき電流電圧が遮断される。 Conventionally, the heat generated from the power semiconductor element is transferred to the overheat protection circuit of the control IC, but the temperature detected at this time is the temperature transferred via the insulator on the heat sink. When the object is thick, the correlation between the heat generated from the power semiconductor device and the detected temperature was poor. In the present invention, the heat generated in the power semiconductor element is transferred to the temperature detecting means formed in the control IC through the thin metal wire, and the heat generated in the power semiconductor element correlates with the detected temperature. To do. The detection result detected by the temperature detecting means is transmitted to the overheat protection circuit, and when the temperature is higher than a predetermined value, the current voltage to be supplied to the power semiconductor element is cut off.
【０００８】[0008]
本考案実施例として、リニアレギュレータを例にあげて以下に説明する。 図２はこの本考案実施例の平面図であり、図１はその要部拡大図である。 As an embodiment of the present invention, a linear regulator will be described below as an example. FIG. 2 is a plan view of this embodiment of the present invention, and FIG. 1 is an enlarged view of the essential parts thereof.
【０００９】 トランジスタチップ１と制御用ＩＣチップ２は放熱板３上に搭載されており、 これらのチップは樹脂７によって樹脂封止されている。このトランジスタチップ １は、過大な電流が流れたり、放熱が不十分である場合、熱を発生する。このた め、トランジスタチップ１は導電性及び熱伝導性が良いハンダ８を介して放熱板 ３に搭載されているが、制御用ＩＣチップ２は放熱板３との絶縁性を保持するた めに絶縁フィルム６を介して固着されている。さらに、トランジスタチップ１と 制御用ＩＣチップ２と外部出力端子９とは金属細線４によって電気的に接続され ている。この制御用ＩＣチップ２において、この金属細線４との接続部分にはボ ンディングパット１０が設けられており、トランジスタチップ１で発生した熱は このボンディングパット１０に伝達し、またこのボンディングパット１０の近傍 に設けられた温度センサ５ａにより温度が検知され、過熱保護回路５ｂに伝達さ れる。そこで過熱保護回路５ｂによって、この検知された温度が予め設定された 温度に達しているか否かの判断がなされ、設定された温度に達している場合は、 トランジスタチップ１に供給すべき電流及び電圧を遮断することにより、トラン ジスタチップ１の作動を停止し、過熱を防止している。The transistor chip 1 and the control IC chip 2 are mounted on a heat dissipation plate 3, and these chips are resin-sealed with a resin 7. The transistor chip 1 generates heat when an excessive current flows or heat dissipation is insufficient. For this reason, the transistor chip 1 is mounted on the heat sink 3 via the solder 8 having good electrical conductivity and thermal conductivity, but the control IC chip 2 is required to maintain insulation from the heat sink 3. It is fixed via the insulating film 6. Further, the transistor chip 1, the control IC chip 2, and the external output terminal 9 are electrically connected by the thin metal wire 4. In this control IC chip 2, a bonding pad 10 is provided at the connection portion with the thin metal wire 4, the heat generated in the transistor chip 1 is transferred to the bonding pad 10, and the bonding pad 10 also has a bonding pad 10. The temperature is detected by the temperature sensor 5a provided in the vicinity and transmitted to the overheat protection circuit 5b. Therefore, the overheat protection circuit 5b determines whether or not the detected temperature has reached a preset temperature. If the detected temperature has reached the preset temperature, the current and voltage to be supplied to the transistor chip 1 are determined. By shutting off, the operation of the transistor chip 1 is stopped and overheat is prevented.
【００１０】 ここで、図３に示した本発明実施例のリニアレギュレータのブロック図を参照 しながら、本発明実施例の作用を説明する。 トランジスタ１ａが発熱すると、その熱は金属細線を介して制御用ＩＣチップ ２に伝達される（図１に示す矢附の向き）。トランジスタ１ａが予め設定された 温度まで上昇した場合に、過熱保護回路５が温度を検知し作動する。この過熱保 護回路５が作動すると、トランジスタ１ａを制御するトランジスタ３７のべース 電流が過熱保護回路５に引き込まれオフとなり、トランジスタ１ａのべースに供 給する電流を遮断し、このトランジスタ１ａをオフとすることにより、トランジ スタ１ａは動作を停止する。The operation of the embodiment of the present invention will be described with reference to the block diagram of the linear regulator of the embodiment of the present invention shown in FIG. When the transistor 1a generates heat, the heat is transferred to the control IC chip 2 through the thin metal wire (in the direction of the arrow shown in FIG. 1). When the temperature of the transistor 1a rises to a preset temperature, the overheat protection circuit 5 detects the temperature and operates. When the overheat protection circuit 5 operates, the base current of the transistor 37 that controls the transistor 1a is drawn into the overheat protection circuit 5 and turned off, shutting off the current supplied to the base of the transistor 1a. By turning off 1a, the transistor 1a stops operating.
【００１１】 一方、トランジスタ１ａが上述した設定温度まで上昇していない場合は、過熱 保護回路５は作動せず、基準電圧発生回路３３の基準電圧に基づいて出力電圧が 制御される。On the other hand, when the transistor 1a has not risen to the above-mentioned set temperature, the overheat protection circuit 5 does not operate, and the output voltage is controlled based on the reference voltage of the reference voltage generation circuit 33.
【００１２】 なお、ＡＳＯ保護回路３１はこのリニアレギュレータにおいて、過電流過電圧 を保護する回路である。また、出力ON/OFF制御回路３４は外部信号により出力を オンオフさせる回路である。The ASO protection circuit 31 is a circuit that protects the overcurrent and overvoltage in this linear regulator. The output ON / OFF control circuit 34 is a circuit that turns the output on and off by an external signal.
【００１３】[0013]
以上述べたように、本考案の電力半導体装置によれば、電力半導体素子から発 生する熱は金属細線によって制御用ＩＣに伝達され、その伝達された熱による温 度を検知する温度検知手段と、その検知された温度が所定以上である場合には電 力半導体素子に供給すべき電流及び電圧を遮断するための過熱保護回路とを設け たので、電力半導体素子に過熱異常が発生した場合、ただちにその電力半導体素 子の動作が停止するように電流及び電圧の供給を遮断することができる。したが って、過熱による素子破壊を防ぐことができ、その結果、絶縁性及び信頼性の高 い電力半導体装置を実現できる。 As described above, according to the power semiconductor device of the present invention, the heat generated from the power semiconductor element is transferred to the control IC by the thin metal wire, and the temperature detection means for detecting the temperature due to the transferred heat is used. Since an overheat protection circuit is provided to shut off the current and voltage that should be supplied to the power semiconductor element when the detected temperature is above a predetermined level, if an overheat abnormality occurs in the power semiconductor element, Immediately, the supply of current and voltage can be cut off so that the operation of the power semiconductor element is stopped. Therefore, element breakdown due to overheating can be prevented, and as a result, a power semiconductor device with high insulation and reliability can be realized.
【００１４】 さらに、制御用ＩＣに用いられる絶縁物は、従来のような熱伝導性に優れた高 価なものは必要とせず、製造コストを低減することができる。Further, the insulating material used for the control IC does not need to be a high-priced material having excellent thermal conductivity as in the conventional case, and the manufacturing cost can be reduced.
【図１】本考案実施例の要部拡大図FIG. 1 is an enlarged view of a main part of an embodiment of the present invention.
【図２】本考案実施例の平面図FIG. 2 is a plan view of an embodiment of the present invention.
【図３】本考案実施例の回路ブロック図FIG. 3 is a circuit block diagram of an embodiment of the present invention.
【図４】従来例を説明する図FIG. 4 is a diagram illustrating a conventional example.
【図５】従来例を説明する図FIG. 5 is a diagram illustrating a conventional example.
１・・・・トランジスタチップ ２・・・・制御用ＩＣチップ ３・・・・放熱板 ４・・・・金属細線 ５・・・・過熱保護回路部 ５ａ・・・・温度センサ ５ｂ・・・・過熱保護回路 ６・・・・絶縁フィルム ７・・・・樹脂 ８・・・・ハンダ ９・・・・リード端子 １０・・・・ボンディングパット １１・・・・べース 1 ...- Transistor chip 2 ...- Control IC chip 3 ...- Heat sink 4 ...- Metal thin wire 5 ...- Overheat protection circuit section 5a ... Temperature sensor 5b ...・ Overheat protection circuit 6 ・ ・ ・ Insulation film 7 ・ ・ ・ Resin 8 ・ ・ ・ ・ Solder 9 ・ ・ ・ ・ Lead terminal 10 ・ ・ ・ ・ Bonding pad 11 ・ ・ ・ ・ ・ ・ Base
Claims (1)
素子が電気的に接続され、かつ、上記電力半導体素子を
制御するための制御用ＩＣが絶縁物を介して固着されて
なる半導体装置において、その制御用ＩＣと電力半導体
素子とが金属細線を介して電気的に接続されているとと
もに、上記制御用ＩＣ内に、当該制御用ＩＣの温度を上
記金属細線の接続点近傍で検知する温度検知手段と、そ
の温度検知手段による検知結果に基づいて上記電力半導
体素子に供給すべき電流及び電圧を遮断するための過熱
保護回路とを備えたことを特徴とする電力半導体装置。1. A semiconductor device in which a power semiconductor element is electrically connected via a solder to a heat sink, and a control IC for controlling the power semiconductor element is fixed via an insulator. In the above, the control IC and the power semiconductor element are electrically connected via a metal thin wire, and the temperature of the control IC is detected in the control IC near the connection point of the metal thin wire. A power semiconductor device comprising: a temperature detecting means; and an overheat protection circuit for cutting off a current and a voltage to be supplied to the power semiconductor element based on a detection result of the temperature detecting means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992073377U JP2564370Y2 (en) | 1992-10-21 | 1992-10-21 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992073377U JP2564370Y2 (en) | 1992-10-21 | 1992-10-21 | Power semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0638259U true JPH0638259U (en) | 1994-05-20 |
| JP2564370Y2 JP2564370Y2 (en) | 1998-03-09 |
Family
ID=13516439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1992073377U Expired - Fee Related JP2564370Y2 (en) | 1992-10-21 | 1992-10-21 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2564370Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH094787A (en) * | 1995-06-15 | 1997-01-07 | Nakatsu:Kk | Piping wiring containing frame for outdoor machine and disposing work executing method therefor |
| JP2006041407A (en) * | 2004-07-30 | 2006-02-09 | Hitachi Industrial Equipment Systems Co Ltd | Temperature sensing method of semiconductor apparatus and power converter |
-
1992
- 1992-10-21 JP JP1992073377U patent/JP2564370Y2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH094787A (en) * | 1995-06-15 | 1997-01-07 | Nakatsu:Kk | Piping wiring containing frame for outdoor machine and disposing work executing method therefor |
| JP2006041407A (en) * | 2004-07-30 | 2006-02-09 | Hitachi Industrial Equipment Systems Co Ltd | Temperature sensing method of semiconductor apparatus and power converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2564370Y2 (en) | 1998-03-09 |
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