JPH0638177A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To provide the video signal processing unit suitable for large scale circuit integration by adding data of horizontal/vertical blanking and an identification signal to reproduced video signal data with simple configuration. CONSTITUTION:Pre-processing circuits 30-37 including a correction circuit which corrects picture element data not corrected by error correction from video signal data of plural channels not subject to error check correction reproduced from a tape in a reproduction system circuit of a digital VTR for HDTV by using adjacent picture element data, an additional data generating circuit generating additional data including identification signal data for digital interface and horizontal vertical blanking data to be added to video signal data of each channel and an additional circuit adding addition data to the video signal data of each channel are arranged to a pre-stage of a parallel parallel conversion circuit 38.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device in a video recording / reproducing device such as a digital VTR,
In particular, the present invention relates to a video signal processing device having a function of adding additional data including horizontal / vertical blanking data and digital interface identification signal data to reproduced video signal data.

[0002]

2. Description of the Related Art With the promotion of HDTV (High Definition Television) system, development of VTR for recording / reproducing HDTV signals is in progress. In such an HDTV VTR, a digital recording system with less signal deterioration than an analog recording system is being adopted.

FIG. 6 and FIG. 7 show schematic configurations of a recording system circuit and a reproducing system circuit of a conventional HDTV digital VTR. The digital VTR for HDTV uses a luminance signal Y of an analog input / output video signal and two kinds of color signals P.
b and Pr, a video signal input / output of two systems of a luminance signal Y of a digital input / output video signal and a time-division-multiplexed color signal P, and recording / reproducing of a video signal in a multi-track (multi-channel). is there.

First, in the recording system circuit shown in FIG. 6, the luminance signal Y of the analog input video signal is the A / D converter 1
Is converted into an 8-bit digital signal at a sampling rate of 74.25 MHz, and the color signals Pb and Pr are
Is converted into an 8-bit digital signal at a sampling rate of 37.125 MHz by the A / D converters 2 and 3. The selection switch 4 selects the luminance signal Y and the color signals Pb and Pr converted into digital signals and the luminance signal Y and the color signal P which are digital input video signals.

In the case of an HDTV signal, since the source bit rate of the video signal data at the time of leaving the selection switch 4 reaches about 1.2 Mbps, the bit rate is too high as it is, and the digital signal processing and the tape are processed. Is difficult to record. Therefore, from the video signal data selected by the selection switch 4, only the effective video signal excluding the horizontal and vertical blanking is extracted by the serial-parallel conversion circuit 5 and divided into 8 channels of the 1st to 8th channels.
Parallelization processing is performed to reduce the bit rate per channel to 150 Mbps.

The video signal data of the first to eighth channels output from the serial-parallel conversion circuit 5 are input to the error encoder 6, where (a) shuffling processing for dispersing burst errors due to tape damage, (b) A process of calculating parity for error detection and error correction during playback and adding it to the video signal data, and (c) Dividing the video signal data containing a predetermined length of parity for recording on tape into blocks. After the process of adding an ID by the recording head 7
Is digitally recorded on the tape 8.

On the other hand, in the reproducing system circuit shown in FIG. 7, the video signal data of the first to eighth channels including the error reproduced from the tape 8 by the reproducing head 9 is the error decoding circuit 10.
The error is detected and corrected by the parity added at the time of recording. If many errors occur in the reproduced video signal data and there is error pixel data that cannot be corrected by the error decoding circuit 10, the error decoding circuit 10 sets an error flag in the error pixel data, and this error flag is set. Accordingly, the correction circuit 11 performs the error correction processing using the adjacent pixel data.

Since the correction circuit 11 uses the adjacent pixel data for error correction, the adjacent pixels are arranged in the output in the order of adjoining pixels for each channel in the time axis direction (horizontal direction), as shown in FIG. There is. It should be noted that the numbers in the subscripts in FIG. 8 indicate the pixel numbers in the horizontal direction on the television screen. For this reason,
When the parallelized video signal data is restored in the parallel-serial conversion circuit 14, the video signal data output from the modification circuit 11 is input to the parallel-parallel conversion circuit 12 in order to facilitate parallel-serial conversion. A process of rearranging the pixels in the order of pixels such that the adjacent pixels are located in the adjacent channel is performed as shown in FIG.

From the parallel / parallel conversion circuit 12, only effective video signal data excluding horizontal and vertical blanking is output. Therefore, FP (frame pulse) and HD from the synchronization generation circuit 23 synchronized with the input synchronization signal
In accordance with the (horizontal drive) signal and the clock signal, the sync signal data generation circuit 15 generates a sync signal to be added to the luminance signal Y, and similarly, the blanking data generation circuit 16 outputs blanking data to be added to the color signal P. It is generated and added to the video signal data by the switch circuit 13 as shown in FIG.

The parallel video signal data to which the horizontal and vertical blanking are added is the parallel-serial conversion circuit 1 in the next stage.
No. 4, as shown in FIGS. 10 to 11, 74.25 Mb
It is converted into a serial digital video signal of a luminance signal Y of ps 8-bit parallel data and a time-division multiplexed color signal P.

The luminance signal Y and the color signals Pb and Pr of the digital video signal data are output as analog video output signals by the D / A converters 18 to 20, and the digital synchronizing signal data added to the luminance signal Y. Is D / A
It is output as an analog sync signal output by the converter 21. Further, according to the signal from the synchronization generation circuit 23, EAV (End of Active Video) and S to be added to the luminance signal Y and the color signal P in the identification signal data generation circuit 17
Digital interface identification signals shown in Tables 1 and 2 of AV (Start of Active Video) are generated, and the digital interface identification signals are converted into parallel-serial conversion circuits 14
Is added by the switch circuit 22 to obtain a digital video output signal as shown in FIG.

[0012]

[Table 1]

[0013]

[Table 2]

As described above, in the conventional video signal processing device,
Since the circuit (additional data addition switch circuit 13) for adding the horizontal / vertical blanking and digital interface identification signals is provided in the subsequent stage of the parallel / parallel conversion circuit 12, three independent additional data generation circuits (synchronization signals Data generation circuit 15, blanking data generation circuit 1
6 and the identification signal data generation circuit 17).
Therefore, the circuit configuration is not suitable for downsizing the LSI circuit (LSI).

[0015]

As described above, in the conventional video signal processing device, in order to add each data of the horizontal / vertical blanking and the identification signal to the reproduced video signal data, each data is added. Since a plurality of additional data generating circuits that are individually generated and an additional circuit for adding them are required, there is a problem that the overall circuit scale increases and it is not suitable for an LSI.

According to the present invention, each data of identification signals such as horizontal / vertical blanking and identification signals for digital interface can be added to the reproduced video signal data with a simple structure, which is suitable for LSI implementation. An object is to provide a video signal processing device.

[0017]

In order to solve the above-mentioned problems, the present invention provides a horizontal / horizontal correction method for video signal data which has been subjected to a modification process by a modification circuit in the preceding stage of a parallel / parallel conversion circuit.
The main point is that each data of the identification signal such as the identification signal for vertical blanking and digital interface is added.

That is, the video signal processing apparatus according to the present invention includes an error correction means for detecting and correcting an error in video signal data of a plurality of channels reproduced from a recording medium, and the video signal data of the plurality of channels. A plurality of modifying means for modifying the pixel data not corrected by the error correcting means using adjacent pixel data, and horizontal / vertical blanking data and identification signal data to be added to the video signal data of the plurality of channels. A plurality of additional data generating means for generating additional data including the additional data, and a plurality of additional data adding means for respectively adding the additional data generated by the additional data generating means to the video signal data of the plurality of channels that have passed through the modifying means. , The video signal data of a plurality of channels to which the additional data is added by the additional data adding means Characterized by comprising a parallel-parallel conversion means for row conversion.

[0019]

In this way, by adding the respective data of the horizontal / vertical blanking and the identification signal in the latter stage of the modifying means and before the parallel / parallel converting means, the modifying means, the additional data generating means and the adding means are provided. Furthermore, the circuit can be integrally configured including the timing control means for controlling these operation timings, which is advantageous for the LSI of the reproduction system circuit.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a part of a reproduction system circuit in a video signal processing device according to an embodiment of the present invention.
The configuration from the error decoding circuit 10 onward to the preceding stage of the D / A converters 18 to 21 is shown. 2 and 3 are block diagrams showing the internal configurations of the first channel preprocessing circuit 30 and the fifth channel preprocessing circuit 35 in FIG. 4 to 5 are time charts showing the horizontal blanking portion.

In FIG. 1, the video signal data of the first to eighth channels output from the error decoding circuit 10 of FIG.
It is input to the preprocessing circuits 30 to 37. Pre-processing circuit 30-
Reference numeral 33 denotes an error correction of correction-missing pixel data according to an error flag indicating a correction omission from an error decoding circuit (not shown) for the luminance signals Y of the first to fourth channels, and horizontal / vertical blanking / sync signals. This is a circuit that performs processing for adding each data of the identification signal, and is composed of a timing controller, a correction circuit, a blanking / synchronization signal / identification signal data generation circuit, and an additional data addition switch circuit.

Similarly, the preprocessing circuits 34 to 37 perform error correction on the correction-missing pixel data for the color signals Y of the fifth to eighth channels according to an error flag indicating a correction error from an error decoding circuit (not shown). In addition, it is a circuit that performs processing for adding each data of horizontal / vertical blanking / identification signal, and is composed of a timing controller, a correction circuit, a blanking / identification signal data generation circuit, and a switch circuit.

2 and 3 are diagrams showing the internal configuration of the preprocessing circuits 30 and 34. As shown in FIG. The timing controllers 40 and 44 are FPs from a synchronization generation circuit (not shown).
(Frame pulse), HD (horizontal drive pulse) and clock signals are used to control the timing of the adjusting circuits 41 and 45 and the blanking / synchronizing signal / identification signal data generating circuits 42 and 46.

Specifically, the timing of the error correction processing operation in the correction circuits 41 and 45 is performed on the corrected leaked pixel data in the effective video signal data section, and then the blanking section at the time when the correction processing is completed is performed. Switches 43 and 47 are provided for transmitting the horizontal / vertical blanking data generated by the blanking / synchronization signal / identification signal data generation circuit 42 and the blanking / identification signal data generation circuit 46 and the identification signal data for digital interface.
The selection signal of is switched in the blanking section. The preprocessing circuits 31 to 33 have basically the same configuration as the preprocessing circuit 30, and the preprocessing circuits 35 to 37.
The configuration of is basically the same as that of the preprocessing circuit 34.

The outputs of the preprocessing circuits 30 to 37 are input to the parallel / parallel conversion circuit 38 in the next stage and become the parallel / parallel conversion output data shown in FIG. The decimal number shown in FIG. 4 indicates an 8-bit video level. In addition, the decimal display level of the horizontal blanking data shown in FIG. 4 represents the level when the pedestal level is set to “110” as an example.

Among the data added to the video signal data after the correction by the correction circuits 41 and 45, the horizontal / vertical blanking data and the identification signal data are transmitted to one data bus, so that the digital output is identified. Signal data EA
When transmitting V and SAV, blanking data of analog output is not supplied. Therefore, the luminance signal Y
The black level data of level “16” and the color signal P
The pedestal level data of level “128” is added to the serial data after the parallel-serial conversion circuit 39, and the switch circuit 50.
Is added according to the blanking gate signal from the timing controller 40.

On the other hand, since the blanking data of the digital output when the horizontal blanking data (synchronization signal) of the analog output is being transmitted is not supplied, the luminance signal Y is supplied with the digital image according to the clock gate signal from the timing controller 4. Blanking data is added by inhibiting the latch clock of the output latch 52 with the gate 51.

As a result, a serial digital video signal and a digital video output signal as shown in FIG. 5 can be obtained. The serial digital video signal is converted into an analog signal by a D / A converter (not shown) at the next stage and becomes an analog video output signal. The horizontal blanking data multiplexed on the luminance signal Y is converted into an analog signal by a D / A converter (not shown) at the next stage in accordance with the sync signal gate of the control signal from the timing controller 40. It becomes an analog sync output signal.

As described above, according to this embodiment, the data generating circuits 42 and 46 for generating the respective data of the horizontal / vertical blanking and the identification signal for the digital interface are provided in the preceding stage of the parallel / parallel conversion circuit 38, and the respective data. Switch circuits 43 and 47 for adding the video signal data corrected by the correction circuits 41 and 45 to the data generation circuit 4
2, 46 and preprocessing circuit 30 having timing control circuits 40, 44 for switch circuits 43, 47.
By arranging 37, the circuit can be easily made into an LSI.

[0030]

According to the present invention, the correction circuit and the additional data are generated by adding the respective data of the horizontal / vertical blanking and the identification signal in the stage after the correction circuit and in the stage before the parallel-parallel conversion circuit. Further, a circuit for addition and a timing control circuit can be configured by one circuit for each channel. Therefore, the circuit scale of the reproduction system circuit in the video signal processing device can be reduced, which is advantageous for the LSI and miniaturization, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a reproduction system circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a first channel preprocessing circuit in FIG.

FIG. 3 is a block diagram showing a configuration of a fifth channel preprocessing circuit in FIG.

FIG. 4 is a diagram showing a part of a time chart for explaining the operation of the reproduction system circuit of FIG. 1;

5 is a diagram showing another part of the time chart for explaining the operation of the reproduction system circuit of FIG. 1;

FIG. 6 is a block diagram of a recording system circuit in a conventional digital VTR.

FIG. 7 is a block diagram of a reproduction system circuit in a conventional digital VTR.

8 is a diagram showing a pixel array of video signal data at the output of the modifying circuit of FIG.

9 is a diagram showing a pixel array of video signal data at the output of the parallel-parallel conversion circuit of FIG.

10 is a diagram showing a part of a time chart for explaining the operation of the reproduction system circuit of FIG.

11 is a diagram showing another part of the time chart for explaining the operation of the reproduction system circuit of FIG. 7. FIG.

[Explanation of symbols]

40, 44 ... Timing control circuit (timing control means) 41, 45 ... Modifying circuit (correction means) 42 ... Blanking / synchronization signal / identification signal data generation circuit (additional data generation means) 46 ... Blanking / identification signal data generation Circuit (additional data generating means) 43, 47 ... Switch circuit (additional means) 38 ... Parallel-parallel conversion circuit 39 ... Parallel-serial conversion circuit 50 ... Blanking data changeover switch circuit 51 ... Clock inhibit gate 52, 53 ... Digital video signal data For latch

Claims (2)

[Claims] 1. An error correction unit for detecting and correcting an error of video signal data of a plurality of channels reproduced from a recording medium, and a pixel which is not corrected by the error correction unit for the video signal data of the plurality of channels. A plurality of modifying means for modifying data using adjacent pixel data; and a plurality of additional data for generating additional data including horizontal / vertical blanking data and identification signal data to be added to the video signal data of the plurality of channels Generating means, a plurality of additional data adding means for respectively adding the additional data generated by the additional data generating means to the video signal data of the plurality of channels that have passed through the modifying means, and the additional data is added by the additional data adding means. And parallel-parallel conversion means for converting the added video signal data of a plurality of channels in parallel and parallel. A video signal processing device characterized by the above. 2. The video signal processing according to claim 1, wherein the modifying means, the additional data generating means, the additional data adding means, and the timing control means for controlling the timings of these are integrally formed for each channel. apparatus.