JPH0637780A - Method for retransmitting disappearing frame and its equipment - Google Patents

Abstract

PURPOSE:To detect disappearance of plural frames without use of a timer by monitoring a transmission frame returned through circulation of a token ring network so as to detect disappearing frames and re-transmitting disappearing frames. CONSTITUTION:A frame consecutive transmission means 1 sends a frame continuously to a token ring network. A destination address buffer 2 stores sequentially a destination address of a frame and its time sent by the frame consecutive transmission means 1. Then when the sent frame is returned through the token ring network, a retrieval means 3 retrieves a destination address stored in the destination address buffer 2. Furthermore, when the circulated frame cannot be detected by the retrieval means 3 on the transfer of data, a re-transmission control means 4 controls the re-transmission of a frame corresponding to the destination address in the destination address buffer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network for connecting computers, and more particularly to a method and apparatus for retransmitting a lost frame in, for example, a token ring network.

[0002]

2. Description of the Related Art With the development of computer technology, a network system for connecting a plurality of computers has been developed. This network is designed to add the address of the receiving computer and transfer the data when it is necessary to transfer the data from an individual computer such as a personal computer to another personal computer. Since a plurality of computers are connected to one network, it is conceivable that a coregion or the like may occur, but the transfer of these data is controlled by various methods.

Token ring networks are another method. In this token ring network, a plurality of communication devices connected on the ring transmit a chaotic frame to collide with each other, and a special frame called a free token is circulated to prevent a so-called co-region from occurring. The computer that receives the frame can send the frame.

When a communication device that generates data to be transmitted, for example, a personal computer connected to a token ring, receives a free token, it changes the free token into a busy token, and further adds its own transmission data as a data frame after that. Send to network. When another communication device connected to the network receives the busy token and the data frame, the other party simply relays the busy token and the data frame and sends the busy token and the data frame to the token ring. When the other party is his / her own, it relays and simultaneously copies the data frame to itself. Then, assuming that the busy token and the data frame have been normally received, the reception flag is turned on and transmitted to the token ring, and the communication device that sent the frame is returned to.

The transmitting communication device does not relay the returned frame, but deletes it from the network. After the transmission, the transmission source sends a free token to release the transmission right. Data is transferred by the above-mentioned configuration.

Even in the token ring network as described above, the transmitted frame may not circulate on the loop and may disappear on the way. Therefore, it is necessary to detect the lost frame and retransmit it. That is, in the broadcast communication on the loop network, the lost frame is retransmitted to improve the reliability of communication against a failure or the like. In other words, when the frame is sent to the token ring network, the round trip monitoring timer is set, and if a time-out occurs before the returning of the revolving frame, the frame is retransmitted.

[0007]

According to the above-mentioned method,
In the case of detecting the loss, when the system sends one frame and cannot send another frame until the time-out occurs when the frame does not come back and goes around, only one monitoring timer is required. However, if multiple frames are transmitted continuously in order to increase the throughput of the transmission device, and transmission confirmation is performed collectively for the frames that return consecutively, continuous transmission must be performed to determine loss. The timer must be set for all the frames to be checked to determine the timeout. That is, conventionally, there is a problem that a large number of timers are required.

The present invention provides a lost frame retransmitting method and apparatus for detecting a lost frame and retransmitting the frame without requiring a large number of timers when continuously transmitting a plurality of frames and reducing overhead for detecting the loss. To do.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention relates to a communication device which is connected to a token ring network, monitors outgoing frames that circulate around the token ring network and returns, detects lost frames, and retransmits lost frames.

The frame continuous transmission means 1 continuously transmits frames to the token ring network. The destination address buffer 2 sequentially stores the destination address and time of the frame transmitted from the frame continuous transmission means 1.

The retrieval means 3 retrieves the destination address stored in the destination address buffer 2 when the transmitted frame circulates around the token ring network and returns.

When the data is transferred, the retransmission control means 4
The orbiting frame that makes one round and returns returns to the detection means 3
If not detected by the destination address buffer 2
The frame corresponding to the destination address within is retransmitted.

[0013]

The principle of the lost frame retransmission method of the present invention is that the destination addresses of frames to be continuously transmitted are sequentially stored,
It is judged whether or not the transmitted frame circulates and returns, by comparing with the stored destination address, and the frame that does not return is retransmitted as a lost frame.

The lost frame retransmitting apparatus of the present invention is a communication apparatus which is connected to a network, detects a lost frame by monitoring a transmitted frame that circulates around the network and returns, and retransmits the lost frame. Is.

The destination address buffer 2 constitutes, for example, a ring buffer. The destination address buffer 2 stores the destination address in the buffer every time one frame is transmitted, and when the destination address buffer 2 makes a round through the token ring network, the destination address buffer 2 is returned. The destination addresses stored in order are compared in chronological order. For example, if the address is normal, a matching address is detected in the order of transmission, but if it is lost, the lost frame is skipped and the next frame is matched. At this time, the token ring network judges this as a lost frame and retransmits it.

As a result, when a plurality of frames are lost, all the lost frames can be retransmitted based on the destination address stored in the buffer. Further, it is possible to detect the disappearance of a plurality of frames without using a timer. For this detection, for example, a system in which communication nodes connected to a so-called network in which a frame is sent out at regular intervals perform mutual communication in order to confirm each other's state at regular intervals, It is valid.

Further, the destination address buffer 2 stores not only the destination address but also the sending time in association with the address, and the detecting means 3 has the oldest destination address which has not been read from the destination address buffer. The transmission time and the current time are compared for each specific cycle, and it is determined that the frame has disappeared when the frame circulates and does not return even if the time difference becomes larger than the specific time.

This makes it possible to manage a plurality of time-outs by managing the time-out time with a single timer instead of providing a separate timer.

[0019]

The present invention will be described in detail below with reference to the drawings. <First Embodiment of the Present Invention> FIG. 2 is a block diagram of the first embodiment of the present invention. A transmitter 100 connected to a personal computer or the like receives a communication frame and sends the input frame to a token ring network. The frame continuous sending device 101 and the frame continuous sending device 101 when sending the frame are stored. A destination address storage buffer 102 that stores a destination address of a frame, and a transmission frame delivery confirmation device 1 that confirms delivery of a transmission frame
It consists of 03.

In addition, the transmission frame delivery confirmation device 103 stores the address of the revolving frame input once from the token ring network and the destination address storage buffer 10.
2 is compared with the destination address stored in 2 and the lost frame detection device 104 for detecting the lost frame, and the lost frame detected by the lost frame detection device 104 is retransmitted to the frame continuous sending device 101 to be sent again. And a lost frame retransmission control device 105 for controlling.

In order to execute communication in this transmitter 100, the processing shown in FIG. 3 is performed. It is determined in step S1 whether or not a transmission processing request is generated, and when there is no transmission processing (N), the process waits in step S1. When a communication request is generated (Y), frame information is stored in the frame information storage buffer in step S2. Then, in step S3, a destination address is set in the continuous frame transmission device. With this setting, the information in the frame information storage buffer provided in the communication device 100 is configured into a frame, and the frame continuous transmission device 101 transmits the frame to the token ring network 106. Hereinafter, when a communication request is made, it is further determined whether or not there is another communication request, and when there is a communication request (Y), the process is repeated from step S2. As a result, continuous transmission is performed. Then, when there is no other communication request, the continuous frame sending apparatus 101 is activated in step S5, and waits again in step S1.

By the above operation, continuous frames are constructed and transmitted in the frame continuous transmission device 101. On the other hand, the transmission frame delivery confirmation device 104 always performs delivery confirmation processing. FIG. 4 is a flowchart of the delivery confirmation processing according to the first embodiment of this invention. Whether or not there is a transmission frame from the token ring network 106 is determined in step S10, and when there is no revolving frame, the process waits in step S10. On the other hand, when there is a revolving frame (Y), the lost frame detection device 104 is operated in step S11.

In the lost frame detection device 104, the address stored in the destination address storage buffer 102 matches the destination address in the revolving frame, or there is an old destination address different from the one. Detect the frame.

When a lost frame exists (Y), the lost frame retransmission control device 105 extracts the address of the lost frame from the frame information storage buffer and outputs a transmission request to the continuous frame sending device 101 in step S13. If there is no lost frame (N), the process is repeated from step S10. By the above operation, the lost frame can be retransmitted.

In the embodiment of the present invention, there are various methods for detecting the lost frame in step S11. The method will be described below. The first is to detect omission of a revolving frame. This is to compare the destination address of the frame that has returned by circulation with the corresponding destination address stored in the buffer before transmission, and determine that the loss has occurred when they do not match. When this disappearance is detected, the destination address of the frame that should circulate next, the destination address of the frame that should circulate next, the destination address of the frame, and so on. The destination address is compared to search for a matching address.

Then, it is determined that all the destination address frames that do not match during the search, that is, the frames of the destination address before matching, have all disappeared. The detection of the disappearance of frames has a feature that the disappearance of a plurality of frames can be detected. Note that this detection does not use a timer, and it is necessary to send frames at regular intervals to detect lost frames. This is because communication nodes connected to the network are able to communicate with each other at regular intervals. This is effective for a system that regularly communicates to check the status of each other.

FIG. 5 is an explanatory diagram of the destination address storage buffer and the pointer. The destination address storage buffer 102 constitutes a ring buffer, and the write pointer 110 and the read pointer 111 indicate the write address and the read address. For example, when there is a file to be transmitted next, the destination address is written to the write pointer 11
Write to the position indicated by 0. Then, the write pointer is moved as shown in FIG. By this movement, the next writing position is designated. That is, the destination address is written in the portion indicated by the write pointer by the above operation,
Increment the write pointer. The same procedure is repeated when multiple frames are continuously transmitted.

When a round frame is received, the destination address indicated by the read pointer is compared with the destination address in the round frame as shown in FIG. 7, and the read pointer is incremented. If the comparison results are in agreement, the next received circular frame is searched. If they do not match, as shown in FIG. 8, while the read pointer is being updated for the same revolving frame, the destination addresses in the buffer are searched in the order in which they were stored, and they match the destination address in the revolving frame. Find something. Then, the frame to the destination address before the match (the result does not match) is determined to be lost, and the procedure for sending again is performed (see FIG. 9).

The above-mentioned destination address storage buffer stores and manages only the destination address, but the present invention is not limited to this. The second method of detecting lost frames according to the present invention is to use a timer in addition to the destination address. There are two ways to use this timer. First, a method of using the first timer will be described. For example, the configuration of the destination address storage buffer 102 shown in FIGS. 10 to 14 may be adopted. 10 to 14, the destination address storage buffer 102 stores the destination address and the writing time at the time of transmission. The storage of the destination address is the same as described above except that the writing time is added.

At the time of communication, the destination address and time are also written and the pointer is incremented (see FIG. 11). Further, for example, one timer checks the difference between the destination write time of the transmission frame indicated by the read pointer and the current time at regular intervals to check whether the time-out time has passed (see FIG. 12). Further, as shown in FIG. 13, when the frame circulates and returns before the time-out time elapses, it is searched whether the destination addresses match, and if they match, the write time is calculated for the next destination address. Inspect the transit time.

When a time-out is retrieved,
As shown in FIG. 14, the difference from the present is checked at regular intervals, but when the timeout occurs, the read pointer is incremented and the elapsed time is monitored based on the write time of the next registered destination address. To do. At this time, the frame for the destination address that has timed out is retransmitted.

The management of this destination address storage buffer is
The sending time is stored in the buffer together with the destination address before continuous transmission, and the time elapse after sending is calculated for the first sent destination address at regular intervals, and the frame is If the frame does not return after going around, it is determined that the frame has disappeared. Immediately after detecting this disappearance, the time lapse after transmission from the detection time of the next transmitted frame is monitored as before. In this method, it is not necessary to provide a timer corresponding to the frame, and further, it is possible to detect the transmission of the frame without the system condition that the frame is always transmitted within a fixed time.

Next, a method of using the second timer will be described. That is, according to the method of using the second timer, the management of the destination address storage buffer described above is performed with the following configuration. As described above, the destination address and the sending time are stored in the destination address storage buffer 102 at the time of sending, as shown in FIG. Then, as shown in FIG. 16, when the destination address is written, the write pointer 110 is incremented.

As shown in FIG. 17, the timer is set only for the destination sent first to detect the timeout. If the frame does not circulate and return even after a timeout, it is determined that the frame has disappeared. After the disappearance is detected, the timeout time is set by referring to the transmission time of the next frame to be transmitted, so that even with continuous transmission, one timer can set the timeout time almost accurately.

That is, as shown in FIGS. 15 to 18, the destination address and the write time are stored as indicated by the write pointer of the ring buffer. Then, the write pointer is incremented. At this time, the timer is also set at the same time. When continuously transmitting a plurality of frames, only the destination address and the write information are registered, and the timer for sending the second corresponding frame is not set.

When the circulating frame returns before the time-out, it is checked whether the destination addresses match as shown in FIG. 17, and if they match, the timer for the next destination address is written based on the write time. Reset the setting of. When the time-out occurs, the read pointer is immediately incremented as shown in FIG. 18, and the frame of the time-out destination address is retransmitted. And write to the timer +
Timeout time-Set the current time. With the above settings, a single timer can simultaneously manage a plurality of frames.

The second method of detecting lost frames in combination with this timer is effective for a system in which, for example, one to several frames are transmitted and then nothing is transmitted for a specific time. <Second Embodiment of the Present Invention> FIG. 19 is a block diagram of a communication apparatus according to a second embodiment of the present invention. The communication device is network control hardware 122, transmission FIFO 123, reception F.
IFO 124, virtual storage table 125, real storage 12
6, a transmission control mechanism 127, a reception control mechanism 128, and a destination address storage buffer 129.

This communication device performs communication by writing the address (virtual address) of the virtual memory table 125 in the transmission frame. Destination address storage buffer 12
9. The virtual storage table 125 and the real storage 126 are provided in the memory. The actual storage 126 is a transmission buffer that stores data frames to be transmitted, a reception buffer that stores data frames received from the token ring network, an empty buffer that is linked when transmitting or receiving, and should be sent from the personal computer to another device. It has a received buffer for storing data.

The virtual storage table 125 is divided into a plurality of areas, and each area corresponds to the ID of each communication device. The reception control mechanism 128 writes the real address of the reception buffer in the real memory (the reception buffer is connected) to the virtual address of the area corresponding to its own ID of each communication device (the reception buffer is connected), and the page state "reception buffer allocation The code of "Done (VP)" is written.

Now, as an example, three communication devices TX1 and TX
2 and TX3 are connected in a ring shape and communication device TX1
A case of transferring data from the communication device to the communication device TX3 will be described. The transmission control mechanism 127 of the communication device TX1 sets the page state of the virtual address to which the transmission buffer is connected among the virtual addresses of the area of the communication device ID of the destination to the code of “transmission state”, and the transmission FIFO 123 stores the virtual address. , Write transfer length. When the transmission control mechanism 127 activates the network control hardware 122, the network control hardware 122 frames the data in the transmission buffer at the real address corresponding to the virtual address and the virtual address itself according to the instruction written in the transmission FIFO. , Broadcast to the network.

Upon receiving the frame from the communication device TX1, the network control hardware of the communication device TX2 reads the virtual address portion of the frame and refers to the page state of the address. Since the area of ID3 in the virtual page address of the communication device TX2 is in the "buffer unallocated state (NA)", the frame is relayed without receiving the data. When the frame reaches the communication device TX3, the network control hardware 122 of the communication device TX3 copies the data to the reception buffer because the virtual address state of the area of ID3 is “reception buffer allocated (VP)”, The state is changed to the “reception completed (RD)” state, the virtual address, the result code (a code indicating the success or failure of transmission / reception), and the transfer data length are written in the reception FIFO 124, and the reception success notification is written in the response area in the frame to write the frame. Relay. The frame finally returns to the communication device TX1 which is the transmission source.

The network control hardware 122 of the communication device TX1 receives this frame, and if the response is successful in reception, rewrites the page state from "transmission state (SD)" to "transmission completed state (SC)" and the reception FIFO 124.
Write the virtual address and result code to. The reception control mechanism 128 monitors the reception FIFO, confirms that the result code has been successfully transmitted, and that the page state corresponding to the virtual address is "transmission completed (SC)", and then the transmission buffer as shown in FIG. Is connected to the free buffer queue in the real memory 126. At this time, the end address of the buffer queue becomes the end address of the connected empty buffer.

On the other hand, the reception control mechanism 128 of the communication device TX3 which has received the data reads out the reception FIFO 124, the result code is successful reception, and the page state corresponding to the virtual address is "reception completed (RD)". Confirmed,
The receive buffer containing the data is connected to the received buffer queue as shown in FIG. Communication is performed as described above. At this time, the end address of the buffer queue becomes the end address of the connected reception buffer.

The transmission control mechanism 127 connects transmission buffers to a plurality of virtual addresses and continuously writes transmission instructions in the transmission FIFO, so that the transmission control mechanism 128 does not perform transmission confirmation one by one, It is also possible to send data continuously.

The destination address storage buffer 129 is used to detect the loss of a frame. When writing the virtual address to the transmission FIFO 123, the transmission control mechanism 127 sequentially writes the virtual addresses of the frames to be transmitted to the destination address storage buffer (writes a plurality when the continuous transmission is performed), and the frame circulates and returns. At this time, the reception control mechanism 128 executes a lost frame detection process. The virtual addresses stored in the buffer by this detection processing are referred to in order from the oldest one. And
When a frame disappears and is lost on the way, it is detected to which virtual address the frame has disappeared. When the loss is confirmed, the reception control mechanism 128 writes the virtual address of the lost frame in the transmission FIFO 123 and retransmits it. As described above, the lost frame can be retransmitted. <Third Embodiment of the Present Invention> FIG. 22 is a configuration diagram of a network according to a third embodiment of the present invention.

A plurality of nodes 202 (see FIG. 2) are included in the network 201 mainly composed of the optical fiber ring 206.
2, the numbers such as # 000, # ***, # %%%, etc.) are connected.

At node 202, processor bus 2
A plurality of processors 204 are connected to 05, and the processor bus 205 is accommodated in the message communication device 203. The message communication device 203 includes the processor bus 20.
5, the processor 204 processes the message data transmitted or received, and also processes the frame in which the message data input to or output from the optical fiber ring 206 is stored. This message communication device 203
The configuration of the buses within is most relevant to the present invention.

Next, FIG. 23 is a configuration diagram of the message communication device 203 in the node 202 of FIG. 22 in the embodiment of the present invention. The real memory 307 functions as a communication buffer that temporarily holds message data.

The control memory 308, for each virtual page address in the virtual storage space used for message communication, if the virtual page address is allocated to the real page address in the real memory 307, the real page address. The address and data indicating the page state (communication state) of the virtual page address are stored.

The processor bus interface 312 is
22 is connected to the external bus 301 while accommodating the processor bus 205 shown in FIG. 22, and message data or the like input from the processor 204 shown in FIG. 22 via the processor bus 205 is real memory via the external bus 301 and the virtual memory controller 309. To the virtual memory controller 309 from the real memory 307.
Message data or the like input via the external bus 301 and the processor 20 via the processor bus 205.
Output to 4.

Further, the processor bus interface 31
2 exchanges communication control data with the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302. Normally, the bus coupling unit 311 does not connect the external bus 301 and the CPU bus 302, and
Alternatively, the # 1 processor bus interface 312 accesses the external bus 301 to exchange message data with the real memory 307, and the CPU 313.
The operation of accessing the CPU bus 302 to access the real memory 307 or the control memory 308 can be performed independently and in parallel. As a result, the throughput of the entire message communication device 203 is improved.

Although not explicitly shown in FIG. 22, in FIG.
Two processor buses 205 are provided for each node. Therefore, the processor bus interface 312
Also, two # 0 and # 1 are provided corresponding to each processor bus 205. Then, the # 0 processor bus interface 312 uses the control line 319 so that each of the # 0 and # 1 processor bus interfaces 312 is connected to the external bus 301.
Conflict control when accessing. Further, the processor bus interface 312 of # 0 has control lines 321 and 3
22 via the CPU bus arbiter 314 and I / O controller 315, which will be described later, while exchanging control data relating to bus use, the external bus 301 is subjected to contention control and, if necessary, via the control line 320. The opening / closing control of the bus coupling unit 311 is performed.

The network control circuit 310 receives the CPU bus 302, I from the CPU 313 at the time of frame transmission.
A control memory 308 via a control memory access bus 306 based on a transmission command input via the I / O controller 315 and the network command / result bus 303.
While accessing, read message data to be transmitted from the real memory 307 via the virtual memory controller 309 and the network data transmission bus 305, construct a transmission frame including the message data, and send it to the optical fiber ring 206. The transmission result is sent to the network command / result bus 303 and the I / O controller 31.
5 and the CPU 313 via the CPU bus 302.

Further, the network control circuit 310 receives the frame from the optical fiber ring 206, and the control memory 308 via the control memory access bus 306.
Access the received frame to another node 2
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 30
4 to the real memory 307 via the virtual memory controller 309, and the reception result is notified to the CPU 313 via the network command / result bus 303, the I / O controller 315, and the CPU bus 302.

The CPU 313 is connected to the CPU bus 302 and is connected to the CPU bus 302 at the start of operation.
It operates according to a control program written from the PROM 316 to the program RAM 317 connected to the CPU bus 302.

This CPU 313 has a CPU bus 302,
Communication control data is exchanged with the processor bus interface 312 via the bus coupling unit 311 and the external bus 301.

Further, the CPU 313, when transmitting a frame, uses the CPU bus 302, the I / O controller 315,
And output a send command to the network control circuit 310 via the network command / result bus 303, and thereafter
From the network control circuit 310, a network command /
Result bus 303, I / O controller 315, and CP
The transmission result notification is received via the U bus 302. Conversely, the CPU 313 receives from the network control circuit 310 the network command / result bus 303, the I / O controller 315, and the CPU bus 3 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 313 has a CPU bus 302.
The page state data (data indicating the communication state) of each virtual page address in the control memory 308 is accessed via the CPU memory 302 and the virtual page address of each virtual page address in the control memory 308 is accessed via the CPU bus 302 and the virtual memory controller 309. The page address data and the real memory 307 are accessed.

The I / O controller 315 is connected to the CPU bus 302 and accommodates a peripheral device bus 318 to which external peripheral devices are connected. In addition, I / O controller 3
As described above, the relay unit 15 relays the transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 313 and the network control circuit 310 via the CPU bus 302 and the network command / result bus 303.

Further, the I / O controller 315 uses the CP
The address that U313 uses to access the external bus 301 is C
When specified for the PU bus 302, the control line 322
To the processor bus interface 312 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 314 is a C bus from the processor bus interface 312 via the control line 321.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 313 via the control line 323, and the CPU 3
13 receives a bus use permission (bus grant acknowledge) from the control line 323 through the control line 323, and based on that, the CPU
Bus access permission (bus grant acknowledge) is sent via the control line 321 to the # 0 processor bus interface 3
Return to 12.

The virtual memory controller 309 is
Processor bus interface 312 and real memory 307
Data exchanged with the external bus 301 via the external bus 301, C
Data transmitted and received between the PU 313 and the real memory 307 or the control memory 308 via the CPU bus 302, and between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305. The switching control and the contention control of the exchanged data are performed.

The operation of the embodiment of the present invention having the above configuration will be described. <Overall operation of inter-processor communication> Now, FIG. 22 and FIG.
In the following, the overall operation in the case of transmitting message data from one processor 204 in the node 202 of # 000 to another processor 204 in the node 202 of # *** will be described.

In this case, the message data transmitted from one processor 204 in the node # 000 is the message communication device 203 in that node (hereinafter, the message communication device 203 in # 000) via the processor bus 205. Call)) to the real memory 307,
It is sent to the real memory 307 of the message communication device 203 in the node 202 of # *** (hereinafter referred to as the message communication device 203 of # ***), and then the destination from the real memory 307 via the processor bus 205. The processor 204
Transferred to. That is, the real memory 307 of each message communication device 203 functions as a communication buffer. <Communication method between message communication apparatuses 203> Here, a special method called a network virtual storage method is applied to communication of message data between the message communication apparatuses 203.

First, a virtual storage space is defined in the entire network 201 of FIG. This virtual memory space is
It is divided into a plurality of virtual pages, and communication of message data is performed via this virtual page. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data.
Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 203 of each node 202 connected to the network 201 is allocated every predetermined number of pages of this virtual storage space, for example, every 16 pages. For example, the message communication device 203 of the # 000th node 202 is allocated to the 0000 to 000F page, the message communication device 203 of the # 001th node 202 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers 0 to F), the message communication device 203 of each node 202 of the # *** th and # %%% th is assigned.

Therefore, in the above example, the network 20
1, a maximum of 4095 message communication devices 203 from # 000 to #FFF can be connected. On the other hand, the real memory 307 in each message communication device 203 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 307 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, in the control memory 308 of each message communication device 203, as shown in FIG.
Control data for all virtual page addresses is stored. As shown in FIG. 24, the control data of each virtual page address indicates the real page address data of the real memory 307 in the own message communication device 203 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 202
In the control memory 308 of the message communication device 203 in the internal message communication device 203, the virtual page address assigned to the node 202 is set to an arbitrary empty page in the real memory 307 of the message communication device 203 by the network reception control function of the CPU 313. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are respectively written in advance. The network reception control function is a CP
This is realized by the U313 executing the control program stored in the program RAM 317.

For example, the # 000 message communication device 203
In the control memory 308 of the own message communication device 2
As shown in FIG. 24, each virtual page address of 0000,0001, ..., 000F pages allocated to the 03 is assigned to each real page of s, q, ..., p in the real memory 307. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

Further, in the control memory 308 of the message communication device 203 of # ***, the own message communication device 20
As shown in FIG. 24, v, u, and v in the real memory 307 are assigned to the virtual page addresses of the **** 0, *** 1, ... .., t are written, and the page state VP indicating the receive buffer allocation state is written.

Similarly, the message communication device 203 of # %%%
In the control memory 308 of the own message communication device 2
As shown in FIG. 24, each virtual page address of the %%% 0, %%% 1, ..., %%% F page allocated to No. 03, y, w, in the real memory 307 is , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
Message data is transferred from one processor 204 in the node # 000 202 to a network transmission buffer (to be described later) whose real page address is r in the real memory 307 of the message communication device 203 of FIG. To do.

The network transmission control function of the CPU 313 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 307 via the CPU bus 302 and the virtual memory controller 309. By doing so, the virtual page address assigned to the node 202 in which the processor 204 corresponding to the destination address is accommodated is determined as the one whose page state is the buffer unallocated state NA. In the example of FIG. 24, for example, the virtual page address *** 2 is determined. The network transmission control function is performed by the CPU 313 in the program RAM 317.
It is realized by executing the control program stored in.

Next, the network transmission control function of the CPU 313 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the determined virtual page address in the control memory 308, and the page is written. Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 24, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The network transmission control function of the CPU 313 is the transmission F function in the I / O controller 315.
The virtual page address and the transfer length of the message data described above are written to the IFO via the CPU bus 302 together with the transmission command.

When the network control circuit 310 reads the above-mentioned transmission command and the like from the transmission FIFO in the I / O controller 315 via the network command / result bus 303, the virtual page added to the transmission command. An address is designated to the control memory 308 via the control memory access bus 306, the real page address set in the above-mentioned virtual page address is read from the control memory 308, and set in the DMA transfer register in the virtual memory controller 309. To do.

Then, the network control circuit 310 is
The page data of the real page address in the real memory 307 including the message data to be transmitted to the virtual memory controller 309 is transferred to the network control circuit 310 via the network data transmission bus 305.
To DMA transfer.

The network control circuit 310 takes out the message data corresponding to the transfer length of the message data added to the send command from the above-mentioned page data, and the message data and the virtual page address added to the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 206, and the network control circuit 310 can send a transmission frame only when a free token circulating on the optical fiber ring 206 is acquired. .

In the example of FIG. 24, the transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 307 is sent from the message communication device 203 of # 000. It is sent to the optical fiber ring 206.

The above-mentioned transmission frame is sequentially transferred to another node 202 (see FIG. 22) connected to the optical fiber ring 206. When the network control circuit 310 of the message communication device 203 in each node 202 fetches the transmission frame from the optical fiber ring 206, the page state corresponding to the virtual page address stored in the transmission frame is set to the control memory access bus 3
Read from the control memory 308 via 06, whether the page state is the receive buffer allocation state VP, that is,
Whether or not the virtual page address is assigned to the message communication device 203 of the own node 202, or whether or not the page state is the transmission state SD, that is, the transmission frame is transmitted by the own network control circuit 310. Or not.

When the network control circuit 310 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is taken into the real memory 307 as follows.

That is, the network control circuit 310 first specifies the virtual page address stored in the transmission frame to the control memory 308 via the control memory access bus 306, and the control memory 308 changes the virtual page address to the above virtual page address. The set real page address is read out and set in the DMA transfer register in the virtual memory controller 309. Then, the network control circuit 310 causes the virtual memory controller 309 to
The message data included in the transmission frame is DMA-transferred to the above-mentioned real page address in the real memory 307 via the network data reception bus 304.

After that, the network control circuit 310
The virtual page address stored in the transmission frame is
Control memory 30 via control memory access bus 306
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.

Further, the network control circuit 310 is
The virtual page address extracted from the transmission frame and the transfer length of the message data are written into the reception FIFO in the / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 310
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 206, the transmission frame is sent to the optical fiber ring 206 again.

For example, in the example of FIG. 24, the network control circuit 310 of the message communication device 203 of # *** is # 0.
The virtual page address *** 2 stored in the transmission frame from the node 202 of 00 is stored in the transmission frame by determining that the page state on the control memory 308 is the reception buffer allocation state VP. The message data is sent to the real memory 3 having the real page address u set to the virtual page address *** 2 of the control memory 308.
After loading in the network receive buffer in 07,
The page state of the virtual page address *** 2 of the control memory 308 is changed from the reception buffer allocation state VP to the reception completion state RD.

The above-mentioned reception result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The U313 network reception control function uses the reception F in the I / O controller 315 via the CPU bus 302.
When the above reception result notification is received from the IFO and if the result code is successful in reception, the virtual page address which is a part of the reception result notification is designated to the control memory 308 via the CPU bus 302, and the page state Read the real page address.

If the above-mentioned page state is the reception completion state RD, the network reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

Thereafter, the network reception control function of the CPU 313 controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect an arbitrary empty page to the network reception buffer, and further Control memory 3 via CPU bus 302 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

Thereafter, the processing for the processor transmission waiting buffer queue in the real memory 307 is performed by the CPU 31.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 310 reads the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 206.

For example, in the example of FIG. 24, the network control circuit 310 of the # %%% message communication device 203 uses # 0
By determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 of 00 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is It is sent to the optical fiber ring 206 as it is.

Optical fiber ring 206 as described above
The transmission frame sequentially transferred above returns to the network control circuit 310 of the message communication device 203 in the node 202 which is the transmission source.

The network control circuit 310 of the transmission source
As a result of reading out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 310.

In this case, the network control circuit 310
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 308 of the control memory 308 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 306. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 310 is
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The network transmission control function of the U313 is performed by the reception F in the I / O controller 315 via the CPU bus 302.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 308 via the CPU bus 302, and the page status is changed. Read the real page address.

If the above-mentioned page state is the transmission completion state SC, the network transmission control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 313 controls the control memory 3 via the CPU bus 302 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 201 (see FIG.
2), one virtual storage space is defined above,
A virtual page having a fixed data length that constitutes this space is assigned to each message communication device 203. Communication of message data between the message communication devices 203 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 310 of the message communication device 203 in each node 202 on the optical fiber ring 206 receives a transmission frame, the virtual page address stored in the transmission frame causes the network control circuit 310 on the control memory 308. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, a response region is provided in the transmission frame transferred on the optical fiber ring 206, and the network control circuit 310 of the message communication device 203 in the node 202 on the reception side transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 206. Therefore, by the time this transmission frame is transferred on the optical fiber ring 206 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, the communication of the message data between the message communication devices 203 is performed using the real memory 307 while the network control circuit 310 in the message communication device 203 accesses the control memory 308, and the processor 204 and the message communication device 203. The communication of message data between 203 is performed by the message communication device 2 as described later.
The processor bus interface 312 in 03 uses the real memory 307 independently of the operation of the network control circuit 310 described above. Further, the correspondence between the message data stored in the real page address in the real memory 307 and the virtual page address in the virtual storage space is as described below, in which the CPU 313 sends the destination address in the header added to the message data. Based on. Therefore, between the processor 204 and the message communication device 203,
Message communication device 203 and message communication device 203
It is possible to efficiently perform the processing between them at high speed.

In the communication between the above-mentioned communication devices, so-called message communication devices 203, the third embodiment of the present invention has a configuration in which a lost frame is detected and retransmitted. When the network control circuit 310 transmits a frame, that is, when a token is acquired and a busy token is transmitted, the token network 301 in the real memory 307 storing the data file to be transmitted is stored.
The destination address is stored in the destination address storage buffer 102 in the real memory 307. The destination address storage buffer 102 has the configuration shown in FIG. 5, FIG. 10, FIG. Then, the network control circuit 310 sends the file stored in the real memory 307 by the above-mentioned operation.

When receiving, the network control circuit 310 receives the reception FIFO1 of the I / O controller 315.
The virtual address and the result code are written in 24. When receiving this, the network control circuit 310 changes from the transmission state to the transmission completion state. The CPU 413 reads out the information stored in the FIFO 124 and compares it with the address in the destination address storage buffer provided in the real memory 407. Then, when they match, it is determined that the transmission is normally performed, and the read pointer of the destination address storage buffer 102 is incremented. For example, when the information stored in the destination address storage buffer is only the destination address, the CPU compares the destination addresses stored in the oldest order, that is, at the position indicated by the read pointer, and compares If not, it is assumed that the frames stored in the destination address storage buffer until the coincidence are not normally transmitted, and the number of frames are retransmitted. In this resending process, the transmission FIFO 1 which the CPU 413 sends to the I / O controller 315 is transmitted.
This is done by instructing 23.

The CPU 313 described above compares the destination addresses to determine whether or not they have disappeared, but the present invention is not limited to this. For example, as described above, one timer is provided, and when the CPU 313 sends a file, the sending time of the first file is set and the timer is instructed to interrupt after a specific time. Is set to the next time-out time, and the operation is repeated sequentially until only the lost frame times out.
The lost frame can be detected. Further, a timer interrupt may be given at regular intervals, and it may be determined whether or not a specific time period has elapsed and the lost frame may be detected. <Transfer Operation of Message Data from Processor 204 to Message Communication Device 203 at Transmission Source> Next, the transmission source node 202 (node # 000 20 in the example of FIG. 24)
The operation when the message data is transferred from one processor 204 in 2) to the real memory 307 of the message communication device 203 in the node will be described.

First, the processor reception control function of the CPU 313 accesses the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect the processor reception buffer queue to the free buffer queue in the real memory 307. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 313 executing the control program stored in the program RAM 317.

Then, the processor reception control function of the CPU 313 activates, for example, the # 0 processor bus interface 312 via the CPU bus 302, the bus coupling unit 311, and the external bus 301, and The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 312 is
The message data transferred from the processor 204 via the processor bus 205 is received, and the received message data described above is updated while sequentially updating the buffer address with the start address as the reception start address.
External bus 301 and virtual memory controller 30
9 is sequentially transferred to an empty buffer connected to the processor reception buffer queue in the real memory 307.

The processor bus interface 312 is
When there is no free buffer connected to the processor reception buffer queue, the free buffer is automatically stopped, and the fact is notified to the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

The processor reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to separate the above-mentioned received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. Thereafter, the processing for the network transmission buffer in the real memory 307 is transferred from the processor reception control function of the CPU 313 to the network transmission control function described above, and the transmission source of the transmission source is transmitted in accordance with the communication method between the message communication devices 203 described above. From the real memory 307 in the message communication device 203 of the node 202 (# 000 message communication device 203 in the example of FIG. 24), the message communication device 203 of the node 202 (in the example of FIG. 24, the processor 204 of the destination is accommodated. The message data transfer operation to the real memory 307 in the message communication device 203) of # *** is executed. <Message Data Transfer Operation from Message Communication Device 203 to Processor 204 on Receiving Side> Next, the receiving node 202 (in the example of FIG. 24, the node 20 of # ***)
The operation when the message data is transferred from the real memory 307 of the message communication device 203 in 2) to one processor 204 in the node 202 will be described.

When the network control circuit 310 succeeds in receiving the transmission frame, as described above, the CPU 313
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 307.

On the other hand, the processor transmission control function of the CPU 313 includes the CPU bus 302 and the bus coupling unit 31.
For example, the # 0 processor bus interface 312 is activated via 1 and the external bus 301, and the interface 312 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 312 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 30 is accessed via the external bus 301 and the virtual memory controller 309.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 205. Via the destination processor 204.

[0116]

As described above, according to the present invention, in a system for continuously transmitting and receiving a plurality of frames,
Loss of a plurality of frames can be detected and retransmitted without using one timer or even a timer, and system reliability can be improved. In addition, it is possible to detect the lost frame and retransmit it while reducing the overhead for detecting the loss.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of a lost frame retransmission device according to the first embodiment of the present invention.

FIG. 3 is a flowchart of a transmission process according to the first embodiment of this invention.

FIG. 4 is a delivery confirmation processing flowchart of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a destination address storage buffer and a pointer.

FIG. 6 is an explanatory diagram of a destination address storage buffer and a pointer during transmission.

FIG. 7 is an explanatory diagram of a destination address storage buffer and a pointer when receiving a circular frame.

FIG. 8 is an explanatory diagram of a destination address storage buffer and a pointer when the destination address of the circulating frame matches.

FIG. 9 is an explanatory diagram of a destination address storage buffer and a pointer when the destination address of the circulating frame does not match.

FIG. 10 is an explanatory diagram of a destination address storage buffer and a pointer.

FIG. 11 is an explanatory diagram of a destination address storage buffer and a pointer during transmission.

FIG. 12 is an explanatory diagram of a destination address storage buffer and a pointer at the time of comparison at regular intervals.

FIG. 13 is an explanatory diagram of a destination address storage buffer and a pointer when the destination address of the circulating frame matches.

FIG. 14 is an explanatory diagram of a destination address storage buffer and a pointer at the time of timeout.

FIG. 15 is an explanatory diagram of a destination address storage buffer and a pointer.

FIG. 16 is an explanatory diagram of a destination address storage buffer and a pointer during transmission.

FIG. 17 is an explanatory diagram of a destination address storage buffer and a pointer when the circulating frame and the destination address match.

FIG. 18 is an explanatory diagram of a destination address storage buffer and a pointer at the time of timeout.

FIG. 19 is a configuration diagram of a communication device according to a second embodiment of the present invention.

FIG. 20 is an explanatory diagram of an empty buffer queue.

FIG. 21 is an explanatory diagram of a received buffer queue.

FIG. 22 is a configuration diagram of a network according to the third embodiment of this invention.

FIG. 23 is a configuration diagram of a message communication device according to a third embodiment of the present invention.

FIG. 24 is an explanatory diagram of message communication.

[Explanation of symbols]

 1 frame continuous sending means 2 destination address buffer 3 searching means 4 resending means

Claims (6)

[Claims] 1. A communication method in which a transmitted frame that circulates around a network and returns is detected to detect a lost frame, and a lost frame is retransmitted. In this communication method, destination addresses of frames to be continuously transmitted are sequentially stored and transmitted. A method of retransmitting a lost frame, characterized in that it is determined whether the frame has gone around and returned, and the frame that has not returned is retransmitted as a lost frame. 2. A communication device, which is connected to a network, detects a lost frame by monitoring a transmitted frame that circulates and returns the network, and retransmits the lost frame. Means (1), a destination address buffer (2) for sequentially storing destination addresses of frames to be transmitted, and a destination stored in the destination address buffer (2) when the frames to be transmitted return in a loop. And a retransmission control means (4) for controlling the retransmission of the frame corresponding to the destination address in the destination address buffer (2) not detected by the retrieval means. A lost frame retransmitting device. 3. A destination address stored in the destination address buffer (2) and not yet detected as a circular frame destination address by the searching means (3) every time a transmission frame circulates and returns. 3. The lost frame retransmitting apparatus according to claim 2, wherein among the oldest destination addresses, the matching destination addresses are searched in order, and the frames of the non-matching destination addresses are set as the lost frames. 4. The destination address buffer (2) stores a destination address of a transmission frame and also stores a transmission time of the frame, and the searching means (3) further stores the destination address buffer (2). When the sending time of the oldest destination address that has not been read and the current time are compared for each specific period, the frame wraps around and does not return even if the time difference becomes longer than the specific time. 3. The lost frame retransmitting device according to claim 2, further comprising a time-out means for determining that the frame has disappeared. 5. The destination address buffer (2) stores the destination address of the transmission frame and also stores the transmission time of the frame, and the search means (3) still reads from the destination address buffer. A timer is set for the oldest destination address that has not been issued, and it is assumed that the frame has disappeared if the frame does not circulate and return even if the timer times out. 3. The lost frame retransmitting device according to claim 2, further comprising a time-out means for setting a time-out time for the frame of the destination address from a transmission time of the frame. 6. The lost frame retransmitting apparatus according to claim 4, wherein the transmission time is a time when the destination address is registered.