JPH0637328A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize a semiconductor storage device having a writing efficiency improved without impairing operational stability at the time of reading, regarding the semiconductor storage device constructed of EPROM memory cells. CONSTITUTION:In a semiconductor storage device in which each memory cell is an EPROM memory cell equipped with a transistor 1, a floating gate 4 provided in proximity to a channel of the transistor l and insulated from the surroundings and a control gate provided in proximity to the floating gate 4 and joined with the floating gate 4 in terms of capacity, each memory cell is equipped with two control gates 5 and 6 being controllable discretely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device called EPROM which can erase the stored contents by irradiating it with ultraviolet rays or the like.
Regarding ROM.

[0002]

2. Description of the Related Art A semiconductor memory called an EPROM which is writable by a user, retains stored contents even when the power is turned off, and can be repeatedly updated by irradiating ultraviolet rays or the like to erase the stored contents. The device is widely used as an element for storing a program in a computer.

FIG. 6 is a diagram for explaining the structure of an n-channel EPROM memory cell which is mainly used at present. In the figure, 62 is a drain and 63 is a source. 64 is a floating gate, which is the insulating film 6
It is insulated from the surroundings by 8. A control gate 65 is capacitively coupled to the floating gate 64.

In the cell of FIG. 6, the control gate 65
Data is stored by utilizing the fact that the seen threshold voltage differs depending on whether or not charges are accumulated in the floating gate 64. Writing is performed by applying a high voltage to the control gate 65 and the drain 62 and injecting electrons (hot electrons) having high energy generated near the drain 62 into the floating gate. Further, the erasing is performed by applying ultraviolet rays to discharge the charges in the floating gate 64.

FIG. 7 is a diagram showing the overall structure of the EPROM. In the figure, reference numeral 70 denotes the memory cells shown in FIG. 6, which are arranged in a matrix. A row decoder 71 outputs a row decode signal for selectively driving the word line 75 connected to the control gate of the memory cell 70 in each row. Reference numeral 72 denotes a column decoder, which outputs a column decode signal that selectively turns on the switches of the switch column 74 that connects the plurality of bit lines 77 and the bit line control unit 73. The drain of each memory cell 70 is connected to the bit line of the column to which the memory cell belongs. By applying the address signal to the row decoder 71 and the column decoder 72, one word line and one bit line are brought into a selected state, and the memory cell located at the intersection is selected.

At the time of writing, the voltage applied to the word line and the bit line is changed according to the data to be written. When writing data corresponding to the state where electrons are injected into the floating gate, a high voltage is applied to the word line and the bit line. At the time of reading, a voltage lower than that at the time of writing is applied to the word line and the bit line. As mentioned above, the threshold voltage of the transistor seen from the control gate differs depending on whether electrons are stored in the floating gate, but the voltage applied to the word line is that the transistor is conductive unless electrons are stored in the floating gate. However, the level is set so that it does not conduct if electrons are accumulated. As a result, if no electrons are stored in the floating gate, the transistor becomes conductive and electricity flows in from the bit line 77. If electrons are stored, the transistor does not become conductive and no electricity flows in the bit line 77. If the sense amplifier of the bit line controller 73 detects this difference in current, the written data can be read.

FIG. 8 is a diagram showing a configuration example of a conventional EPROM cell. A plan view is shown in (a) and an AA ′ line in FIG. 8 is shown so that an actual structural shape can be understood. A sectional view of a portion is shown. In the figure, 82 is a drain and 83 is a source, and a channel portion 88 of the transistor is formed in the middle portion thereof. A floating gate 84 is made of polysilicon. Reference numeral 85 is a control gate.

[0008]

The EPROM memory cell has a structure as shown in FIGS. 6 and 8, and an equivalent circuit thereof is shown in FIG. In the figure, 91 is a transistor, and 92 and 93 are a drain and a source, respectively. 94 is a floating gate, and 95
Is the control gate. As shown in FIG. 6, the floating gate 94 is covered with an insulating film, and the channel portion of the transistor 91 and the control gate 95 are capacitively coupled. Floating gate 94, channel and drain 92, source 93
The capacitance between the and C _D, the capacitance between the floating gate 94 and control gate 95 and C _U.

The potential of the floating gate 94 is set to V_F,
The voltage of the control gate 95 is V _PExpressed as
Charge accumulated in the gate 94_FTo
And V_FIs expressed by the following equation.

[0010]

[Equation 1] Q _F is the charge accumulated in the floating gate 94, which is zero before writing and has a negative value by writing. Therefore, even if the same voltage is applied to the control gate 95 when the charges are accumulated,
The potential V _F of the floating gate 94 is lower than that when no charge is stored.

V_FAnd V_PThe relationship of is as shown in equation (1)
2 capacity C_UAnd C_DCan be affected by the ratio of
It Ie C_U/ C_DThe larger is V_FIs V_PApproaching
growing. As mentioned above, when writing, floaty
It is desirable that the long gate 94 has a high potential. That
Therefore, a high voltage is applied to the control gate 95, but C
_U/ C_DIs small V_FDoes not become a large value, and V_FWhere
V for a constant value _PMust be higher
There is a problem. Therefore C_U/ C_DIncreased
It can be said that the writing efficiency is better.

Further, the potential V _{F of the} floating gate 94
There is a threshold value for whether or not the transistor becomes conductive, and the value is v _th . The V _F of the equation (1) is set to this v _th
And the corresponding threshold value V _th of the control gate 95 is calculated by the following equation.

[0013]

[Equation 2] The change ΔV _th of the threshold V _th depending on whether or not electric charge is accumulated in the floating gate 94 is represented by the following equation.

[0014]

[Equation 3] As is clear from the equation (3), the threshold change ΔV _th decreases as C _U increases. As described above, the voltage V _P of the control gate 95 at the time of reading is set so that the transistor is turned on or off depending on whether or not electric charge is accumulated in the floating gate 94, that is, whether Q _F is a predetermined negative value or zero. Stipulated in. Therefore, if various errors are taken into consideration, the larger ΔV _th , the less erroneous operation during reading and the more stable operation becomes possible. Therefore C _U
Is preferably small.

However, as described above, it is desirable to increase C _U / C _D in order to increase the writing efficiency, which is a conflict with the above-mentioned reduction of C _U.
Therefore, under the present circumstances, it is impossible to increase C _U / C _D, and there has been a problem that a high voltage must be applied to the control gate or the writing time must be lengthened accordingly.

The present invention has been made in view of the above problems, and an object of the present invention is to realize an EPROM having improved write efficiency without impairing stable operation.

[0017]

FIG. 1 is a diagram showing the principle configuration of the present invention. In the semiconductor memory device of the present invention, each memory cell has a transistor 1, a floating gate 4 provided near the channel of the transistor 1 and insulated from the surroundings, and a floating gate 4 provided near the floating gate 4. An EPROM memory cell having a control gate capacitively coupled to.

In order to solve the above problems, each memory cell is provided with two control gates 5 and 6 which can be controlled independently.

[0019]

FIG. 2 is an equivalent circuit diagram of the EPROM cell of the present invention. The operation of the EPROM cell of the present invention will be described below with reference to this drawing. Comparison between the equivalent circuit of the conventional EPROM memory cell shown in FIG. 9 and the equivalent circuit of FIG. 2 shows that the control gate is composed of a first control gate 5 and a second control gate 6 which can be controlled independently. is there. The capacitance between the floating gate 4 and the first control gate 5 is C _U1, and the capacitance between the floating gate 4 and the second control gate 6 is C _U2 .

At the time of writing, the first control gate 5
When the voltage V _P ′ is applied to both the second control gate 6 and the second control gate 6, the potential V _F ′ of the floating gate 4 is expressed by the following equation.

[0021]

[Equation 4] In the above equation, Q _F represents the charge stored in the floating gate. When reading, set one of the control gates to "H" level and the other to "L" level.
Set to level. For example, when the voltage V _P is applied to the first control gate 5 and the second control gate 6 is grounded, the potential V _F of the floating gate 6 at that time is represented by the following equation.

[0022]

[Equation 5] The change ΔV _{th in} the threshold value seen from the first control gate 5 at this time is expressed by the following equation according to the above description.

[0023]

[Equation 6] As is clear from the equation (4), the writing efficiency is (C _U1 +
Influenced by C _U2 ) / C _D , the larger this value, the higher the writing efficiency. Further, it is apparent from the equation (6) that the change ΔV _{th in} the threshold value indicating whether the transistor is conductive or not during reading is influenced only by C _U1 . Therefore C
_While keeping _U1 at a small value that allows stable operation, (C _U1
+ C _U2 ) / C _D can be increased, and the writing efficiency can be improved as compared with the conventional case.

For example, the equivalent circuit of the conventional example shown in FIG.
And C_D: C_U= 1: 10 and C in the equivalent circuit of the present invention.
_D: C_U1: C_U2= 1: 7: 3 setting comparison
For example, C _U/ C_DAnd (C_U1+ C_U2) / C_DAre the same value
Therefore, the writing efficiency is the same. Therefore, when writing the same
Between the two, the charge accumulated in the floating gate 4
Quantity Q_FAre the same. On the other hand, ΔV_thIs about 1.4 times
And the voltage applied to the control gate during reading.
Since the pressure is low, the write data is rewritten when reading
It is difficult to get rash.

On the contrary, if the same ΔV _th is set under the above conditions, the amount of charge injected into the floating gate 4 at the time of writing may be 70% of that in the conventional case, and the writing time can be shortened by that amount.

[0026]

FIG. 3 shows the overall construction of an embodiment of the present invention. In FIG. 3, the column decoder 32, the bit line control unit 33, the bit line selection switch column 34, and the bit line 37 are the same as those in the conventional example shown in FIG.

Reference numeral 30 denotes a memory cell, which has the same structure as that shown in FIG. A row decoder 31 outputs a row decode signal to each of the plurality of first word lines and the plurality of second word lines. The first word line 35 is connected to the first control gate 5 of each memory cell in the row, and the second word line 36 is connected to the second control gate 6.

FIG. 4 is a diagram showing the structure of each memory cell in this embodiment, which corresponds to the conventional example of FIG. 4A is a plan view, and FIG. 4B is a sectional view of a portion indicated by AA ′. In FIG. 4, 42 and 43
Are the drain and the source of the transistor, respectively, and the middle portion thereof is the channel portion 48 of the transistor. Reference numeral 44 denotes a floating gate, the central portion of which is adjacent to the channel portion 48 of the transistor via a gate oxide film 47. Reference numerals 45 and 46 denote a first control gate and a second control gate, respectively, which are adjacent to the floating gate 44 via a gate oxide film 47. Although not shown, the floating gate 44
Is completely covered with an oxide film and insulated from the surroundings. All of the above parts are made by a single layer polysilicon gate process.

As shown in FIG. 4, the area of the overlapping portion between the floating gate 44, the channel portion 48 of the transistor, the first control gate 45 and the second control gate 46 is 1: 7: 3. And has a coupling capacity ratio substantially corresponding to this ratio.
FIG. 5 is a diagram showing an example of applied signals to the control gate and the bit line in the present embodiment, (a) shows applied signals at the time of writing, and (b) shows applied signals at the time of reading. The row decoder 31 and the bit line control unit 33 in FIG. 3 are configured to output an applied signal as shown in FIG.

As shown in FIG. 5A, at the time of writing, the first control gate 45 of the selected memory cell,
A high voltage as shown is applied to the second control gate 46 and the drain 42. Therefore, the row decoder 31 applies a high voltage to the first bit line 35 and the second bit line 36 of the selected row, and the bit line control unit 33 outputs the high voltage. However, when writing the data corresponding to the state in which the charge is not accumulated in the floating gate 34, the high voltage is not applied.

At the time of reading, as shown in FIG.
A voltage is applied to the control gate 35 and the drain 32, and the second control gate 36 is grounded. The voltage applied to the drain 32, that is, the voltage applied to the bit line by the bit line control unit 33 is smaller than that at the time of writing.
First control gate 35, that is, row decoder 31
As shown in the figure, the voltage applied to the first word line 35 is set to a level between a conductive voltage level and a non-conductive voltage level regardless of whether charges are accumulated in the floating gate 34. That is, during this period, there is a difference in whether the transistor is conductive or not depending on the presence or absence of charge accumulation. The above voltage level difference corresponds to the above-mentioned threshold change ΔV _th .

For reading, a signal as shown in FIG. 5B is applied, and the current difference of the bit line depending on whether the transistor of the selected memory cell is conducting or not is detected by the sense amplifier of the bit line control unit 33. It is performed by detecting at 33.

[0033]

According to the present invention, in a semiconductor memory device that is rewritable and the stored contents are maintained even when the power is turned off,
The writing efficiency can be improved without impairing the stability at the time of reading, and the writing time can be shortened and the voltage applied to the word line at the time of reading can be further stabilized.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an equivalent circuit diagram of the EPROM cell of the present invention.

FIG. 3 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 4 is a diagram showing a structure of a memory cell in an example.

FIG. 5 is a diagram showing an applied signal in the example.

FIG. 6 is a structural explanatory diagram of an n-channel EPROM memory cell.

FIG. 7 is a diagram showing an overall configuration of a conventional EPROM.

FIG. 8 is a diagram showing a configuration example of a conventional EPROM memory cell.

FIG. 9 is a diagram showing an equivalent circuit of a conventional EPROM memory cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Transistor 2 ... Drain 3 ... Source 4 ... Floating gate 5 ... 1st control gate 6 ... 2nd control gate

Claims (4)

[Claims] 1. Each memory cell comprises: a transistor (1); a floating gate (4) provided in the vicinity of the channel of the transistor (1) and insulated from the surroundings; and the floating gate (4). In a semiconductor memory device, which is an EPROM memory having a control gate that is provided in close proximity to the floating gate (4) and is capacitively coupled to the floating gate (4), each memory cell has two controllable controls. A semiconductor memory device comprising a gate (5, 6). 2. The semiconductor memory device according to claim 1, wherein the floating gate (4) and the two control gates (5, 6) are made of polysilicon. 3. The semiconductor memory device according to claim 1, wherein the floating gate (4) is made of polysilicon, and the two control gates (5, 6) are made of an impurity diffusion layer. . 4. The semiconductor memory device according to claim 1, wherein a high voltage is simultaneously applied to both of the two control gates (5, 6) when writing to the memory cell, A semiconductor memory device characterized in that, when reading from a memory cell, a high voltage is applied to only one of the two control gates (5, 6) and the other control gate is grounded.