JPH0637272A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device which can be protected against a junction leakage current and a short channel effect. CONSTITUTION:An epitaxial Si layer 9 higher than an impurity diffusion layer 7 in impurity concentration is provided to the impurity diffusion layer 7 of a first MOS transistor formed on the memory cell region on an Si substrate 1, and a filling layer formed of the same material and at the same time with wiring layers 141 and 142 and filled into a contact hole provided to the impurity diffusion layer of the MOS transistor is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM) in which a memory cell is composed of one MOS transistor and one capacitor.

[0002]

2. Description of the Related Art In recent years, high integration of DRAM has been remarkable. Various so-called stack type capacitor cells in which a capacitor is stacked on a transistor have been proposed as a memory cell structure for further increasing the integration of DRAM. This type of memory cell has attracted attention because it can have a large capacitor area and can be formed without digging a groove in a substrate as in the case of a trench type, and therefore can be easily inspected during manufacturing. FIG. 10 shows a sectional view of a memory cell of a conventional DRAM having a stack structure.

In the figure, reference numerals 104 ₁ and 104 ₂ denote word lines (gate electrodes), on which capacitors are projected. The capacitor is formed on the Si substrate 101 divided by the field insulating film 102,
It is composed of a plate electrode 110, a capacitor insulating film 109, and a capacitor base electrode layer (storage electrode) 107, and n through a contact hole opened in the interlayer insulating film 106.
⁺ It is connected to the mold diffusion layer 108.

On the other hand, the MOS transistor has a gate insulating film 103, gate electrodes 104 ₁ , 104 ₂ , and n ^−. Type diffusion layer 105, n ⁺ It is configured as the type diffusion layer 108 and adopts the LDD structure. Then, the bit line 112 is n.sup. ⁺ Via the contact hole opened in the interlayer insulating films 106 and 111. It is connected to the mold diffusion layer 113. However, the conventional stack type memory cell thus configured has the following problems.

First, high integration progresses, for example, 2
Storage capacity (Cs) at an integration level of about 56 Mbits
In order to increase the storage capacity, it is necessary to increase the height of the storage electrode or to make it cylindrical. When such a method is used, the final contact hole depth is 2
For example, the contact hole having a diameter of 0.3 μm has an aspect ratio of 6 or more. As a result, contact holes having various aspect ratios from a deep depth to a shallow depth are mixed, and there is a problem that the manufacturing yield is significantly reduced.

Second, n ⁺ on the Si substrate side Type diffusion layer 11
Since there are 3,108, etc., these n ⁺ Type diffusion layer 1
There is a problem that there is a junction leak between the semiconductor substrate 13 and 108 and the Si substrate 101, which makes it difficult to improve the pause characteristics of the DRAM.

Thirdly, due to the miniaturization, it is becoming difficult to align various contacts with each electrode.
Although some kind of self-alignment method was used, there was a problem that it was very complicated and the manufacturing yield was lowered.

Fourth, in order to increase the area of the capacitor electrode, it is desirable to form the capacitor electrode on the bit line 112, but it is self-aligned with both the word lines 104 ₁ and 104 ₂ and the bit line 112. Moreover, it was difficult to make contact with the diffusion layer, which was difficult to achieve.

[0009]

As described above, in order to further increase the integration density of the stack type DRAM having the conventional structure, firstly, since the very deep contact holes and the shallow contact holes are mixed, the manufacturing yield is remarkably reduced. , Secondly Si
Junction leakage cannot be reduced because the diffusion layer having a high impurity concentration penetrates deeply into the substrate. Thirdly, the self-alignment technique for the gate electrode and bit line electrode is complicated and the manufacturing yield is lowered. There is a problem that it is difficult to self-align with both line electrodes. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can be easily highly integrated.

[0010]

In order to achieve the above object, a semiconductor memory device of the present invention includes a first MOS transistor formed in a memory cell region of a semiconductor substrate and a peripheral circuit region of the semiconductor substrate. A second MOS transistor formed, and provided on the first impurity diffusion layer and the second impurity diffusion layer of the first MOS transistor,
An epitaxial layer having an impurity concentration higher than the impurity concentrations of the first impurity diffusion layer and the second impurity diffusion layer, and the epitaxial layer and the impurity diffusion layer of the second MOS transistor provided on the semiconductor substrate. An interlayer insulating film layer having a contact hole in the
A wiring layer formed on the interlayer insulating film for filling the contact hole on the epitaxial layer of the impurity diffusion layer, and the second MO formed in the same step as the wiring layer.
A filling layer made of the same material as the wiring layer for filling the contact hole on the impurity diffusion layer of the S transistor,
A capacitor electrically connected to the second impurity diffusion layer is provided.

[0011]

In the semiconductor memory device of the present invention, the epitaxial layer having the impurity concentration higher than that of the first impurity diffusion layer and the second impurity diffusion layer is the first impurity diffusion layer and the second impurity diffusion layer. It is provided above. As a result, junction leakage can be reduced, the short channel effect of the transistor can be suppressed, and reliability can be improved. Further, by sticking a silicide layer on the surface of the epitaxial layer, Schottky contact of metal contact can be prevented and ohmic contact can be realized. In addition, the contact margin can be expanded by extending the epitaxial layer also on the field.

Further, in the semiconductor memory device of the present invention, the filling layer is formed in the same step as the wiring layer. That is, by using the wiring layer as the filling layer, the depth of the contact hole in the peripheral circuit region provided by the stack type memory cell becomes shallower by the amount of the filling layer. For this reason, when the contact is made later, the depth of the contact hole is made uniform and the material of the base is made uniform, so that a contact with high yield can be realized.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a memory cell of a stack type DRAM according to an embodiment of the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is a diagram of FIG. 1 (a). FIG. 9 is a cross-sectional view taken along the line AA ′ of the memory cell. 2A and 2B are cross-sectional views taken along the line BB ′ and C- of the memory cell of FIG. 1A, respectively.
It is a C'cross section. Further, FIG. 3 shows the same stack type DRAM.
2A is a plan view and FIG. 1B is a sectional view taken along the line AA ′ of the peripheral circuit in FIG. In the stacked DRAM of this embodiment, the Al wiring layer 29 is used as the shunt layer of the word line 4, and the following four points are different from the conventional one of FIG.

First, the first difference is that the bit line layer 14
Connecting to the Si substrate, n ^- Type or p ^- Type low impurity concentration impurity diffusion layers 7 and 7a (first impurity diffusion layer)
Are formed, and the impurity diffusion layers 7 and 7a are n ⁺ Type or p ⁺ Type epitaxial Si layer 9 of high impurity concentration
It is located above the i-substrate 1 and the silicide layer 10 is formed on the surface of the epitaxial Si layer 9. This can reduce junction leakage, suppress the short channel effect of the transistor, and improve reliability. The silicide layer 10 prevents the Schottky contact of the metal contact and realizes ohmic contact to the n-type and p-type diffusion layers having a high impurity concentration. In addition, the silicide layer 10
Is formed on the surface of the epitaxial Si layer 9, so that the silicide layer 10 is not uniformly distributed in the Si layer in a later thermal process or the like.
It is possible to prevent the junction from breaking into the board 1,
Product yield can be improved.

The second difference is that the Al wiring layer 29 of the peripheral circuit does not directly contact the low-concentration diffusion layer 7a, and the lower bit line 14 ₁ and the upper bit line layer 14 ₂ in the memory cell area are formed. They are formed in the same process and are in contact with each other through filling layers 14 _1a and 14 _2a made of the same material as the lower bit line 14 ₁ and the upper bit line layer 14 ₂ . Therefore, the deep contact holes in the peripheral circuit region provided by the stacked memory cell are not filled with the filling layer 1.
4 _1a, 14 minutes only of the contact hole depth _2a becomes shallower. For this reason, when the contact is made later, the depth of the contact hole is made uniform and the material of the base is also aligned.
A contact with high yield can be realized.

The third different point is that the self-aligned contact to the gate electrode 4 or the bit line 14 is a gate cap layer 5 or a bit line cap layer made of a Si ₃ N ₄ film provided on the surface or the side surface of each electrode. 15. This is done by using only the spacer layer 8 as a stopper layer.

The fourth different point is that the capacitor electrode portion (polycrystalline Si films 20, 22, plate electrode 24) has a plug layer 12 (conductive layer) formed on the epitaxial Si layer 9 and the silicide layer 10 interposed therebetween. And low concentration impurity diffusion layer 7
′ (Second impurity diffusion layer).

That is, the impurity diffusion layer 7'having an effective low concentration is effectively formed.
Has been lifted to a position above the gate electrode 4. Therefore, in the stack type memory cell having the plug layer 12 in which the bit line is formed prior to the storage electrode, it is sufficient to perform self-alignment only to the bit line when forming the capacitor electrode contact in a later step. Can be greatly simplified, and the manufacturing yield can be significantly improved. Next, a method of manufacturing a DRAM having such characteristics will be described with reference to FIGS.

First, FIGS. 4 (a) and 4 (b) (each shown in FIG.
As shown in the plan view of (a) and the cross-sectional view of FIG. 1 (b, the same applies to the drawings after FIG. 4), the impurity concentration is 5 × 10 ¹⁵ cm
^A P-well is formed in the n-channel transistor region and an n-well is formed in the P-channel transistor region on the (100) plane of the p-type or n-type Si substrate 1 of about ^-3 . Then, for example, using reactive ion etching (RIE), Si
The field insulating film 2 is formed by forming a groove in the substrate 1 and filling the insulating film 2 by so-called trench isolation or by the so-called LOCOS method using a Si ₃ N ₄ film. Although the channel stopper layer is not shown here, it is formed if necessary.

Next, after exposing the surface of the Si substrate 1 in the element forming region, a gate oxide film 3 having a thickness of about 10 nm is formed, and a gate electrode 4 is formed on the gate oxide film 3. The gate electrode 4 employs a so-called polycide structure to reduce the resistance, but a simple polycrystalline S
Only the i layer may be used. The lower layer of the gate electrode 4 has a thickness of 1
Polycrystalline S doped with impurities such as phosphorus having a size of about 00 nm
The i-layer 4 ₁ and the upper layer is a tungsten silicide (WSi ₂ ) layer 4 ₂ having a thickness of about 150 nm.

Then, after forming a gate gap layer 5 made of a Si nitride film (Si ₃ N ₄ ) serving as an etching stopper layer for the gate electrode 4 in the later self-alignment process on the WSi ₂ layer 4 ₂ , A resist pattern (not shown) is formed on the gate gap layer 5, and subsequently, using the resist pattern as a mask, the gate gap layer 5, the silicide layer 4 ₂ and the polycrystalline Si layer 4 ₁ are continuously processed. . Next, in order to improve the breakdown voltage between the gate electrode 4 and the low-concentration impurity diffusion layer 7, for example, thermal oxidation is performed at 800 ° C. in an O ₂ atmosphere for about 30 minutes to form a so-called post oxide film 6.

Thereafter, in order to form an LDD structure, a resist pattern (not shown) is formed, and n-type impurity ions are implanted into the desired surface of the Si substrate 1 through the post oxide film 6 to selectively reduce the impurity concentration. The n-type impurity diffusion layer 7 having a high concentration is formed.
Similarly, a low concentration p-type impurity diffusion layer is formed in the p-channel transistor region by ion implantation. The concentration of ion implantation is 5 × 1 for both n-channel and p-channel.
It is about 0 ¹³ cm ^-2 . Next, as shown in FIGS. 5A and 5B, an impurity diffusion layer having a high impurity concentration, which is one of the features of the present invention, is formed.

That is, first, S having a thickness of about 50 nm is formed on the entire surface.
After depositing the i ₃ N ₄ film by the CVD method, the entire surface is etched by the RIE method and the width of the sidewall of the gate electrode 4 is reduced to 50 mm.
A spacer layer 8 made of the above Si ₃ N ₄ film having a thickness of about nm is formed. At this time, the surface of the Si substrate 1 in the region of the low concentration impurity diffusion layer 7 is exposed. Then this exposed S
An epitaxial Si layer 9 having a thickness of about 200 nm is selectively grown on the surface of the i substrate 1.

After that, for example, arsenic ions having a dose amount of about 5 × 10 ¹⁵ cm ⁻² are implanted into the epitaxial Si layer 9 in the n-channel region, so that the epitaxial Si layer 9 in the n-channel region has a high concentration of n-type impurities. Make it function as a diffusion layer. Similarly, in the epitaxial Si layer 9 of the impurity diffusion layer 7 in the p channel region, for example, a dose amount of 5 × 10 5
BF ₂ ^{+ of} about ¹⁵ cm ^-2 Is implanted so that the epitaxial Si layer 9 in the p-channel region functions as a high-concentration p-type impurity diffusion layer.

Next, the silicide layer 10 is formed only on the surface of the epitaxial Si layer 9. This silicide layer 10
Can be formed, for example, by sputtering Ti on the entire surface by 5
Then, a heat treatment for silicidation (for example, heat treatment at 600 ° C., N ₂ , 30 minutes) is performed, and finally the unreacted Ti layer on the gate gap layer 5 and the spacer layer 8 is removed. To do. As a result, the silicide layer (TiSi ₂ ) 10 can be selectively formed only on the exposed surface of the epitaxial Si layer 9. As another silicide material, for example, nickel silicide, cobald silicide, or the like may be used. Next, as shown in FIG.
As shown in (b), the plug layer is formed using the self-aligned etching technique for the capacitor electrode portion, which is one of the features of the present invention.

That is, first, as the interlayer insulating film 11, for example, a BPSG film is deposited to a thickness of about 600 nm by the CVD method, and then the so-called chemical mechanical polishing method of chemically and mechanically polishing the entire surface of the substrate is used to form the gate electrode. Flattening etching is performed so that the film thickness of the inter-layer insulating film 11 on 4 is about 200 nm. Where other flattening methods,
For example, a so-called resist etch-back method may be used in which a resist is applied to planarize the base and then etching is performed under the condition that the etching rates of the resist and the insulating film are substantially equal.

Next, a resist pattern for contact holes (not shown) for making contact between the capacitor electrode portion and the low-concentration impurity diffusion layer 7'on the interlayer insulating film 11.
Is formed, and using this as a mask, the interlayer insulating film 11 is selectively etched to expose the silicide layer 10 to open a contact hole. The selective etching of the interlayer insulating film 11 is performed by using, for example, RIE, and the etching condition is such that the etching rate of the BPSG film is slower than that of the spacer layer 8 (Si ₃ N ₄ film). For example, it can be realized by using a mixed gas of CHF ₃ and CO as an etching gas and a vacuum degree of about 6 mTorr. The above etching conditions can be realized under other setting conditions.

By doing so, the interlayer insulating film 11 (BP
The SG film) is etched, but the gate gap layer (Si ₃ N ₄ ) 5 on the gate electrode 4 and the spacer layer (Si ₃ N ₄ ) 8 on the side wall of the gate electrode 4 are not etched and are formed in a later process. It is possible to prevent a short circuit between the capacitor electrode portion and the gate electrode 4 that operate. That is, a new etching stopper layer becomes unnecessary, and the contact hole can be opened in a self-aligned manner without using a complicated process.

Next, a polycrystalline Si layer, for example, arsenic-doped, which becomes the plug layer 12, is deposited on the entire surface until the contact hole is completely filled. For example, for a contact hole with a diameter of 0.4 μm, deposit a film thickness of about 400 nm,
Etching back is performed using a chemical dry etching (CDE) method to fill the contact holes with a polycrystalline Si layer. A chemical mechanical polishing method may be used for this. Through such steps, the plug layer 12 made of a polycrystalline Si layer electrically connected to the low-concentration impurity diffusion layer 7'can be formed at a position above the gate electrode 4.
This is a structure that works very effectively when the capacitor electrode portion is formed in a later step.

Here, the interlayer insulating film 11 is formed of BPS.
Although the example using the G film is shown, other films such as a plasma oxide film, an ozone (O ₃ ) -TEOS film, and other insulating films that can be formed at a temperature as low as possible, and are Si ₃ N ₄ at the time of RIE. Any insulating film may be used as long as the film is etched faster than the film. Next, as shown in FIGS. 7A and 7B, the process proceeds to the step of reducing the depth of the contact hole in the peripheral circuit portion, which is one of the features of the present invention.

That is, for the insulation of the plug layer 12, an interlayer insulating film 13 is formed on the entire surface by a CVD method, for example, to have a film thickness of 1
A SiO ₂ film of about 00 nm is deposited. Next, a contact hole for making a contact between the low-concentration impurity diffusion layer 7 and the bit line layer 14 is formed by using a normal lithography process.

The opening of the contact hole is also performed in a self-aligned manner by using the difference in etching rate between the SiO ₂ film and the Si ₃ N ₄ film, as in the process of FIG. That is, the interlayer insulating films 11 and 13 (SiO ₂ film) are etched, but S
The gate cap layer 5 and the spacer layer 8 made of i ₃ N ₄ are R under an etching condition such that they are hardly etched.
Perform IE. It is desirable that the etching selection ratio of SiO ₂ and Si ₃ N ₄ be 10 or more. At this time, a contact hole to the low-concentration impurity diffusion layer 7a of the peripheral circuit is also opened at the same time.

That is, the low-concentration impurity diffusion layers 7 and 7'formed in the step of FIG. 5, the epitaxial Si layer 9 formed thereon, and the silicide layer 10 formed thereon are laminated. Contact holes are simultaneously formed in the regions. In other words, the contact holes of the low-concentration impurity diffusion layers 7 and 7'of the memory cell and the contact holes of the low-concentration impurity diffusion layer 7a of the peripheral circuit are simultaneously formed.

At this time, as can be seen from FIG. 8 (see also FIG. 2), the epitaxial Si layer 9 is formed into the field insulating film 2.
It also extends and spreads over the top, helping to widen the contact margin with the field edge. That is, it is possible to make a contact on the field insulating film 2.

After that, the bit line layer 14 is formed. The material of the bit line layer 14 is to reduce the wiring resistance as well as the resistance of the lifting contact.
It is preferable to use a metal material. For example, a tungsten (W) film formed by a CVD method is used.

In this case, the underlying interlayer insulating film 13 (SiO 2
₂ ) In order to prevent the peeling between the W film and the W film, a TiN film or a W film formed by a sputtering method is used as the lower bit line layer 14 ₁ .

That is, first, after forming the contact hole, the lower bit line layer 14 ₁ made of TiN and having a thickness of 50 nm is formed by the CVD method, and subsequently, the lower bit line layer 14 ₁ made of W and having a thickness of 100 nm is formed by the CVD method. Upper bit line layer 14 ₂
To form. Next, as the gate cap layer 15, for example, a plasma nitride film (Si ₃ N ₄ ) having a thickness of 150 nm is formed, and then a resist pattern is sequentially formed thereon by using a normal lithography technique. Then, using this resist pattern as a mask, the gate cap layer 1
5, the upper bit line layer 14 ₂ and the lower bit line layer 14 ₁ are sequentially processed by RIE.

The structure of the memory cell portion is a bit line prefabricated type in the stack type memory cell, but in the peripheral circuit portion, the contact hole of the impurity diffusion layer 7a is formed in the gate electrode 4 in a self-aligning manner. , The same filling layers 14 _1a , 1 as the bit line layers 14 ₁ , 14 ₂ in the memory cell area
It becomes lifted structure by 4 _2a.

Although not shown in FIG. 8, the contact to the gate electrode 4 is also made simultaneously with the bit line layers 14 ₁ , 14.
Lifted by the same packed bed 14 _1a, 14 _2a and _2, by all the impurity diffusion layer 7a and the gate electrode 4 of the peripheral circuit portion bit line layer 14 _1, 14 ₂ and the same packing layer 14 _1a, 14 _2a layer on once Will be lifted to the position. As a result, the depths of the contact holes at the time of forming the metal wiring after the memory cell portion and the peripheral circuit portion are made uniform, and it is possible to avoid the drawback of the memory cell having the deep contact hole such as the stack type memory cell.

As shown in FIG. 8, in order to improve the oxidation resistance / heat resistance of the surface of the metal material of the bit lines 14 ₁ and 14 ₂ such as the W film and the TiN film, for example, plasma nitriding treatment or the like is performed. It is very effective to form the surface protective film 16 by performing the above. Next, as shown in FIGS. 9A and 9B, a process of forming a capacitor electrode using the plug layer 12, which is one of the features of the present invention, will be described.

That is, the interlayer insulating film 17 of the bit line layer 14 can be formed on the entire surface by a CVD method at a low temperature of about 350 ° C., for example, an ozone-TEOS oxide film of about 500 n.
Deposit about m.

Next, the entire surface is flattened by a chemical mechanical polishing method or the like, an interlayer insulating film 17 is left on the bit line layer 14 by about 100 nm, and then a thickness of 5 is formed on the entire surface.
A Si ₃ N ₄ film 18 of about 0 nm is deposited by the CVD method.

Next, a resist pattern (not shown) for a contact hole for connection with the plug layer 12 is formed on the Si ₃ N ₄ film 18 by a normal lithography method, and then using this as a mask, Si ₃ is formed by RIE. N ₄ film 1
8. The interlayer insulating films 17 and 13 are sequentially etched to form contact holes.

At this time, as in the case of the steps of FIGS. 6 and 7, etching is performed under the etching conditions such that the etching rate of the SiO ₂ film is about 10 times faster than that of the Si ₃ N ₄ film. Thus, for example, even if a contact hole is formed in the bit line 14 due to misalignment during lithography, the gate cap layer (S
The etching stops at i ₃ N ₄ ) 15. Moreover,
Even if the etching reaches the plug layer 12, the plug layer 12
Is at a position, for example, about 400 nm above the gate electrode 4, so that it is possible to prevent short circuit with the gate electrode 4.

Then, a Si ₃ N ₄ film 19 is deposited on the entire surface, for example, about 50 nm, and the entire surface is etched by RIE, leaving the Si ₃ N ₄ film 19 only on the side walls of the contact hole, and the plug material 12 is formed. Is exposed, and the side surface of the exposed bit line 14 is insulated from the capacitor electrode formed in a later step.
Next, a polycrystalline Si film 20 doped with arsenic as a capacitor base electrode (storage electrode) is formed on the entire surface, for example, with a film thickness of 7
After depositing about 0 nm, SiO ₂ is deposited on the entire surface by the CVD method.
The film 21 is deposited, for example, to a film thickness of about 500 nm, and the SiO ₂ film 21 is etched into a capacitor electrode shape by the RIE method. At this time, etching is performed on the polycrystalline Si film 20.
Stop with.

Next, by changing the etching gas conditions, the underlying polycrystalline Si film 20 is etched into the same shape as the SiO ₂ film 21. At this time, etching is performed on the underlying Si ₃
Stop at the N ₄ film 18. Then, a polycrystalline Si film 22 as a capacitor base electrode layer is again formed on the entire surface to a film thickness of 500 n.
Deposit about m. At this time, in order to ensure a low resistance electrical connection between the polycrystalline Si film 22 and the polycrystalline Si film 20 as the capacitor base electrode layer, arsenic is angled from four directions (for example, about 30 degrees). Ion implantation is performed). Alternatively, phosphorus-doped polycrystalline Si may be used to reliably maintain the electrical connection.

Next, RIE is performed on the entire surface under the etching condition of polycrystalline Si to perform SiO ₂ film 21 and polycrystalline Si film 20.
The polycrystalline Si film 22 is left on the side surface of the. By doing so, the size of the capacitor electrode can be made larger than the size determined by lithography. That is, the area of the capacitor electrode can be increased, and the storage capacitance (Cs) can be increased. If the capacity (Cs) is the same, this polycrystalline Si film 2
The height of 2 can be lowered. This is very effective in reducing the overall step difference.

Next, the SiO ₂ film 21 is replaced with, for example, NH ₄
It is removed using an etching solution such as F liquid. At this time,
The underlying Si ₃ N ₄ film 18 can prevent the underlying interlayer insulating film 17 from being etched by the NH ₄ F liquid. Next, there are two methods of forming the capacitor insulating film, though the capacitor forming process is started. The first method is the usual so-called NO.
This is how to use a membrane.

That is, first, the natural oxide film on the surface of the polycrystalline Si layers 20 and 22 as the capacitor base electrodes is removed by silane gas (SiH ₄ ), and then Si is applied to the surfaces of the polycrystalline layers 20 and 22 in the same vacuum. _{The 3} N ₄ film is heated to a high temperature (for example, 80
For example, about 1 nm is formed by flowing ammonia gas (NH ₃ ) at 0 ° C.

Thereafter, a Si ₃ N ₄ film is deposited on the entire surface as a capacitor insulating film 23 to a film thickness of about 60 nm, and the surface is oxidized for about 60 minutes in an atmosphere of 800 ° C., HCl and 10% to obtain a so-called top. About 2 nm oxide film
Form a degree. Next, a polycrystalline film to be the plate electrode 24 is deposited on the entire surface, and this is patterned to form the plate electrode 24.

Then, as the interlayer insulating film 25, for example, a plasma-TEOS film (SiO ₂ film) is deposited on the entire surface by about 100 nm, and then an ozone-TEOS film 26 is deposited on the entire surface by about 1000 nm, for example. And
The surface is flattened by using a chemical mechanical polishing technique or the like, and a plasma-TEOS film is deposited on the entire surface of the same again as an interlayer insulating film 27 to be a base of the Al wiring 29 by about 100 nm.

The second method is to use a high dielectric film such as a tantalum oxide film (Ta ₂ O ₅ ) as a capacitor insulating film.
Membrane) is the way to do it. The same applies to other high-dielectric film, for example, strontium titanate (SrTiO ₃ ) film, but by considering the reaction of each film with the capacitor electrode, the electrode material and surface treatment are devised and used and selected. There is a need.

As an example, the case of a Ta ₂ O ₅ film will be described. First, as in the case of the NO film, the natural oxide film on the surface of the polycrystalline Si films 20 and 22 as the capacitor base electrodes is removed by, for example, the silane reduction method, and then the
A Si ₃ N ₄ film is formed on the surface to a thickness of about 1 nm.

Then, a Ta ₂ O ₅ film is formed as a capacitor insulating film 23 on the entire surface by a CVD method, and then Ta ₂ O _{5 is formed.}
In order to improve the dielectric constant of the film, N ₂ annealing at about 750 ° C. is performed.

Next, a titanium nitride film (TiN) film, a carbon film (C) or a nickel (Ni) film is formed as the plate electrode 24. Alternatively, a W film or an Al film may be simultaneously formed on the surface in order to reduce the resistance of the plate electrode 24 or prevent the plate electrode 24 from peeling off.

Next, as in the case of the previous NO film, plasma-TEOS film (SiO ₂ film) and ozone (O ₃ ) -TEO which can be formed as the interlayer insulating films 25 and 26 at low temperatures, respectively.
After depositing the S films on the entire surface of 100 nm and 1000 nm, respectively, they are uniformly planarized over the entire surface of the substrate by a chemical mechanical polishing method or the like.

The above is an example of the method of forming a capacitor when using the NO film and the high dielectric film. In the case of Sr (TiO ₃ ), Ta // is used as the electrode in order to prevent reaction with the electrode. A Pt laminated system may be used.

In the subsequent steps, as shown in FIGS. 1, 2 and 3 described above, a contact hole for the bit line 14 or the plate electrode 24 is opened, and, for example, a W film 28 is formed in this contact hole. After selective growth is performed or a W film is deposited on the entire surface, the W film 28 is buried in the contact hole by an etch back method, and a low resistance metal material is buried in the contact hole. As a result, the resistance of the contact plug can be reduced.

Finally, an Al film composed of a TiN film 29 ₁ as a barrier metal material and an Al film 29 ₂ as a main wiring.
The wiring 29 is formed to complete the memory cell and the peripheral circuit section. At this time, the wiring 29 is connected to the word line layer 4 of the memory cell section.
It may be used as a shunt material. If necessary, another layer of Al wiring may be formed.

Although the present embodiment does not show the mutual relationship between a plurality of memory cells adjacent in the word line 4 direction,
Only passage of the word line when the arrangement of the memory cells is the folded bit line system is shown on the field. Of course, the present invention can be applied to a DRAM having an open bit line structure. In addition, various modifications can be made without departing from the scope of the present invention.

[0062]

As described above, according to the present invention, the epitaxial layer having the impurity concentration higher than that of the first impurity diffusion layer and the second impurity diffusion layer is the first impurity diffusion layer.
Since it is provided on the impurity diffusion layer and the second impurity diffusion layer, the junction leak can be reduced and the short channel effect of the transistor can be suppressed.

Further, by utilizing the wiring layer as the filling layer, the deep contact hole in the peripheral circuit region provided by the stack type memory cell becomes shallower by the filling layer, and the yield due to the contact failure is increased. Can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a memory cell of a stack type DRAM according to an embodiment of the present invention.

FIG. 2 is a memory cell B- of the stacked DRAM of FIG.
B'sectional view.

FIG. 3 is a diagram showing a schematic configuration of a peripheral circuit of the stacked DRAM of FIG.

FIG. 4 is a sectional view of a manufacturing process of a memory cell of a stack type DRAM according to an embodiment of the present invention.

FIG. 5 is a sectional view of a manufacturing process of a memory cell of a stack type DRAM according to an embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process of a memory cell of a stack type DRAM according to an embodiment of the present invention.

FIG. 7 is a sectional view of a manufacturing process of a peripheral circuit portion of a stack type DRAM according to an embodiment of the present invention.

FIG. 8 is a sectional view of a manufacturing process of a memory cell of a stack type DRAM according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of a manufacturing process of a memory cell of a stack type DRAM according to an embodiment of the present invention.

FIG. 10 is an element cross-sectional view of a memory cell of a conventional stack type DRAM.

[Explanation of symbols]

1, 101 ... Si substrate, 2, 102 ... Field insulating film, 3, 103 ... Gate insulating film, 4, 104 ... Gate electrode, 5 ... Gate camp layer, 8 ... Spacer layer, 7, 1
05 ... Impurity diffusion layer, 9 ... Epitaxial Si layer, 10
... silicide layer, 12 ... plug layer, 14, 112 ... bit line layer, 14 ₁ , 14 ₂ ... filling layer, 11, 13, 17,
25, 26, 27, 106, 111, 114 ... Interlayer insulating film, 20, 22, 107 ... Polycrystalline Si film, 23, 109
... Capacitor insulating film, 24, 110 ... Plate electrode, A
l wiring ... 29.

Front page continued (72) Inventor Toru Ozaki 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Institute (72) Inventor Takashi Yamada 1 Komu-shi Toshiba-cho, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute

Claims (2)

[Claims] 1. A first MOS transistor formed in a memory cell region of a semiconductor substrate, a second MOS transistor formed in a peripheral circuit region of a semiconductor substrate, and a first impurity of the first MOS transistor. An epitaxial layer provided on the diffusion layer and the second impurity diffusion layer and having an impurity concentration higher than the impurity concentrations of the first impurity diffusion layer and the second impurity diffusion layer, and provided on the semiconductor substrate, An interlayer insulating film layer having a contact hole on the epitaxial layer and the impurity diffusion layer of the second MOS transistor; and an interlayer insulating film filling the contact hole on the epitaxial layer of the first impurity diffusion layer. The formed wiring layer, and the wiring layer formed in the same step as the wiring layer and on the impurity diffusion layer of the second MOS transistor. The semiconductor memory device comprising the filling layer made of the same material as the wiring layer filling the contact hole, that is formed by and a second capacitor which is electrically connected to the impurity diffusion layer. 2. The semiconductor memory device according to claim 1, wherein an insulating film is provided on a side portion and an upper portion of the gate electrode of the first MOS transistor.