JPH0637091A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a wiring structure which has high reliability and excellent electric characteristics. CONSTITUTION:A first silicon film 10a is formed on a metal silicide layer (e.g. a TiSi2 layer) by a physical vapor depositing method, and then a second silicon film 10 having different physical and chemical characteristics from those of the film 10a is formed on the film 10a by using a CVD method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a wiring structure of low contact resistance and high reliability and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, demands for high integration and miniaturization of semiconductor devices have been increasing. In response to such demands for high integration and miniaturization, measures such as reduction of wiring layer and electrode dimensions and multilayer wiring structure have been adopted. Thus, as the dimensions of the wiring layer, the electrodes, etc. are reduced, the electrical resistance of these increases. Therefore, it is required to reduce the resistance of the electrodes and wiring layers.

Generally, diffusion resistance of an impurity region, contact resistance, wiring resistance, etc. can be mentioned as main constituents of electrical resistance in a semiconductor device. The resistance value of the diffused resistor can be lowered by increasing the concentration of the impurity region. The contact resistance is determined by the state of the interface between the semiconductor substrate and the wiring layer, and its effective resistance can be reduced by increasing the effective contact area. Regarding wiring resistance, the dimensions of the wiring layer etc.
The use of lower resistance materials is being considered.

As described above, various measures have been taken in order to reduce the electric resistance of the semiconductor device. Among them, it has been conventionally practiced to use metal silicide as a part of the wiring layer in order to reduce the wiring resistance. As the metal silicide, a refractory metal silicide is often used. By using the refractory metal silicide, it is possible to realize low resistance, high heat resistance, etc. Various characteristics such as good matching of the thermal expansion coefficient are ensured.

That is, a wiring layer having low resistance and high reliability can be obtained. Among such metal silicides, titanium silicide (TiSi ₂ ) is known to have the lowest resistance. Therefore, it is often used as a part of the electrode or provided in the contact portion between the wiring layer and the impurity region. This makes it possible to reduce the contact resistance and the wiring resistance. That is, salicide (Self Aligned Sili
By forming a transistor having a (cide) structure,
It is possible to obtain a high-performance semiconductor device.

An example of a semiconductor device having the above-mentioned salicide transistor will be described below with reference to FIGS.
4 will be described. FIG. 17 is a cross-sectional view showing a partial cross section of a semiconductor device having a salicide structure transistor.

Referring to FIG. 17, n-type impurity regions 75 serving as source / drain regions are formed in a prescribed region of the main surface of p-type semiconductor substrate 71 at intervals. The impurity region 75 defines the channel region of the transistor. Then, a gate electrode 73 is formed on the channel region via a gate insulating film 72.
Are formed.

This gate electrode 73 and impurity region 75
A titanium silicide layer 77 for reducing the electrical resistance of the gate electrode 73 and the impurity region 25 is formed in the. A sidewall 74 is formed on the sidewall of the gate electrode 73. This sidewall 74
An interlayer insulating film 78 is formed on the gate electrode 73 and the impurity region 75. A contact hole 79 is provided in a predetermined region of the interlayer insulating film 78, which serves as a contact portion between the impurity region 75 and the wiring layer provided thereabove.

Then, in the contact hole 79,
A polycrystalline silicon layer 80 having impurities introduced therein is formed, and an interlayer insulating film 81 is formed on the polycrystalline silicon layer 80.
Are formed. A contact hole 82 is provided in the interlayer insulating film 81, and a wiring layer 83 made of a metal containing aluminum is formed in the contact hole 82.

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIGS.
18 to 24 are cross-sectional views showing the first to seventh steps in the manufacturing process of the semiconductor device having the salicide structure transistor as described above.

Referring to FIG. 18, first, a gate insulating film 72 having a thickness of about 150 Å is formed on the main surface of a p-type semiconductor substrate 71 made of silicon single crystal or the like by thermal oxidation. Then, CVD (Chemical Vapor Depos) is formed on the gate insulating film 72.
Ionization method is used to form a polycrystalline silicon film having a thickness of about 1500 to 5000 Å.

The polycrystalline silicon film and the gate insulating film 72 are patterned to form a gate electrode 73. Then, a sidewall 74 made of a silicon oxide film is formed on the sidewall of the gate electrode 73. The side wall 74 is formed by forming a silicon oxide film so as to cover the gate electrode 73 and anisotropically etching the silicon oxide film.

After that, on the main surface of the p-type semiconductor substrate 71,
Impurity regions 75 to be source / drain regions are formed by introducing n-type impurities such as phosphorus (P) and arsenic (As). At this time, the diffusion depth of the impurity region 75 is about 1000 to 3000Å, and the impurity concentration is about 10 ²⁰ atoms / cm ³ or more.

Next, referring to FIG. 19, impurity region 75
A Ti film 76 having a thickness of about 500 Å is formed on the top and the gate electrode 73 by a sputtering method or the like. After that, the p-type semiconductor substrate 71 on which the Ti film 76 is formed
In a nitrogen atmosphere at a temperature of 600 to 700 ° C
A (Rapid Thermal Annealin
g) Perform processing. In this case, the RTA process may be performed in a vacuum or an argon atmosphere instead of the nitrogen atmosphere.

As a result, as shown in FIG.
The lower part of the i film 76 is the gate electrode 73 and the impurity region 75.
By reacting with silicon in the mono-silicide (TiSi) layer or disilicide (TiSi
₂ ) A composite layer 77a composed of layers is formed. An unreacted Ti layer 76 remains on the composite layer 77a,
A TiN layer 77b is formed on the layer 76. At this time,
The Ti film 76 in contact with the sidewall 74 is formed of unreacted T film.
The i layer 76 is left as it is or the TiN layer 77b is formed.

Next, referring to FIG. 21, a p-type semiconductor substrate
71 is an etching solution, for example, H₂SO_Four/ H₂O₂/
H₂O mixture or NH_FourOH / H₂O₂/ H₂O mixture
By treating with the liquid, the TiN layer 77b and the unreacted
The corresponding Ti layer 76 is removed. Thereby, the gate electrode 7
3 and the impurity region 75. ₂
Alternatively, only TiSi) 77a remains.

Next, the p-type semiconductor substrate 71 in the above-described state is subjected to R at a temperature of 800 ° C. or higher in a nitrogen atmosphere.
TA processing is performed. In this case, the nitrogen atmosphere may be changed to a vacuum or an argon atmosphere. As a result, as shown in FIG. 22, the titanium silicide (TiSi ₂ ) layer 77, which is a complete disilicide, is formed on the gate electrode 73 and the impurity region 75 at 300-10.
It is formed at a depth of about 00Å.

Next, referring to FIG. 23, 2000 to 500 are formed on the entire surface of p-type semiconductor substrate 71 by the CVD method or the like.
An interlayer insulating film 78 having a film thickness of about 0Å is formed. And
The p-type semiconductor substrate 71 in this state is heat-treated at a temperature of 800 to 1000 ° C. By this heat treatment, the film quality is improved and PSG (Phospho Sil)
icate glass) film, BPSG (Boro P
A good flatness is obtained by reflowing a phosporo Silicate Glass) film or the like. After that, the opening size of 0.8 to 0.5 is formed in the interlayer insulating film 78 on the impurity region 75.
A contact hole 79 of 1.2 μm is formed.

After that, as shown in FIG. 24, a polycrystalline silicon layer 80 into which impurities such as phosphorus (P), arsenic (As), and boron (B) have been introduced is formed by the CVD method. Then, this polycrystalline silicon layer 80 is patterned into a desired shape. Then, using the CVD method or the like, 50
Interlayer insulating film 81 having a film thickness of about 00 to 10000Å
To form. Then, heat treatment is performed at a temperature of 800 to 1000 ° C. to improve the film quality, and the PSG film and B
A PSG film or the like is reflowed to obtain good flatness.

Then, referring to FIG. 17, an opening dimension of 1.2 is formed in interlayer insulating film 81 on polycrystalline silicon layer 80.
A contact hole 82 of about 1.5 μm is formed. The contact hole 82 is made of a metal containing aluminum by 5000 to 10 by using a sputtering method or the like.
The wiring layer 83 having a film thickness of about 000Å is formed. Through the above steps, a semiconductor device having a salicide transistor is formed. As a result, the wiring resistance of the polycrystalline silicon gate and the bias resistance of the impurity region can be reduced at the same time, and a semiconductor device with higher performance can be formed.

[0021]

However, the semiconductor device having the above structure also has the following problems.

In the conventional manufacturing method described above, titanium silicide (T) is formed before the polycrystalline silicon layer 80 is formed.
The oxide film formed on the surface of the iSi ₂ ) layer 77 had to be removed. This is because titanium silicide is a very active metal and an oxide film is easily formed on the surface thereof. As a method for removing the oxide film, for example, HF vapor treatment or H ₂ baking treatment has been used. Then, after such a process was previously performed in the CVD apparatus, the polycrystalline silicon layer 80 was formed on the titanium silicide layer 77.

However, since titanium silicide is a very active metal as described above, the polycrystalline silicon layer 8 is formed on the titanium silicide layer 77 by the CVD method.
When 0 is formed, the phenomenon that the polycrystalline silicon layer 80 locally abnormally grows occurs. Here, FIG.
The abnormal growth of the polycrystalline silicon layer 80 will be described more specifically with reference to FIG. FIG. 25 is an explanatory diagram schematically showing how the polycrystalline silicon layer 80 is locally abnormally grown when the polycrystalline silicon layer 80 is formed on the titanium silicide layer 77 by the CVD method. Is. With reference to FIG. 25, it can be seen that the polycrystalline silicon layer 80 has a locally abnormally grown shape and has a shape with a very large unevenness on the titanium silicide layer 77.

As described above, since the unevenness in level is very large, it is usually not possible to form a wiring layer on it, but if it is attempted to form a wiring layer on this polycrystalline silicon layer 80, The upper surface of the polycrystalline silicon layer 80 must be flattened. It is very difficult to flatten such an uneven surface having a very large step. For example, when the flattening is performed by etching back or the like, the film surface formed for the flattening is formed. In addition, it is very likely that the tip of the abnormally grown protrusion of the polycrystalline silicon layer 80 remains. In that case, the wiring layer formed on the flattening film and the polycrystalline silicon layer 80 are electrically short-circuited. That is, it can be said that it is extremely difficult to form a multilayer wiring structure.

Further, as described above, the polycrystalline silicon layer 80
In some cases, the silicon in the p-type semiconductor substrate 71 may break through the titanium silicide layer 77 and grow. This state is shown in FIG. FIG. 26 shows that when the polycrystalline silicon layer 80 is formed by the CVD method, p
The silicon in the semiconductor substrate 71 is titanium silicide layer 7
FIG. 7 is a cross-sectional view schematically showing a state of abnormal growth by breaking through 7. As shown in FIG. 26, the silicon in the p-type semiconductor substrate 71 breaks through the titanium silicide layer 77 and abnormally grows, so that the titanium silicide layer 77.
However, there is a problem that the reliability of the contact portion is deteriorated due to the defect.

Further, a polycrystalline silicon layer 8 is used as a wiring layer.
Since 0 is used, impurities are introduced into the polycrystalline silicon layer 80. This impurity is easily absorbed by the titanium silicide layer 77. Therefore, when the polycrystalline silicon layer 80 is formed directly on the titanium silicide layer 77, impurities are absorbed from the polycrystalline silicon layer 80, and the wiring resistance of the polycrystalline silicon layer 80 increases with time. Was being considered.

On the other hand, it may be considered that the polycrystalline silicon layer 80 is formed only by the sputtering method. However, in the case where the polycrystalline silicon layer 80 is formed only by the sputtering method in this way, the following problems can be considered. Regarding this problem,
This will be described with reference to FIGS. 27 and 28. 27 and 28 are partial cross-sectional views showing stepwise a state in which the polycrystalline silicon layer 84 is formed on the interlayer insulating film 78 including the inner surface of the contact hole 79 only by the sputtering method.

Referring to FIG. 27, since the step coverage is not good in the sputtering method, the film thickness W1 of the polycrystalline silicon layer 84 formed on the interlayer insulating film 78 and the multi-layer formed on the side wall of the contact hole 79. There is a difference in film thickness from the film thickness W2 of the crystalline silicon layer 84. The film thickness W1 of the polycrystalline silicon layer 84 formed on the interlayer insulating film 78 is larger than the film thickness W2 of the polycrystalline silicon layer 84 formed on the side wall of the contact hole 79.

Therefore, as shown in FIG. 28, when the polycrystalline silicon layer 84 is formed to have a desired film thickness, voids (Voi) are formed inside the polycrystalline silicon layer 84.
d) The possibility that 85 will be formed increases. as a result,
This causes a problem that reliability of the contact portion of the semiconductor device is lowered.

Further, when the polycrystalline silicon layer 84 is formed by the sputtering method, a problem arises when impurities are introduced to make the polycrystalline silicon layer 84 conductive. That is, when the polycrystalline silicon layer 84 is formed only by the sputtering method, impurities will be introduced by ion implantation. Therefore, there is a possibility that impurities may be introduced into the polycrystalline silicon layer 84 unevenly.

The present invention has been made in view of the above, and an object of the present invention is to increase the wiring resistance over time when forming a polycrystalline silicon wiring layer on a metal silicide layer. It is an object of the present invention to provide a semiconductor device having a wiring layer structure capable of blocking and a manufacturing method thereof.

Another object of the present invention is to provide a more reliable and multilayer wiring structure by preventing abnormal growth of the polycrystalline silicon layer when forming the polycrystalline silicon wiring layer on the metal silicide layer. Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can be applied to.

[0033]

A semiconductor device according to the present invention comprises a metal silicide layer, a first silicon layer formed on the metal silicide layer and having first physical and chemical characteristics, and a first silicon layer. The first physical layer formed on the layer
A second silicon layer having a second physical / chemical property different from the chemical property. Then, a crystal discontinuity exists at the boundary between the first silicon layer and the second silicon layer.

According to the method of manufacturing a semiconductor device of the present invention, first, a metal silicide layer is formed. A first silicon layer is formed on the metal silicide layer using a physical vapor deposition method. Then, a second silicon layer is formed on the first silicon layer by using a chemical vapor deposition method.

[0035]

In the semiconductor device according to the present invention, the first
A discontinuous interface exists at the boundary between the silicon layer and the second silicon layer. Therefore, when impurities are introduced to reduce the resistance value of the second silicon layer, the amount of the impurities absorbed by the metal silicide layer can be significantly reduced. This makes it possible to effectively prevent the resistance of the second silicon layer functioning as a wiring layer from increasing with time.

According to the method of manufacturing the semiconductor device of the present invention, the first silicon layer is first formed on the metal silicide layer by the physical vapor deposition method. In this case, since the silicon layer is formed on the metal silicide layer using the physical vapor deposition method,
It can be said that the phenomenon of abnormal growth of silicon as described above cannot occur. Then, a second silicon layer is formed on the thus formed first silicon layer by a chemical vapor deposition method. At this time, a first layer is formed on the active metal silicide layer.
Since the silicon layer is formed, the silicon layer does not grow abnormally even if the second silicon layer is formed thereon by using the chemical vapor deposition method. That is, when the silicon layer is formed on the metal silicide layer, the silicon layer can be formed without abnormal growth. This makes it possible to form a semiconductor device having a wiring layer structure that is more reliable and can be applied to a multilayer wiring structure.

[0037]

Embodiments of the present invention will be described below with reference to FIGS. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, impurity regions 5 serving as source / drain regions are formed at intervals on the main surface of p-type semiconductor substrate 1 so as to define a channel region. And
A gate electrode 3 is formed on the channel region via a gate insulating film 2. A sidewall 4 is formed on the sidewall of the gate electrode 3. Gate electrode 3
A titanium silicide (TiSI ₂ ) layer 7 is formed on the upper part of and the impurity region 5. Thereby,
The resistance values of gate electrode 3 and impurity region 5 are reduced.

On the impurity region 5 and the gate electrode 3,
An interlayer insulating film 8 is formed, and a contact hole 9 is formed in a region of the interlayer insulating film 8 located on the impurity region 5. A first silicon film 10a having a predetermined film thickness is formed in the contact hole 9, and a second silicon film 10a having a physical and chemical characteristic different from that of the first silicon film 10a is formed on the first silicon film 10a. A silicon film 10 is formed. Therefore, a discontinuous crystal interface exists at the boundary between the first silicon film 10a and the second silicon film 10.

Here, the difference between the physical and chemical characteristics of the first silicon film 10a and the second silicon film 10 will be described more specifically. First, examples of physical characteristics include particle diameter, resistivity, surface roughness, and coverage. Examples of chemical characteristics include the amount of impurities contained in the first silicon film 10a or the second silicon film 10.

Each of these characteristics is characterized by the first silicon film 10a.
Alternatively, it can be arbitrarily set depending on the formation conditions of the second silicon film 10. However, regarding the coverage of the step, the PVD method and the CVD method are obviously different. The first silicon film 10a is formed using a PVD method such as a sputtering method, and the second silicon film 10 is formed using a CVD method. for that reason,
It is considered that the above-mentioned characteristics of the first silicon film 10a and the second silicon film 10 are difficult to be exactly the same. Therefore, the first silicon film 10a and the second silicon film 10
, Their physical properties or chemical properties are substantially different, and their boundaries have a discontinuous crystal interface. Also, both physical and chemical properties may differ. Also in this case, the first silicon film 10a and the second silicon film 10
At the boundary between and, there is a discontinuous interface of crystals.

Arsenic (As), phosphorus (P), boron (B) are added to the first and second silicon films 10a and 10 in order to reduce the resistance value of the first and second silicon films 10a and 10. Impurities such as are introduced. The impurities introduced into the first silicon film 10a are absorbed to some extent by the titanium silicide layer 7 located under the first silicon film 10a, but the impurities introduced into the second silicon film 10a are absorbed into the first silicon film 10a. The titanium silicide layer 7 is formed by the discontinuous interface at the boundary between the second silicon film 10 and the second silicon film 10.
Is effectively prevented from being absorbed. Thereby,
It is possible to prevent the resistance value of the second silicon film 10 from increasing with time. That is, a more reliable wiring layer can be obtained.

An interlayer insulating film 11 is formed on the second silicon film 10. A contact hole 12 is provided in a region of the interlayer insulating film 11 located on the second silicon film 10. This contact hole 1
In 2, the wiring layer 13 containing Al or the like is formed.

Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS. Figure 2
12 to 14 are cross-sectional views showing first to eleventh steps in the method of manufacturing a semiconductor device according to the present invention. Unless otherwise stated, the same method as the conventional example is used.

Referring to FIG. 2, 1500 to 5000 Å is provided on the main surface of p type semiconductor substrate 1 with gate insulating film 2 interposed therebetween.
The gate electrode 3 having a film thickness of about 3 is formed. The material of the gate electrode 3 is preferably polycrystalline silicon.
Then, a sidewall 4 is formed on the side surface of the gate electrode 3, and then an n-type impurity is introduced into the main surface of the p-type semiconductor substrate 1 to form an impurity region 5 serving as a source / drain region. Then, as shown in FIG.
A Ti film 6 is formed on the entire surface of the p-type semiconductor substrate 1 by using a sputtering method or the like.

Next, referring to FIG.
RTA on the p-type semiconductor substrate 1 at a temperature of about 00 to 700 ° C.
By performing the treatment, a composite layer 7a made of monosilicide (TiSi) or disilicide (TiSi ₂ ) is formed on the upper portion of the gate electrode 3 and the upper portion of the impurity region 5.
Is formed. At this time, the unreacted Ti layer 6 remains on the composite layer 7a. A TiN layer 7b is formed on the unreacted Ti layer 6.

Next, referring to FIG. 5, the p-type semiconductor substrate 1 in the above-described state is subjected to the same etching treatment as in the prior art to remove the TiN layer 7b and the Ti layer 6. Then, referring to FIG. 6, this p-type semiconductor substrate 1
RTA at a temperature of 800 ° C or higher in a nitrogen atmosphere
By performing the processing, the composite layer 7a is converted into a complete disilicide layer (TiSi ₂ layer) 7. At this time, the formation depth of the TiSi ₂ layer is 300 to 100.
It is about 0Å.

Thereafter, as shown in FIG. 7, the interlayer insulating film 8 is formed on the entire surface of the p-type semiconductor substrate 1 by the CVD method or the like.
To form. At this time, the natural oxide film 15 is formed on the upper surface of the titanium silicide layer 7. The film thickness of the interlayer insulating film 8 is preferably about 2000 to 5000Å.
The interlayer insulating film 8 is, for example, a PSG film or a BP.
It is formed of a laminated film of an SG film and a non-doped oxide film.

The interlayer insulating film 8 has a thickness of 800 to 10
By heat treatment at a temperature of 00 ° C., reflow is performed and flattening is performed. Then, in the interlayer insulating film 8 located on the titanium silicide layer 7, the opening dimension is 0.8 to
A contact hole 9 of about 1.2 μm is formed. Thereby, a part of the titanium silicide layer 7 is exposed.

After forming the above contact hole 9,
The resist pattern (not shown) used to form the contact hole 9 is removed. Oxygen plasma is used to remove the resist pattern. At that time, as shown in FIG. 8, the exposed titanium silicide layer 7 is again exposed.
A native oxide film 15 is formed on the surface.

Next, the step of forming the first silicon film 10a in the contact hole 9 after removing the above-mentioned natural oxide film 15 formed on the bottom surface of the contact hole 9 is carried out. A semiconductor manufacturing apparatus which is considered to be suitable for performing the subsequent steps will be described with reference to FIG. FIG. 16 is a diagram showing a schematic configuration of a manufacturing apparatus considered to be suitable for manufacturing the above semiconductor device.

Referring to FIG. 16, this semiconductor manufacturing apparatus 6
0 is a pre-etch chamber 61 for removing an oxide film formed on the surface of the semiconductor substrate, and a PVD (Physical Vap) for forming a film on the surface of the semiconductor substrate by physical vapor deposition such as sputtering.
or Deposition chamber 63 and C for forming a film on the surface of a semiconductor substrate by a chemical vapor deposition method such as a CVD method.
The VD chamber 64, the load lock chamber 65 for isolating the semiconductor substrate from the outside air, and the transfer system 6 for transferring the semiconductor substrate to each processing chamber in a vacuum or an inert gas.
2 and. Thereby, it is possible to prevent an unnecessary oxide film from being formed on the surface of the semiconductor substrate after the respective treatments.

After forming the contact hole 9 as described above, a natural oxide film is easily formed on the surface of the active titanium silicide layer 7 as shown in FIG. In order to remove this oxide film, the p-type semiconductor substrate 1 housed in the load lock chamber 65 is carried into the pre-etch chamber 61. Then, referring to FIG. 9, natural oxide film 15 is removed by performing HF vapor treatment or H ₂ baking treatment in pre-etch chamber 61. For convenience of description, FIGS. 10 to 10 used in the following description.
The natural oxide film 15 is not shown in FIG.

Thereafter, the p-type semiconductor substrate 1 is carried into the PVD chamber 63 through the carrier system 62 which is held in a vacuum or an inert gas atmosphere. At this time, no oxide film is formed on the surface of the titanium silicide layer 7 during transportation. Thereafter, referring to FIG. 10, in PVD chamber 63, first silicon film 10a having a film thickness of about 100 to 500 Å is formed on titanium silicide layer 7 by using, for example, a sputtering method.

The average particle size of the silicon particles in the first silicon film 10a is relatively larger than the average particle size of the silicon particles in the second silicon film 10 by appropriately adjusting the film forming conditions. Can be Since the silicon film formed by the sputtering method is inferior to the silicon film formed by the CVD method in terms of coverage and film formation rate, the silicon film having a relatively thin film thickness as described above is formed. . It can therefore be said that productivity will not be significantly reduced.

After the first silicon film 10a is formed in this way, the p-type semiconductor substrate 1 is loaded into the CVD chamber 64 through the transport system 62 held in the above atmosphere again. Then, referring to FIG. 11, in the CVD chamber 64, the second silicon film 10 having a film thickness of about 1500 to 2000 Å is formed on the first silicon film 10a by the CVD method.

At this time, after the first silicon film 10a is formed, the p-type semiconductor substrate 1 is carried into the CVD chamber 64 through the above-mentioned transfer system 62, so that the first silicon film 10a is formed.
An oxide film is not formed on the wiring layer, and a good wiring layer can be obtained. As described above, the average particle size of the silicon particles in the second silicon film 10 formed by the CVD method can be adjusted by appropriately adjusting the film forming conditions. It can be relatively smaller than the average particle size.

In this case, the first silicon film 10a is formed by the PVD method such as the sputtering method, and the second silicon film is formed on the first silicon film 10a by the CVD method. The phenomenon of abnormal growth does not occur. Therefore, it is possible to form a more reliable wiring layer.

In the above embodiments, the difference in the particle size of silicon particles was mentioned as an example of the physical and chemical characteristics of the first silicon film 10a and the second silicon film 10. Then, the first silicon film 10a and the second silicon film 10 were respectively formed under the condition that the particle diameters of the silicon particles were different.

However, the present invention is not limited to this, and the first silicon film 1 is provided under the condition that other physical and chemical characteristics are different.
0a and the second silicon film 10 may be formed. Also in this case, since the first silicon film 10a is formed using the PVD method, the phenomenon of abnormal growth of the silicon film unlike the conventional case does not occur.

After the second silicon film 10 is formed as described above, the second silicon film 10 and the first silicon film 10a are patterned. After that, arsenic (As),
After implanting impurities such as phosphorus (P) and boron (B) into the first and second silicon films 10a and 10, a heat treatment for activation is performed. As a result, the titanium silicide layer 7
A wiring layer (10, 10a) connected to is formed.

Here, the effect of having such a wiring structure will be described in more detail with reference to FIG. FIG. 13 is a partially enlarged cross-sectional view of the contact portion between the titanium silicide layer 7 and the first and second silicon films 10 and 10a which are wiring layers in FIG.

As described above with reference to FIG. 13, the first
Impurities for reducing the resistance value are introduced into the second silicon film 10a and the second silicon film 10a. However, since the first silicon film 10a is in direct contact with the titanium silicide layer 7, the titanium silicide layer 7 is formed. As a result, impurities are absorbed from the first silicon film 10a.
However, since the film thickness of the first silicon film 10a is smaller than the film thickness of the second silicon film 10, the resistance value does not increase so much.

On the other hand, with respect to the second silicon film 10, the titanium silicide layer 7 is formed via the first silicon film 10a.
Therefore, the amount of impurities absorbed by the titanium silicide layer 7 can be extremely small.
At the interface between the first silicon film 10a and the second silicon film 10, there is a discontinuous surface due to the difference in the physical and chemical characteristics such as the difference in the average particle size of the particles in each film,
This is because impurities in the silicon film 10 are less likely to be absorbed by the titanium silicide layer 7 due to the existence of this interface.

Incidentally, in FIG. 13, the arrow indicates that the titanium silicide layer 7 is formed by the impurities in the second silicon film 10 due to the interface between the first silicon film 10a and the second silicon film 10.
It is schematically shown that the absorption is blocked by. As a result, it is possible to effectively prevent the resistance of the wiring layer from increasing with time due to the impurities being absorbed from the silicon film.

Regarding the conditions for forming the second silicon film 10, for example, silane (SiH ₄ ) gas is used.
When the film is formed at a temperature of 0 ° C. or higher, the second silicon film 10
As a result, polycrystalline silicon is mainly formed. Also, 57
When the film is formed at a temperature in the range of 0 ° C. to 580 ° C., polycrystalline silicon and amorphous silicon coexist and 570
Amorphous silicon is mainly formed below the temperature of ° C. However, even when amorphous silicon is formed, it becomes polycrystalline silicon by a heat treatment in a later step.

After forming the second silicon film 10 as described above, referring to FIG. 12, an interlayer having a film thickness of about 5000 to 10000Å is formed on the entire surface of p-type semiconductor substrate 1 by the CVD method or the like. The insulating film 11 is formed. Then 80
By performing heat treatment at a temperature of 0 to 1000 ° C., the film quality is improved, and the PSG film, BPSG film, etc. are reflowed to obtain good flatness.

After that, a contact hole 12 having an opening size of 1.2 to 1.5 μm is formed in the interlayer insulating film 11 located on the second silicon film 10. Then, the contact hole 12 is made of metal 500 including aluminum.
The wiring layer 13 having a film thickness of about 0 to 10000Å is formed. In this way, a semiconductor device having a salicide structure transistor is formed.

Next, referring to FIG. 14, DR of the present invention will be described.
AM (Dynamic Random Access)
The case of application to Memory) will be described. Figure 1
2 is a sectional view showing a sectional structure of a memory cell portion of a DRAM having a wiring layer structure according to the present invention.

Referring to FIG. 14, element isolation oxide film 34 is formed in the element isolation region on the main surface of p-type semiconductor substrate 21.
Are formed, and the impurity regions 25 to be the source / drain regions are formed in the element formation region at intervals. The impurity region 25 defines the channel region of the transistor, and the gate electrode 23 is formed on the channel region via the gate insulating film 22.

A titanium silicide (TiSi ₂ ) layer 27 is formed on the impurity region 25 and the gate electrode 23. An interlayer insulating film 28 is formed on the p-type semiconductor substrate 21, and a portion of the interlayer insulating film 28 located on the titanium silicide layer 27 is
Contact holes 35 and 36 are provided.

Then, the first silicon film 30a is formed in the contact hole 36 by the sputtering method or the like, and the second silicon film 30 is formed by the CVD method on the first silicon film 30a. ing. The first and second silicon films 30 and 30a form the lower electrode of the capacitor. A dielectric film 31 is formed on the second silicon film 30, and a conductive layer 32 functioning as an upper electrode of the capacitor is formed on the dielectric film 31. On the other hand, in the contact hole 35, a metal wiring layer 33 formed on the interlayer insulating film 28 and functioning as a bit line is formed.

In the above DRAM, the wiring layer structure according to the present invention is used for the lower electrode of the capacitor electrode. As described above, by applying the present invention to the lower electrode of the capacitor electrode, it becomes possible to form a connection structure between the lower electrode and the impurity region, which has lower resistance and higher reliability.

Next, the present invention will be described with reference to SRAM (Static).
A case where it is applied to the Random Access Memory) will be described with reference to FIG. Figure 15 shows
FIG. 3 is a sectional view schematically showing a sectional structure of an SRAM having a wiring layer structure based on the present invention.

Referring to FIG. 15, an element isolation oxide film 45 is formed in the element isolation region on the p-type semiconductor substrate 41, and a channel region is defined in the element formation region other than this element isolation region. Thus, the impurity regions 42 are formed at intervals. Then, this impurity region 4
2 is a titanium silicide (TiSi ₂ ) layer 43
Are formed.

Gate electrodes 44 and 44a are formed on the channel region with a gate insulating film 40 interposed therebetween. The gate electrodes 44 and 44a are made of, for example, polycrystalline silicon, and the titanium silicide layer 43 is formed on the upper portions thereof. In this case, the gate electrode 4
4 constitutes an access transistor together with other elements, and the gate electrode 44a constitutes a driver transistor.

A contact hole 57 is formed in the interlayer insulating film 48 located on the predetermined titanium silicide layer 43, and a first silicon film 50a is formed in the contact hole 57 by using a sputtering method or the like. Has been done. The second silicon film 50 is formed on the first silicon film 50a by the CVD method. That is, in this portion, the present invention is applied to the SRAM.

As a result, a highly reliable wiring layer structure of the contact portion can be obtained. A gate electrode 44a extending in a direction substantially orthogonal to the gate electrode 44 in FIG. 15 is connected to the first and second silicon films 50a, 50 in the contact hole 57.

[0078] On the second silicon layer 50 is titanium silicide (TiSi _x) layer 49 is formed. It is connected to the titanium silicide layer 49 and is located on the titanium silicide layer 49 and the gate electrode 44a,
A polycrystalline silicon film 51 is formed. The polysilicon film 51 is formed on the gate electrode 44a by the interlayer insulating film 48a.
Is formed through.

A polycrystalline silicon film 52 is further formed on the polycrystalline silicon film 51. Then, by introducing an impurity into a predetermined region of the polycrystalline silicon film 51, a region serving as a source / drain region is formed in the polycrystalline silicon film 51. As a result, a so-called TFT (Thin FilmT) is provided at a position surrounded by a dotted line in the figure.
A transmitter 47 will be formed. This TFT functions as a load transistor.

A first aluminum wiring layer 54 functioning as a bit line is formed on the polycrystalline silicon film 52 with an interlayer insulating film 48 interposed therebetween. This first aluminum wiring layer 54 is connected to a prescribed impurity region 42 formed on the main surface of p type semiconductor substrate 41. The titanium silicide layer 43 formed on the predetermined impurity region 42
The contact hole 5 is formed in the upper interlayer insulating film 48.
8 is formed. And this contact hole 5
8, the first silicon film 50a is formed by the sputtering method or the like as in the above case.
The second silicon film 50 is formed on the silicon film 50a by the CVD method. The present invention is also applied to this portion.

[0081] Then, this on the second silicon film 50 is formed of titanium silicide (TiSi _x) layer 49, on the titanium silicide layer 49, a tungsten layer 46 is formed. That is, the first aluminum wiring layer 54 is connected to the titanium silicide layer 43 in the impurity region 42 through the tungsten layer 46, the titanium silicide layer 49, the first silicon film 50a and the second silicon film 50. Become. A second aluminum wiring layer 56 functioning as a word line is formed on the first aluminum wiring layer 54 with an interlayer insulating film 55 interposed therebetween.

As described above, by applying the present invention to the SRAM, it becomes possible to form the SRAM having the wiring layer structure with higher reliability.

In the above embodiment, the metal
As an example of the side layer, a titanium silicide layer (TiSi
₂) Is formed, but other silisa
Id, for example, tungsten silicide (WS
i₂), Tantalum silicide (TaSi₂),cobalt
Silicide (CoSi₂), Nickel silicide (Ni
Si ₂), Platinum silicide (PtSi₂) Etc.
You may stay. In addition, the first silicon films 10a and 30
Although a and 50a were formed by the sputtering method,
It may be formed using another PVD method.

[0084]

As described above, according to the present invention, when a silicon wiring layer is formed on a metal silicide layer,
A physical vapor deposition method is used to form a relatively thin first silicon film, and then a chemical vapor deposition method is used to form a relatively thick second silicon film. Therefore, when a phenomenon such as abnormal growth of the silicon layer does not occur and impurities are introduced into the second silicon layer,
The phenomenon that impurities are absorbed from the second silicon layer can be effectively prevented by the lower metal silicide layer. This makes it possible to form a wiring layer structure that is highly reliable over time. Furthermore, since the thickness of the first silicon film is set thin by the physical vapor deposition method, the productivity is not significantly reduced. That is, according to the present invention, it is possible to manufacture a semiconductor device having a wiring structure with higher reliability and less variation in resistance value over time without lowering productivity.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a first step of a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 3 is a cross sectional view showing a second step of the manufacturing process of the semiconductor device in one embodiment based on the present invention.

FIG. 4 is a cross-sectional view showing a third step of manufacturing the semiconductor device in the embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth step of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross sectional view showing a fifth step of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross sectional view showing a sixth step of manufacturing the semiconductor device in one embodiment based on the present invention.

FIG. 8 is a sectional view showing a seventh step of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a sectional view showing an eighth step of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a cross sectional view showing a ninth step of manufacturing the semiconductor device in an embodiment of the present invention.

FIG. 11 is a sectional view showing a tenth step of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 12 is a sectional view showing an eleventh step of manufacturing the semiconductor device according to an embodiment of the present invention.

13 is a partially enlarged cross-sectional view of the contact portion in FIG.

FIG. 14 is a DRA when the present invention is applied to a DRAM.
It is sectional drawing which shows the cross-section of M.

FIG. 15 is an SRA when the present invention is applied to SRAM.
It is sectional drawing which shows the cross-section of M.

FIG. 16 is a diagram showing a schematic configuration of a manufacturing apparatus for carrying out the present invention.

FIG. 17 is a cross-sectional view showing an example of a semiconductor device having a conventional salicide structure transistor.

FIG. 18 is a cross-sectional view showing a first step in a manufacturing process of a conventional semiconductor device having a salicide transistor.

FIG. 19 is a cross-sectional view showing a second step in the manufacturing process of a conventional semiconductor device having a salicide structure transistor.

FIG. 20 is a cross-sectional view showing a third step in the manufacturing process of a conventional semiconductor device having a salicide transistor.

FIG. 21 is a cross-sectional view showing a fourth step in the manufacturing process of a semiconductor device having a conventional salicide transistor.

FIG. 22 is a cross-sectional view showing a fifth step in the manufacturing process of a conventional semiconductor device having a salicide transistor.

FIG. 23 is a cross-sectional view showing a sixth step in the manufacturing process of a conventional semiconductor device having a salicide transistor.

FIG. 24 is a cross-sectional view showing a seventh step in the manufacturing process of a conventional semiconductor device having a salicide transistor.

FIG. 25 is a cross-sectional view schematically showing that a silicon film is abnormally grown when the silicon film is formed based on the conventional manufacturing method.

FIG. 26 is a cross-sectional view schematically showing how a silicon film penetrates a titanium silicide layer and undergoes abnormal growth when a silicon film is formed by a conventional manufacturing method.

FIG. 27 is a cross-sectional view showing the first step when a silicon film is to be formed only by the PVD method.

FIG. 28 is a cross-sectional view showing a second step when a silicon film is to be formed using only the PVD method.

[Explanation of symbols]

 1, 21, 41, 71 p-type semiconductor substrate 5, 25, 42, 75 impurity region 7, 27, 43, 77 titanium silicide layer 10, 30, 50 second silicon film 10a, 30a, 50a first silicon film

Claims (2)

[Claims] 1. A metal silicide layer, a first silicon layer formed on the metal silicide layer and having a first physical / chemical property, a first silicon layer formed on the first silicon layer, and the first silicon layer. Physical·
A second silicon layer having a second physical / chemical characteristic different from the chemical characteristic, and a crystal discontinuity exists at a boundary between the first silicon layer and the second silicon layer. , Semiconductor devices. 2. A step of forming a metal silicide layer, a step of forming a first silicon layer on the metal silicide layer using a physical vapor deposition method, and a step of forming a first silicon layer on the first silicon layer using a chemical vapor deposition method. 2. A method of manufacturing a semiconductor device, comprising the step of forming a silicon layer.