JPH0969521A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress depletion due to diffusion of impurities into adjacent silicide or segregation at the interface to an insulation film when doped silicon is crystallized through heat treatment. SOLUTION: When doped silicon is deposited, impurity concentration is increased in the region contiguous to silicide but it is decreased in the region contiguous to insulation film. Alternatively, a step for adsorbing oxygen by about 1nm at the part where the impurity concentration varies is inserted additionally. Consequently, the characteristics of element are prevented from deteriorating due to depletion caused by diffusion of impurities in doped silicon into a metal silicide or segregation at the interface to an insulation film.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device using a doped polycrystalline silicon film or a laminated film of a doped polycrystalline silicon film and a metal silicide film as a wiring or an electrode. .

[0002]

2. Description of the Related Art In a process of manufacturing a semiconductor device, a process of forming a recon film containing impurities is diversified. For example, in a DRAM (Dynamic Random Access Memory), a gate electrode, a bit wiring, a stacked capacitor and the like are widely used. A silicon film containing these impurities is used as a single-layer electrode or a metal silicide film. It is used as an electrode of a laminated film. There are several methods for forming a silicon film containing these impurities. A typical example is a method in which an undoped polycrystalline silicon film not intentionally doped with an impurity is grown by a low pressure CVD method, followed by heat treatment in an impurity such as phosphorus oxytrichloride to diffuse the solid layer, or an ion implantation technique. There is a method of implanting an impurity by using GaN. Alternatively, when forming a silicon film containing impurities as it is by a low-pressure CVD method instead of an undoped polycrystalline silicon film using a normal batch-type low-pressure CVD apparatus, a temperature at which polycrystalline silicon is formed. (600 ° C. or higher) is very poor in uniformity of the film thickness and impurity concentration between wafers, so that the temperature at which amorphous silicon is formed (600 ° C. or lower)
Is generally used. In the case of forming a film using amorphous silicon, the film is crystallized by applying heat of 800 ° C. or more after forming the film, and becomes a conductor. Comparing the former method of introducing an impurity into an undoped silicon film and the method of forming a doped silicon film, the method of introducing an impurity into an undoped silicon film shows that the impurity is introduced from the surface and the doped silicon film is Is different in that a film is formed while performing doping. In a semiconductor manufacturing process that has become increasingly complicated in recent years, a method of forming a doped silicon film is becoming mainstream in order to reduce the number of processes as much as possible.

A conventional method of manufacturing a DRAM using a doped silicon film will be described below.

First, as shown in FIG. 10A, a gate oxide film 12 is thermally oxidized at about 700 to 900 ° C. on an active region of, for example, a P-type silicon substrate 10 partitioned by a predetermined element isolation region 11. Is formed, the phosphorus concentration is 1.5 ×
A doped amorphous silicon film 13 having a thickness of about 10 ²⁰ cm ^{−3 is formed} to a thickness of about 100 nm. Subsequently, a tungsten silicide film 14 having a thickness of about 100 nm is formed by using a sputtering method. Here, the tungsten silicide film 14 diffuses 5 × 10 5 over the entire surface of the wafer using an ion implantation technique in order to compensate for the decrease in the phosphorus concentration in the doped silicon film due to the diffusion.
Phosphorus may be ^{implanted at} about ¹⁹ cm ^-2 . At this time, the energy of the implantation is about 30 keV so that phosphorus reaches the interface between the doped amorphous silicon film 13 and the tungsten silicide film 14.

Next, by successively etching the tungsten silicide film 14 and the doped amorphous silicon film 13 using a lithography technique and a dry etching technique, as shown in FIG. A gate electrode pattern 15 (also serving as a word line pattern) is formed. Next, phosphorus or arsenic ions are implanted to form N-type implanted layers 16-1 and 16-2.

Subsequently, as shown in FIG. 10C, a silicon oxide film (B
(PSG film) is formed to a thickness of about 500 nm, and is heat-treated in a nitrogen atmosphere to reduce the surface step. In the heat treatment at this time, the lower doped amorphous silicon film 13 is crystallized to become a doped polycrystalline silicon film 13a, and a gate electrode also serving as a word line is completed. Next, a contact hole 18 having an opening size of 350 nm is formed by using a lithography technique and a dry etching technique. Next, the phosphorus concentration was again 2 × 10
A doped amorphous silicon film 19 of about ²⁰ cm ^-3
Then, the inside of the contact hole 18 is buried. Thereafter, a 100 nm-thick tungsten silicide film 20 is formed, and phosphorus ions are implanted again under the above-described conditions. Subsequently, the tungsten silicide film-doped amorphous silicon film is patterned using a lithography technique and a dry etching technique to form a bit wiring. Next, FIG.
As shown in FIG. 3, an interlayer insulating film 21 is formed, planarization is performed by heat treatment, a contact hole 22 reaching the N-type diffusion layer 16-2a is formed, and a doped amorphous silicon film 23 is deposited and patterned. As shown in FIG. 11B, a capacitor insulating film 25 is formed, and a plate electrode 26 of the capacitor is formed. The doped amorphous silicon film 19 is crystallized by the heat which is inevitably applied during the heat treatment for planarizing the interlayer insulating film 21 and the doped amorphous silicon film 23 is formed during the heat treatment for forming the capacitive insulating film. 19
a, the stack electrode 24 is formed.

[0007]

However, there are the following problems in the process of manufacturing a DRAM using the above-described conventional technology, particularly in the process using a doped silicon film.

First, in the step of forming a gate electrode, there has been a problem that impurities in a doped silicon film diffuse from a necessary portion to an unnecessary portion. That is, there is a problem that impurities in the doped silicon film are diffused into the tungsten silicide film due to a heat treatment inevitably applied in a later step, or are segregated at the interface between the doped silicon film and the gate insulating film. .

[0009] Tungsten silicide has a high solid solubility of impurities, so that when the impurity concentration of the doped silicon film is low, the impurities are almost absorbed into the tungsten silicide film. When the impurity concentration of the doped silicon film decreases, the space charge region of the portion facing the gate oxide film as a gate electrode expands, and there is a problem of deteriorating the characteristics of the transistor. The implantation compensates for the diffusion of impurities into the tungsten silicide film. However, since the crystal lattice of the doped silicon film is destroyed by the energy at the time of ion implantation, the impurity distribution after implantation is generated in the depth direction, and ions reaching the deep portion are deposited on the gate oxide film under the gate electrode. On the other hand, there is a problem in that the gate oxide film is damaged and the insulating property of the gate oxide film is deteriorated.

In particular, in recent miniaturized devices, there is a great need to reduce the level difference in the gate electrode portion due to processing problems, and the gate electrode is becoming increasingly thin. It was becoming increasingly difficult.

Therefore, a method of increasing the impurity concentration in the doped silicon film from the beginning can be considered. However, when the doped amorphous silicon film having a high concentration is heat-treated, there is a problem that segregation of impurities easily occurs at the interface with the oxide film. This is because when the doped amorphous silicon film is crystallized,
This is because heat treatment at a relatively low temperature of 850 ° C. or lower has a slow crystallization speed, and impurities are sufficiently moved while silicon atoms are bonded to each other, so that the impurity atoms are 'pushed out' from the film. In recent devices, the temperature of the heat treatment process has been increasingly reduced in order to keep the diffusion layer region of the device small, and it has become important to minimize the decrease in the "push-out" of impurities from doped silicon.

The impurity distribution in the depth direction of the insulating film-doped silicon-silicide structure as seen in the gate electrode and the bit wiring layer will be specifically described. 12 and 13 show a silicon oxide film (insulating film) -phosphorus-doped silicon film of about 100 nm-tungsten silicide film of about 100
FIG. 9 shows an impurity distribution in a depth direction in a phosphorus-doped silicon film having a structure of nm.

FIGS. 12 (a) and 12 (b) show the distribution of impurities in the depth direction after the film formation and after the heat treatment when the phosphorus concentration of the doped silicon is a relatively low concentration of about 8 × 10 ¹⁹ cm ^−3. 13 (a) and 13 (b) are those of a doped silicon film having a high phosphorus concentration of 3 × 10 ²⁰ cm ⁻³ in the doped silicon film. In each figure, (a) shows before heat treatment, that is, before crystallization, and (b) shows after heat treatment, that is, after crystallization. In each of the figures, it can be seen that when heat treatment is performed, phosphorus escapes from the vicinity of silicide in the doped silicon film, and the concentration decreases. In particular, it can be seen that the phosphorus content at the interface of the tungsten silicide film is greatly reduced in the case of a doped silico film that originally has a low phosphorus concentration. It is also confirmed that phosphorus is segregated at the interface with the silicon oxide film. Segregation occurs to some extent even at low phosphorus concentrations. When such a structure is applied to the gate electrode, if there is a region where the impurities are extremely concentrated due to the segregation of the impurities, a secondary recrystallization occurs due to the heat treatment that is performed in a subsequent process, which locally gives a large stress to the gate oxide film. This causes a decrease in withstand voltage. FIG. 14 shows an example of the relative frequency of the breakdown voltage failure of the gate oxide film. The current density was set to 0.1 mA / cm ² as a criterion for the breakdown voltage failure. Electric field strength 4-8 MV / c
About 10 to 20% of B-mode defects exist around m.

Further, the problem of segregation of impurities from the doped silicon film has been observed not only in the gate electrode but also in a wiring or an electrode having a contact, that is, a bit wiring or a stack electrode. This is because the impurities are extruded during the heat treatment after the formation of the doped silicon film, so that the impurities are segregated between the diffusion layer under the contact and the contact, and the segregated impurities are diffused into the substrate by further performing the heat treatment. This is the phenomenon. In the growth of a doped silicon film having a contact, a natural oxide film is inevitably formed on the surface of the silicon substrate when entering the furnace at the start of growth. Phosphorus segregates in the natural oxide film layer at the interface between the silicon substrate and the doped silicon film, and serves as a diffusion source into the substrate. FIG. 15 shows an example of the phosphorus concentration distribution in the contact portion between the phosphorus-doped silicon film and the silicon substrate. Due to such segregation and diffusion of phosphorus, there is a serious problem such as a change in the channel length of the transistor near the contact, a reduction in the threshold voltage of the parasitic transistor, and other adverse effects on the device.

Accordingly, a first object of the present invention is to provide a method for forming a doped silicon film capable of preventing impurities from segregating at an interface with an insulating film such as a gate insulating film or a contact interface with a semiconductor substrate. It is in. A second object of the present invention is to provide a method for improving the uniformity of the impurity concentration in a doped silicon film when forming a two-layer film of a doped silicon film and a metal silicide film. .

[0016]

A first method of manufacturing a semiconductor device according to the present invention comprises a step of forming an undoped amorphous silicon film by coating a predetermined insulating film on a semiconductor substrate,
The method includes the step of forming a doped amorphous silicon film, and the step of forming a doped polycrystalline silicon film including a step of polycrystallizing by heat treatment.

According to a second method of manufacturing a semiconductor device of the present invention, a step of forming an undoped amorphous silicon film by covering a predetermined insulating film on a semiconductor substrate, and forming a first doped amorphous silicon film. A step of forming a second doped amorphous silicon film having a concentration higher than that of the first doped amorphous silicon film, a step of depositing a metal silicide film, and a heat treatment to increase the amount of amorphous silicon. And a step of forming a two-layer film of a doped polycrystalline silicon film-metal silicide film including a crystallization process.

In the first and second semiconductor device manufacturing methods, an impurity diffusion having a conductivity type different from that of the surface portion of the semiconductor substrate in which an insulating film is selectively formed on the surface portion of the gate insulating film or the semiconductor substrate. An interlayer insulating film having a contact hole reaching the layer can be formed. Further, the amorphous silicon film can be formed by the low pressure CVD method. In that case, a silane gas and a phosphine gas can be used as a deposition gas and an impurity gas, respectively. Further, a step of interrupting the supply of the film-forming gas and the impurity gas and supplying the oxygen gas to adsorb oxygen to the amorphous silicon film is inserted, thereby corresponding to the adsorbed portion in the doped polycrystalline silicon film. It is also possible to segregate impurities in portions, and it is preferable to form an adsorption layer having a thickness of 0.5 nm to 2 nm.

Since the non-doped amorphous silicon film is formed first, an abnormal increase in impurity concentration due to the deposition of impurities on the interface with the insulating film is reduced.

[0020]

Next, a first embodiment of the present invention will be described. The first embodiment of the present invention relates to a method for forming a doped silicon film-metal silicide structure of a gate electrode of a transistor. First, in the same manner as in the prior art, a gate oxide film is formed by performing a heat treatment in an oxidizing atmosphere on an active region of a P-type silicon substrate 10 partitioned by element isolation regions 11 as shown in FIG. 12 is formed to a thickness of about 10 nm. Next, a phosphorus-doped silicon film is grown to a thickness of about 100 nm using a low-pressure CVD apparatus in the following manner.

FIG. 1A shows a film forming sequence showing the flow rates of the silane gas and the phosphine gas at the time of forming the amorphous silicon film in the first embodiment of the present invention. Here, 100% silane gas is used, and 1% nitrogen-based phosphine gas is used. The film forming temperature is around 530 ° C., and the film forming pressure is 2 torr.
Use the values before and after. When the amorphous silicon film is formed under these conditions, the film formation rate hardly depends on the phosphorus concentration of the film, and is stable at about 2.4 to 2.8 nm / min.

First, a film having a thickness of 10 n is formed by using only silane gas for about 3 to 4 minutes in an initial stage of film formation.
An about m non-doped amorphous silicon film is formed.
Subsequently, phosphine gas is gradually introduced into the reaction tube while flowing silane gas, and the flow rate of phosphine is increased at a rate of about 5 sccm / min. When the flow rate of the phosphine gas reaches about 20 sccm, the gas continues to flow for about 20 minutes at the same flow rate ratio. Thus, a first doped amorphous silicon layer having a thickness of about 50 nm and a low phosphorus concentration of about 0.8 × 10 ²⁰ cm ⁻³ is formed. Subsequently, the flow rate of the phosphine gas is again set to 10 sccm /
increase to about 100sccm at a rate of about min,
The flow rate of silane was set at 40 sccm / min for 800 s.
Reduce to about ccm. By performing film formation for about 10 minutes as it is, a second doped amorphous silicon film having a thickness of about 40 nm is formed, and an amorphous silicon film having a total thickness of about 100 nm is formed. Phosphine flow rate 100s
After reaching ccm, the phosphorus concentration increases to about 3 × 10 ²⁰ cm ⁻³ . After all, the phosphorus concentration in the formed amorphous silicon film is as shown in FIG.

After the step of forming the amorphous silicon film (corresponding to 13 in FIG. 10A) is completed, the tungsten silicide film 14 is formed to a thickness of about 100 nm by the sputtering technique as in the conventional example, and the lithography technique is used. A wiring layer having a laminated structure of tungsten silicide and phosphorus-doped silicon is patterned by using a dry etching technique to form a gate electrode pattern (also serving as a word wiring pattern). After the gate electrode pattern is formed, an interlayer insulating film 17 is formed, heat treatment for reflow is performed, a contact hole is opened, a bit wiring is formed, an interlayer insulating film is further formed, and a capacitor electrode portion is formed. A DRAM can be obtained. The amorphous silicon film is subjected to a heat treatment of about 850 ° C. in a subsequent step of reflowing the interlayer insulating film and forming the capacitor insulating film, and the finished product is a phosphorus-doped polycrystalline silicon film.

FIG. 2 shows the phosphorus concentration distribution in the depth direction of the silicon film thus formed immediately after the film formation (amorphous silicon film) and after the product is completed (polycrystalline silicon film).
It shows in (a) and FIG.2 (b). Immediately after the film formation, the portion under the gate oxide film has a very low phosphorus concentration, and the portion above the tungsten silicide film has a high phosphorus concentration. Therefore, in the region near the tungsten silicide film in the silicon film, there is a sufficient amount of impurities to be diffused into the tungsten silicide film during the heat treatment, so that it is not necessary to further implant the impurities by the ion implantation method, and the gate oxide film is also formed. Since the amount of impurities is extremely small in the region close to, the amount of impurities segregated at the interface with the gate oxide film can be suppressed low. Further, since the impurity distribution immediately after the film formation changes continuously in the depth direction, the distribution becomes almost uniform after the heat treatment.

In the gate electrode actually manufactured using the first embodiment of the present invention, the resistance of the polycrystalline silicon film does not increase due to the diffusion of impurities into tungsten silicide, and the gate due to the segregation of impurities does not occur. The deterioration of the oxide film can be almost eliminated. FIG. 3 shows the relative frequency of breakdown voltage failure per wafer when an electric field intensity of 0 to 10 MV / cm is applied to the gate oxide film for a predetermined time. The dielectric strength was determined at a current density of 0.1 mA / cm ² .
Gate electrode using conventional technology (FIG. 14) 4 to 8M
About 20 to 20% of B-mode defects near V / cm exist. On the other hand, it can be seen that the use of the present embodiment has reduced these defective rates to less than half. This is because the ion implantation used in the prior art is not used, and the segregation of impurities at the gate oxide film interface is reduced. According to this embodiment, the characteristics of the gate electrode and the gate insulating film are greatly reduced. Can be improved.

Next, a second embodiment of the present invention will be described. First, a gate oxide film 12 having a thickness of about 10 nm is formed on an active region by heat-treating a P-type silicon substrate 10 having an element isolation region 11 in an oxidizing atmosphere in the same manner as in the prior art and the first embodiment. Next, decompression C
Using a VD apparatus, an amorphous silicon film is reduced to about 1 in the following manner.
Grow by 00 nm.

The growth of the amorphous silicon film is performed at a temperature of 530 ° C.
At a pressure of 1.8 torr, only the gas flow rate is changed over time. FIG. 4 (a) shows a diagram of a temporal change of the gas flow rate.
First, a non-doped amorphous silicon film having a thickness of about 10 nm is formed by performing film formation for 3 to 4 minutes using only silane gas in the initial stage of film formation. Subsequently, phosphine gas is gradually introduced into the reaction tube while flowing silane gas, and the flow rate of phosphine is increased at a rate of about 5 sccm / min. Phosphine flow rate 20 scc
When the pressure reaches about m, the supply of the silane and phosphine gas is temporarily stopped in this state, and oxygen diluted with 1% nitrogen is introduced into the reaction furnace at 15 sccm and exposed for about 5 minutes. Here, an oxygen adsorption layer of about 1 nm is formed on the surface of the phosphorus-doped amorphous silicon film. Next, silane and phosphine gases are supplied again, and film formation is continued at the original gas flow rate for about 20 minutes. Subsequently, the supply of silane and phosphine gas was stopped again, oxygen diluted with 1% nitrogen was introduced into the reaction furnace at 15 sccm, and exposed for about 5 minutes.
m and phosphine are introduced at 100 sccm to form a phosphorus-doped amorphous silicon film having a high phosphorus concentration for about 15 minutes.
After all, the phosphorus concentration distribution immediately after the formation of the amorphous silicon film is shown in FIG.
As shown in FIG.

After the formation of the amorphous silicon film,
Tungsten silicide film is formed by sputtering
A film having a thickness of 0 nm is formed, and a gate electrode pattern is formed by using a lithography technique and a dry etching technique. After that, an interlayer insulating film is formed, and after a heat treatment for reflow is performed, a contact hole is opened, a bit wiring is formed, a further interlayer insulating film is formed, and a capacitor electrode portion is formed.

FIGS. 5A and 5B show a comparison of the impurity distribution in the depth direction of the silicon film for the gate electrode using the present embodiment between the film formed immediately after the film formation and the film formed after the heat treatment.
It is. From this figure, it can be seen that immediately after the film formation, segregation of impurities occurs in the vicinity of the portion corresponding to the oxygen adsorption layer due to exposure in an oxidizing atmosphere during the process. On the other hand, it can be seen that the amount of impurities segregated at the interface with the underlying gate oxide film is significantly reduced as compared with the first embodiment of the present invention. This indicates that during the heat treatment, the amount of impurities reaching the gate oxide film interface has decreased due to the change in the oxygen-adsorbed layer in the film, possibly due to the trapping of impurities in the layer containing silicon oxide. .

FIG. 6 shows the relative frequency of breakdown voltage failure of the gate oxide film under the gate electrode formed by using the phosphorus-doped polycrystalline silicon film thus formed. From this, it can be seen that the conventional B-mode failure has hardly been seen. This is because the ion implantation used in the prior art is not used, and the segregation of impurities is almost eliminated. Since the adsorbing layer in the middle is as thin as about 1 nm, the resistivity is slightly increased, and the capacitor is not formed by insulating the upper and lower layers. As described above, when the second embodiment of the present invention is used, the gas system at the time of film formation increases as compared with the first embodiment, but the first method is used to suppress the segregation of impurities.
There is an advantage that the present embodiment is superior to the embodiment.

Next, a third embodiment of the present invention will be described. In this embodiment, a method for growing a doped silicon film according to the present invention is used for forming a stacked capacitor lower electrode in a DRAM or the like.

The steps up to the formation of the contact hole 22 in FIGS. 10A to 11A are the same as those in the prior art or the first or second embodiment.

Subsequently, a step of forming a silicon film containing impurities, which is a main part of the present invention, is performed. Using the sequence shown in FIG. 7A, a silicon film having phosphorus as an impurity is deposited. First, a non-doped amorphous silicon film containing no impurities is deposited for about 5 minutes using 100% silane, and then 1% phosphine is gradually introduced into the reaction tube to obtain a flow rate of about 20 sccm. The film is formed for about 2 hours, and the flow rate of the phosphine gas is kept constant.

FIG. 7B shows the distribution of the phosphorus concentration in the depth direction immediately after the film formation. By performing the method for growing a sircon film of the present embodiment, in the state after film formation, a doped amorphous silicon film is formed after forming a non-doped amorphous silicon film of about 10 to 15 nm in a portion connected to a contact. Then, a silicon film having a thickness of about 300 nm is formed.

After the formation of the amorphous silicon film, a stack electrode pattern is formed, and the silicon nitride film (capacitor insulating film) is processed at about 800 ° C. and 0.3 torr in a mixed atmosphere of dichlorosilane and ammonia. About 5 nm is formed. After forming the silicon nitride film, a doped silicon film is formed again to a thickness of about 150 nm.

In this embodiment, the amorphous silicon film is easily crystallized at a temperature of about 800 ° C. when forming the silicon nitride film. At the time of crystallization, diffusion of phosphorus as an impurity occurs. Final doped polycrystalline silicon film and N-type diffusion layer 1
FIG. 8 shows the distribution of impurities in the depth direction at the 6-2a interface. Compared with FIG. 15 showing the impurity distribution in the depth direction when a conventional P-doped silicon film is used, the segregation amount of impurities is significantly suppressed in the case of using this embodiment compared to the conventional case, and It can be seen that the diffusion distance of the impurity is small. As a result, the characteristic deterioration of the element, which has conventionally occurred due to the change in the impurity concentration distribution, is greatly suppressed.

In this embodiment, a step of adsorbing oxygen during the film formation can be inserted as in the second embodiment. In the case of an amorphous silicon film having a high impurity concentration or a high heat treatment temperature in the post-process, the effect of preventing the diffusion of the impurities is insufficient in the third embodiment. However, as shown in FIG. By introducing one or two adsorption layers in the vicinity of about 10 to 50 nm away from the interface between the film and the doped amorphous silicon film, a greater effect of preventing impurity diffusion can be obtained.

Although the case where the doped polycrystalline silicon film-tungsten silicide film is used for the gate has been described above, the present invention can be applied to the case where it is used as a wiring such as a bit wiring. Also, the case where the doped polycrystalline silicon film is used for the lower electrode of the capacitor has been described, but the present invention can be applied to the case where it is used as a wiring such as a gate electrode.

Further, the case where the silicon film is doped with phosphorus has been described. However, the impurity is not particularly limited to phosphorus, and is not limited to n-type impurities such as arsenic and antimony, but also p-type impurities such as boron. The same applies to silicon.

Further, the present invention can be applied to not only tungsten silicide but also other metal silicides such as titanium silicide and molybdenum silicide.

[0041]

As described above, according to the present invention, first, an undoped amorphous silicon film is deposited on an insulating film, then a doped amorphous silicon film is deposited, and then a heat treatment is performed to polycrystallize the film. The segregation of impurities near the interface with the insulating film or near the interface with the semiconductor substrate that is in contact with the contact hole provided in the insulating film is suppressed, which has the effect of preventing adverse effects on device characteristics. In the case of forming a two-layer film of a doped polycrystalline silicon film and a metal silicide film, forming a high-concentration doped amorphous silicon film on the metal silicide film side allows the impurity concentration in the polycrystalline silicon film after the heat treatment to be increased. Can be prevented from becoming lower than other portions on the metal silicide film side and increasing the resistance. Further, by inserting a step of adsorbing oxygen by interrupting the formation of the amorphous silicon film, undesired diffusion can be suppressed by segregating impurities to a portion corresponding to the adsorbed portion in the polycrystalline silicon film. Therefore, a greater effect can be obtained.

[Brief description of drawings]

FIG. 1 is a graph showing a change in the flow rate of a film forming gas and an impurity gas according to a first embodiment of the present invention (FIG. 1A) and a graph showing a phosphorus concentration distribution during film formation (FIG. 1B). ).

FIG. 2 is a graph showing a phosphorus concentration distribution in an amorphous silicon film (FIG. 2A) and a graph showing a phosphorus concentration distribution in a polycrystalline silicon film in the first embodiment (FIG. 2).
(B)).

FIG. 3 is a graph showing the relative frequency of breakdown voltage failure of the gate according to the first embodiment.

FIG. 4 is a graph showing a change in gas flow rate (FIG. 4A) and a graph showing a phosphorus concentration distribution during film formation (FIG. 4A) in the second embodiment of the present invention.

FIG. 5 is a graph showing a phosphorus concentration distribution in an amorphous silicon film in the second embodiment (FIG. 5A) and a graph showing a concentration distribution in a polycrystalline silicon film (FIG. 5B). It is.

FIG. 6 is a graph showing a relative frequency of a relative failure of a gate withstand voltage failure according to the second embodiment.

FIG. 7 is a graph (FIG. 7A) showing a change in the flow rate of a film forming gas and an impurity gas and a graph showing a phosphorus concentration distribution at the time of film forming (FIG. 7 (B)) in a third embodiment of the present invention. ).

FIG. 8 is a graph showing a phosphorus concentration distribution near a contact portion according to a third embodiment.

FIGS. 9A and 9B are a graph showing a change in gas flow rate (FIG. 9A) and a graph showing an impurity concentration distribution during film formation (FIG. 9B) for explaining a modification of the third embodiment; is there.

FIGS. 10A to 10C are cross-sectional views illustrating a method of manufacturing a DRAM in the order of steps shown in FIGS.

FIG. 11 is a sectional view in order of the processes, which is divided into (a) and (b) subsequent to FIG. 10;

FIG. 12 is a graph showing an example of a phosphorus concentration distribution immediately after film formation in a silicon film by a conventional technique (FIG. 12A) and a graph showing an example of a phosphorus concentration distribution after heat treatment (FIG. 12).
(B)).

FIG. 13 is a graph showing another example of the phosphorus concentration distribution immediately after the film formation in the silicon film according to the conventional technique (FIG. 13A) and another example of the phosphorus concentration distribution after the heat treatment (FIG. 1).
3 (b)).

FIG. 14 is a graph showing the relative frequency of breakdown voltage failure of a gate according to a conventional technique.

FIG. 15 is a diagram showing a phosphorus concentration distribution near a contact portion according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 P-type silicon substrate 11 Element isolation region 12 Gate oxide film 13 Doped amorphous silicon film 14 Tungsten silicide film 15 Gate electrode pattern 16-1, 16-2 N-type injection layer 17 Interlayer insulating film 18 Contact hole 19 Doped amorphous Porous silicon film 20 tungsten silicide film 21 interlayer insulating film 22 contact hole 23 doped silicon film 24 attack electrode 25 capacitor insulating film 26 plate electrode

Claims (7)

[Claims] 1. A step of covering a predetermined insulating film on a semiconductor substrate to form an undoped amorphous silicon film, and a first step.
A method of manufacturing a semiconductor device, comprising: a step of forming a doped amorphous silicon film, and a step of forming a doped polycrystalline silicon film by heat treatment. 2. A step of forming an undoped amorphous silicon film by covering a predetermined insulating film on a semiconductor substrate, and a first step.
Forming a doped amorphous silicon film, forming a second doped amorphous silicon film having a higher concentration than the first doped amorphous silicon film, and depositing a metal silicide film. A doped polycrystalline silicon film including a step of polycrystallizing amorphous silicon by heat treatment,
A method of manufacturing a semiconductor device, comprising a step of forming a two-layer film of a metal silicide film. 3. An interlayer insulating film having a contact hole reaching an impurity diffusion layer having a different conductivity type from a surface portion of the semiconductor substrate, wherein the insulating film is selectively formed on a surface portion of the semiconductor substrate. 3. The method for manufacturing a semiconductor device according to claim 1 or 2. 4. The method according to claim 1, wherein the amorphous silicon film is formed by a low pressure CVD method. 5. The method for manufacturing a semiconductor device according to claim 4, wherein a silane gas and a phosphine gas are used as a film forming gas and an impurity gas, respectively. 6. A step of interrupting the supply of the film forming gas and the impurity gas and supplying an oxygen gas to adsorb oxygen to the amorphous silicon film, whereby the adsorbing portion in the doped polycrystalline silicon film is inserted. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the impurities are segregated in a portion corresponding to the above. 7. The method of manufacturing a semiconductor device according to claim 6, wherein an adsorption layer having a thickness of 0.5 nm to 2 nm is formed.