JPH0636579A - Method and device for controlling memory access - Google Patents

Abstract

PURPOSE:To effectively utilize one piece of memory chip of a flash ROM, etc., and to improve its availability. CONSTITUTION:The memory chip M1 is capable of forming a write unit in an optional size by dividing it to plural areas at every prescribed address range. When the cumulative value of the number of write times of the memory chip M1 for the area 5 arrives at a limit value, other area 6 in the empty area as the object of access by a CPU 1 is set and switched, and thereafter, information is written in the area 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method and apparatus for controlling access to a memory such as a flash ROM or EPROM having a limited number of times of writing (hereinafter collectively referred to as "flash memory"). Regarding

[0002]

2. Description of the Related Art In recent years, it has been considered to use a flash memory, which retains stored contents even when the power is turned off, as an external storage device. Since this flash memory has a limited number of writes, the cumulative value of the number of writes is always checked when writing information, and when the cumulative value reaches the limit value,
The target of access is switched from the current memory chip to another memory chip, and information is written to that memory chip.

FIG. 4 shows a concrete example of this type of memory access control device disclosed in Japanese Patent Laid-Open No. 2-27596. In the figure, M1 to Mn are n memory chips prepared in advance, and the first memory chip M1 shown by the thick line among these is the target of access by the CPU 1. The selection circuit 2 is for switching and selecting an access target.

At the time of writing information, when the cumulative value of the number of times of writing to the first memory chip M1 reaches the limit value, the selection circuit 2 prohibits the access of the first memory chip M1 and the access target is Switching to the second memory chip M2, the information is written to that memory chip M2. Similarly, the following memory chips M2 to Mn
Every time the number of writings reaches the limit value, the access target is sequentially switched. Each memory chip M1 to Mn
If the limit value of the number of times of writing for x is x, the number of writable times is (n × x). The address viewed from the CPU 1 is the same as that when there is one memory chip.

[0005]

When the memory capacity of the memory chip is increased in order to use the flash memory for external storage, if the number of writes is limited on a chip-by-chip basis as described above, one memory chip is used. Cannot be used effectively,
Its utilization rate is extremely low.

The present invention has been made in view of the above problems, and by effectively using one memory chip by dividing one memory chip for each predetermined address range and using it. An object of the present invention is to provide a memory access control method and a device therefor with improved rate.

[0007]

According to a first aspect of the present invention, there is provided a memory access control method for controlling access to a flash memory having a limited number of writing operations. It is characterized in that when the cumulative value of the number of times of writing for a certain section reaches a limit value, the access target is switched to another section and information is written to that section.

According to a second aspect of the present invention, there is provided a memory access control device for controlling access to a flash memory having a limited number of writing operations, wherein the flash memory is divided into predetermined address ranges. Storage means for storing the limit value of the number of times of writing and the cumulative value of the number of times of writing for each;
Determination means for determining whether or not information can be written in each section of the flash memory by referring to the stored contents of the storage means;
And a switching unit that determines and switches the section of the flash memory to be accessed in accordance with the determination whether the information can be written by the determination unit.

[0009]

The flash memory is divided into predetermined address ranges, and when the number of times of writing to a certain section reaches the limit value, thereafter, the access target is switched to another section and the information is written to that section. As a result, a write unit of any size is formed for one memory chip, and
The individual memory chips are effectively used and the utilization rate is improved.

According to another aspect of the memory access control device of the present invention, when the information is written, if the cumulative value of the number of times of writing stored in the storage means is smaller than the limit value, the current classification as the access target is determined. If it is selected and the cumulative value has reached the limit value, it is switched to another section and the information is written respectively.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the circuit configuration of a memory access control device embodying the present invention. In the figure, M1 to Mn are n memory chips such as a flash ROM prepared in advance, and the CPU1 makes each of the memory chips M1 to Mn.
Is accessible as in the past.

Each memory chip M1 to Mn can be divided into a plurality of areas for each predetermined address range to form a writing unit of an arbitrary size, and each area is managed as a file. File management data of RAM
It is stored in 3. In FIG. 1, an area 5 of the memory chip M1 indicated by diagonal lines is a current access target area, and when the cumulative value of the number of writings to this area 5 reaches a limit value, the area 5 in the empty area is targeted for access. Other areas 6 can be set and switched.

The RAM 3 is backed up by a battery 4, and the structure of the file management data stored in the RAM 3 is illustrated in FIG. This file management data includes a limit value a of the number of times of writing, a cumulative value b of the number of times of writing, an address start value c of the area to be accessed, a data amount d secured in the area, and other attributes e. Contains data. The other attribute e includes information indicating whether or not information can be written in this file.

When writing information, the CPU 1 determines whether or not information can be written in the area 5 to be accessed according to the control procedure shown in FIG. 3, and the area to be accessed according to the determination. Select and switch to write information.

First, in step 1 of FIG. 3 (indicated by "ST1" in the figure), the CPU 1 cumulatively writes the number of times of writing b.
Is determined to be equal to or less than the write count limit value a. If the determination is “NO”, that is, if the cumulative value b of the number of times of writing has not reached the limit value a, the process proceeds from step 1 to step 5 to transfer the write data to the area 5 to be accessed, At step 6, the cumulative value b of the number of writings is incremented.

If the cumulative value b of the number of times of writing agrees with the limit value a, the determination in step 1 becomes "YES", and in the next step 2, whether or not there is an empty area in the same memory chip M1. Is searched by referring to a management file in an empty area (not shown).

If there is a free area, the determination in step 2 becomes "YES", and the area 6 of a size necessary for writing information is secured in the free area, and the data amount of the file management data is increased. After setting d and rewriting the address head value c to the head address of the area 6, the write data is transferred and the cumulative value b of the number of times of writing is incremented (steps 5 and 6). This prohibits access to the previous area 5.

If it is determined in step 2 that there is no free area in the same memory chip M1, the process proceeds from step 2 to step 7 and the display indicates that the memory chip M1 has overflowed. , Prompt replacement of memory chip.

Although the file management data is stored in the RAM 3 in the above embodiment, each time the power is turned off,
It is also possible to transfer the stored contents to a predetermined area of the memory chip.

[0020]

As described above, according to the present invention, the flash memory is divided into predetermined address ranges, and when the number of times of writing to a certain section reaches the limit value, thereafter, the access target is switched to another section. Since the information is written to that section, a write unit of an arbitrary size is formed for one memory chip, and one memory chip is effectively used, and its utilization rate is improved. Play.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory access control device embodying the present invention.

FIG. 2 is an explanatory diagram showing a structure of file management data.

FIG. 3 is a flowchart showing a control procedure by a CPU.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 M1 to Mn memory chip 1 CPU 3 RAM

Claims (2)

[Claims] 1. A memory access control method for controlling access to a flash memory with a limited number of writes, wherein the flash memory is divided into predetermined address ranges, and the number of writes is accumulated in a certain section. A memory access control method, wherein when a value reaches a limit value, an access target is switched to another section and information is written to the section. 2. A memory access control device for controlling access to a flash memory having a limited number of write operations, wherein the flash memory is divided into predetermined address ranges and the number of write operations is divided into each division. Storage means for storing the limit value and the cumulative value of the number of times of writing, judgment means for judging whether or not information can be written in each section of the flash memory by referring to the stored contents of the storage means, and information by the judgment means Memory access control device, which determines and switches the section of the flash memory to be accessed according to the determination of whether the writing is possible or not.