JPH0636550B2 - Digital copier - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a recording apparatus which reads a document image, converts it into an electric signal, processes the electric signal, and converts image information into binary information of recording / non-recording. The present invention relates to a digital copying machine.

[Prior Art] Generally, in a digital copying apparatus, an analog electric signal obtained at the output of the image sensor by reading a document image in a minute area, that is, by using a CCD (charge coupled device) image sensor or the like. Is subjected to A / D (analog / digital) conversion, various processing is performed on the obtained digital signal, and the signal is given to a recording device to obtain a copy image.

By the way, since it is difficult to change the density level for each recording pixel in the recording apparatus used for this type of apparatus, it is general to perform binary recording / non-recording. However, since the original may include a halftone image such as a photograph, it is necessary to reproduce the halftone image. Dither method, density pattern method, sub-matrix method, etc. have been conventionally proposed as a method for expressing a halftone image by using a recording device for binary recording, and by using these methods, a halftone image is reproduced. it can.

However, when performing halftone processing, a relatively preferable copy image is obtained when the original image density changes gently like a photograph, but when the original image density changes binary like a character. In this case, the contour of the copy image is blurred and it becomes difficult to read the characters, or the stain on the background of the original appears on the copy image, and the copy quality significantly deteriorates.

For original images such as characters, do not perform halftone processing,
A simple binary operation yields the desired copy. Therefore, if a switch for specifying the presence / absence of halftone processing is provided, a preferable copy mode can be selected by the operator's judgment according to the type of the original.

However, for example, like a pamphlet, there are many cases where a half-tone image such as a photograph and a binary image such as a character are mixed in one document. In such a case, if the binary mode is selected, the quality of the photograph is degraded, and if the halftone mode is selected, the quality of the character is degraded.

By the way, in this kind of digital copying apparatus,
There are two disadvantages. That is, when an image is read in small pixel units using a line sensor or the like, if the density change on the document has a periodicity, interference between the period (pitch) and the arrangement pitch (sampling period) of the image reading sensor causes Moire may occur on a recorded image. For example, when halftone printing is performed on a document, since the density change on the image has a periodicity, moire occurs due to interference between the density change cycle and the sampling cycle of the reading sensor.

For example, if the resolution of the image reading sensor is 16 pixels / mm, halftone dot printing with a density close to that resolution, ie 133
When the density is in the range of lines (about 10.5 pixels / mm) to 200 lines (about 16 pixels / mm), moiré is likely to occur in the read signal. Of course, moire also occurs at other densities, but especially at the above densities, the moire occurs remarkably, and the fluctuation range of the signal due to it is large.

The halftone dot printing itself is a kind of pseudo halftone expression, and the density change in pixel units is a binary value of 1/0 (recording / non-recording). In the halftone dot printing, the average density when the entire pixel set is viewed is changed in multiple steps by changing the pitch of the halftone dots or the size of the halftone dots, thereby expressing the halftone density. Therefore, if the problem of moire is not taken into consideration, when copying a document image for halftone printing, it is possible to reproduce a halftone image on a recorded image and perform preferable copying by processing the signal in a binary manner. it can. But in reality,
With respect to the original image printed with halftone dots at a specific density, the moire occurs as described above, so that the copy quality is significantly deteriorated.

On the other hand, when the image read signal is subjected to halftone processing to be converted into a binary signal, in the process of processing, the averaging of the densities of a plurality of pixels, the change of the threshold level, etc. are performed, and as a result, a moire image is obtained on the copy image. Does not occur or the effect is small. In this case, the density of the copy image is represented by a halftone dot, but the halftone dot on the copy is not a direct reproduction of the halftone dot on the original, and is a halftone dot generated by the halftone processing peculiar to the copying machine. It is a point.

Therefore, when a halftone-printed image or an image copied by halftone processing by a digital copying machine is an original, binary recording is performed in pixel units, but a method of selecting a copy mode for performing halftone processing is selected. Is preferred.

[Object of the Invention] The present invention is also preferable for a document in which a halftone image and a binary image are mixed by automatically determining whether each region on the document is a halftone image or a binary image. The primary purpose is to obtain a copy. A second object of the present invention is to prevent the occurrence of moire when an image in which halftones are expressed by halftone dots is a document.

[Configuration of the Invention] In order to achieve the above object, in the present invention, area determination means for processing an electric signal obtained from the image reading means to determine whether the original image is a halftone image is provided, and the area determination is performed. The signal output to the recording means such as a printer is switched according to the determination result of the means. That is, when the area determination unit determines that halftone information is present, a halftone processed signal is selected, and when it is determined that there is no halftone information, a simple binarized signal is selected.

The area determination means includes; a serial-parallel conversion means for simultaneously outputting signals of a plurality of pixels adjacent to each other in the main scanning direction and the sub-scanning direction of the image reading means, and processing a plurality of signals output by the serial-parallel conversion means. For a signal of each pixel, a pixel detection unit that determines whether or not the pixel of interest and surrounding pixels have a halftone dot pattern arrangement, and a signal output from the pixel detection unit is processed to form a first region including a plurality of pixels. In the first area detection means for determining the presence or number or the number of pixels that have detected the halftone dot-like pattern, and processing a signal output from the first area detection means to form a plurality of sets of the first areas. The second area detecting means for determining the presence or absence of the halftone dot pattern for the second area, and the halftone dot detecting means for detecting whether the arrangement of the black level or white level pixels of the original image is the halftone dot shape; If halftone dots are detected, the image To halftone processing.

If the halftone processed signal is selected, the halftone density is reproduced in the recorded image. If the simple binarized signal is selected, the density of the recorded image becomes binary. Half-tone processed signal,
Since switching to the signal subjected to the simple binarization is automatically performed, even if a halftone density image such as a photograph and a binary density image such as a character are mixed in one document, the image of the image is mixed. The signal is automatically switched each time the type is changed, whereby both the halftone density image and the binary density image are reproduced on the copy in a preferable state.

If the original is a halftone dot image, the signal obtained by reading the image is subjected to halftone processing, so that the occurrence of moire is suppressed.

In a preferred embodiment of the present invention, in order to improve the accuracy of halftone dot detection, the signal output from the second area detecting means is processed to produce a third area (second area) formed of a plurality of sets of the first areas. The third area detection means for determining the presence / absence of a halftone dot-like pattern (for a different area).

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows one type of digital copying machine embodying the present invention. This copying machine is roughly divided into a scanner 1 on the upper side of the apparatus and a printer 2 on the lower side of the apparatus.

Reference numeral 26 is a contact glass on which a document is placed. The scanner 1 scans and reads an image of a document placed on the contact glass 26. The sub-scanning is mechanical, and the carriage provided in the scanner moves right and left in FIG. 2 by driving the electric motor MT. The reflected light from the document is imaged on the fixed image reading sensor 10 via various mirrors and lenses. The image reading sensor 10 is a CC
This is a D line sensor, and in FIG. 2, a large number of reading cells are arranged in a direction perpendicular to the paper surface. In this example, when the copy magnification is 1.0, 1
The resolution is 6 pixels. Main scanning is performed by this image reading sensor 1
It is performed electrically by a CCD shift register provided inside 0. The main scanning direction is the reading cell array direction,
That is, in FIG. 2, the direction is perpendicular to the paper surface.

A signal obtained by reading the original image with the scanner 1 is subjected to various processes as described later, and then sent to the printer 2. The printer 2 performs binary recording according to the signal.

The printer 2 includes a laser writing unit 25, a photosensitive drum 3, a charging charger 24, a developing device 12, a transfer charger 14, a separation charger 15, a fixing device 23, and the like. The printer 2 has no particular difference from a general laser printer known in the related art, so only the operation will be briefly described.

The photosensitive drum 3 rotates clockwise in FIG. Then, the surface thereof is uniformly charged to a high potential by the bias of the charging charger 24. The charged surface is irradiated with laser light modulated by a binary signal corresponding to an image to be recorded. The laser beam repeatedly scans the photosensitive drum 3 in the main scanning direction by mechanical scanning. The potential of the charged surface of the photoconductor drum 3 changes when it is irradiated with laser light. Therefore, a change in the laser beam, that is, a potential distribution according to the image to be recorded is generated on the surface of the photosensitive drum 3. This potential distribution is the electrostatic latent image. When the portion on which the electrostatic latent image is formed passes through the developing device 12, toner adheres according to the potential, and the electrostatic latent image is developed into a toner image, that is, a visible image. This visible image is superimposed on the transfer paper fed from the paper feed cassette 4 or 5 to the photosensitive drum 3, and is transferred to the transfer paper by the bias of the transfer charger 14. The transfer paper on which the image has been transferred passes through the fixing device 23, and then the discharge tray 2
It is discharged to 2.

FIG. 1 shows the appearance of the operation panel of this digital copying machine. Referring to FIG. 1, this operation panel has a copy magnification key K5, a density key K6, and a density key K6 as in a general copying machine.
Interrupt key K7, numeric keypad KT, clear / stop key K
C, print start key KS, display DSP, etc. are provided. In this example, a copy mode designating unit is especially provided. The copy mode designating section has four mode keys K1, K2, K3 and K4, and a display lamp (light emitting diode display) L for displaying the current operation mode.
1, L2, L3 and L4 are provided.

The mode key K1 is a key for designating a character mode.
If you choose the text mode, the image is processed completely binary. That is, in reading an original image, a portion having a density lower than a certain threshold density is regarded as a white (non-recording) pixel, and the other portion is regarded as a recording pixel. Each read pixel and recorded pixel have a one-to-one correspondence. Therefore,
A high-quality copy image can be obtained for an image having high resolution and no halftone density such as characters.

The mode key K2 is a key for selecting the photo mode.
When the photographic mode is selected, the image is processed as including halftone information, and the density level information of the original image is also reflected on the copy image. However, in this example, since the printer 2 can perform only binary recording (recording / non-recording) in each recording pixel unit, a special halftone process is performed to convert a multi-level signal into a binary signal. As this type of halftone processing, a dither method, a density pattern method, a sub-matrix method, etc. are known, but in this example, the half-tone processing by the sub-matrix method is adopted.

In the photographic mode, a preferable copy image can be obtained for a multi-tone image such as a photograph, but the halftone processing reduces the resolution and is not suitable for reproducing a binary image such as characters. .

The mode key K3 is a key for selecting the automatic separation mode. In the automatic separation mode, it is automatically determined whether or not the original image includes halftone information based on the image signal read by the scanner 1, and the signal processing is binarized based on the determination result. To automatically perform halftone processing. When this mode is selected, for example, when a photograph containing halftone information and a character that does not contain halftone information are mixed in one document, the process is switched during reading, and halftone information is applied to the photograph. Performs processing, and performs binary processing on characters. Therefore, the photograph is reproduced on the copy in a form including halftone information, and the characters are recorded with high resolution.

The mode key K4 is a key for selecting the magic erase mode. In the magic erase mode, when the document image has a thick line or the like, a copy image is obtained in which only the peripheral portion of the line is left and the inside of the line disappears. Further, if there is a pattern filled with a thin felt-tip pen or the like, a copy image in which the pattern is erased can be obtained. Detailed operation will be described later.

FIG. 3 shows the configuration of the electric circuit of the digital copying machine shown in FIG. Referring to FIG. 3, the scanner 1 includes an image reading sensor 10, a scanning control unit 20, an amplifier 30, an A / D (analog / digital) converter 40, a halftone processing unit 50, a binarization processing unit 60, An area determination unit 70, an operation control unit 80, an output control unit 90, a motor driver MD, etc. are provided.

The scanning control unit 20 exchanges signals with the printer 2, performs main scanning control, sub-scanning control, and generates various timing signals. Various timing signals are generated so as to be synchronized with scanning timing. Key reading control and display control other than the copy mode designation on the operation panel shown in FIG. 1 are performed on the printer 2 side. Various status signals, print start signals, copy magnification signals, etc. are sent from the printer 2 to the scan controller 20. The scan controller 20 sends a scan synchronization signal, a status signal, etc. to the printer 2. Motor MT
Is driven to mechanically scan the scanner and perform sub-scanning.

The image reading sensor 10 includes a large number of reading cells, CCD shift registers, and the like, like a general CCD line sensor. When the scanning control unit 20 outputs the sub-scanning synchronization signal, the signals accumulated in many reading cells of the image reading sensor 10 are transferred to each bit of the CCD shift register at once. After that, the signal of the CCD shift register is shifted in synchronization with the main scanning pulse signal, and the image signal held in the register appears as a serial signal at its output terminal for each pixel (a in FIG. 3). : Hereinafter, the signal generated from the image signal is shown in parentheses).

The amplifier 30 performs amplification of the image signal (a), noise removal, and the like. The A / D converter 40 converts the analog image signal into 6
Convert to bit digital signal. Although not shown in the drawing, the digital signal obtained by the A / D converter 40 is subjected to various types of conventionally known image processing such as shading correction, background removal, and black and white conversion, and then, Bits, that is, 64 gradation digital image signals (b) are output.

The digital image signal (b) is applied to the halftone processing unit 50 and the binarization processing unit 60.

The halftone processing unit 50 is a circuit that converts the 6-bit digital image signal (b) into a binary signal (d) containing halftone information by the sub-matrix method. A circuit for performing halftone processing by the sub-matrix method is well known, and since no special circuit is used in this embodiment, a specific configuration and operation will be omitted. In addition to the sub-matrix method, halftone processing by a dither method or a density pattern method may be performed.

In the binarization processing unit 60, the input 6-bit digital image signal (b) is subjected to MTF correction, the correction result is compared with a predetermined fixed threshold level TH1, and the binary value corresponding to the magnitude of these values is used. The signal (e) is output. Therefore, the processing performed here is a simple binarization processing, and the signal (e) does not include the halftone density information of the original image.

In addition, the binarization processing unit 60 outputs the 6-bit digital image signal (C1) and the 1-bit binary image signal (C2) to the area determination unit 70. The image signal (C1) is an MTF-corrected signal and is not significantly different from the image signal (b) applied to the binarization processing unit 60. In addition, the signal (C
2) is different from the signal timing, except that the binarization processing unit 60
Is the same as the binary image signal (e) output by.

As will be described later, the area determination unit 70 is a circuit that determines whether or not the document image includes halftone information, and outputs a binary signal (f) corresponding to the determination result to the output control unit 90.

The operation control unit 80 controls the mode signals (g: specifically, g1, g2, g3, and g) corresponding to the operation of the mode keys K1 to K4.
4) is given to the output control unit 90. Further, the energization of the display lamps L1 to L4 is controlled according to the mode signal.

The output control unit 90 responds to the mode signal (g) given from the operation control unit 80 and the binary signal (f) given from the region determination unit 70, and outputs the binary image signal ( d), the binary image signal (e) output by the binarization processing unit 60 or the signal of a predetermined level (white level) is selectively output. This signal (h) is given to the printer 2 as a recording signal. The printer 2 modulates the laser light according to this binary signal and records.

FIG. 4 shows the configuration of the area determination unit 70 shown in FIG. Fourth
Referring to the drawing, the area determination unit 70 includes a first determination unit 71,
The second determination unit 72 and the OR gate 73 are included. First
A 6-bit image signal (C1) is applied to the determination unit 71, and a 1-bit binary image signal (C1) is applied to the second determination unit 72.
2) is applied. The logical sum (f) of the signal (1) output from the first determination unit 71 and the signal (r) output from the second determination unit 72 is output to the output of the region determination unit 70.

The first determination unit 71 includes a binarization circuit 110 and a Y delay circuit 12
0, X delay circuit 130 and AND circuit 140.

In this specification, the symbol x or X is used to indicate the main scanning direction of the scanner, and y is used to indicate the sub scanning direction.
Alternatively, the symbol Y is used. Also, the binary image signal "1"
Corresponds to the black pixel level, and “0” corresponds to the white pixel level.

Details of the configuration of the first determination unit 71 are shown in FIG. 5, and examples of signal waveforms and timings of the respective units are shown in FIGS. 6a and 6b.

Details of the first determination unit will be described with reference to FIG. The binarization circuit 110 includes a digital comparator 111, a pull-up circuit 112, and a switch circuit 113. The digital comparator 111 compares the value of the digital signal applied to the 6-bit input terminal A with the value of the digital signal applied to the other 6-bit input terminal B, and outputs the comparison result.

That is, if A ≧ B, the signal (j) becomes “1” (corresponding to the high level H: the same below), and if not, the signal (j) becomes “0” (corresponding to the low level L: the same below). Become.

Each switch of the switch circuit 113 is set so that the value of the input terminal B of the comparator 111 becomes a predetermined threshold value TH2. Although this threshold value TH2 can be changed, it is normally set so as to have a considerably low density level as shown in FIG. 6b. The threshold TH1 used by the binarization processing unit 60 is set to the central level (32) of the density gradation in this example.

In other words, the binarization circuit 110 determines the black level even for a pixel whose density is considerably lower than the normal black pixel determination level.

The Y delay circuit 120 is a circuit that processes the signal (j) output from the binarization circuit 110 and delays the signal timing by a predetermined number of pixels in the y direction, that is, the sub-scanning direction, and includes seven signals jn and k. Is output. In FIG. 5, signal jn
Represents a signal obtained by delaying the signal j by n pixels in the y direction.
The signal k is the same as the signal j3 with respect to the delay amount. y
By delaying the signal for each pixel in the direction, signals of a plurality of pixels adjacent to each other in the y direction can be extracted as a parallel signal. That is, this circuit can be regarded as a serial-parallel conversion circuit.

FIG. 6a shows the operation timing of the Y delay circuit 120. The operation will be described with reference to FIG. 6a. The input signal (j) is latched in the latch 121 by the clock pulse t2 output at the timing of each pixel in the x direction. That is, the signal (j) applied to the input terminal D1 of the latch 121 appears at its output terminal Q1 and its state is held. By the clock pulse t3, the states of the output terminals Q1 to Q6 of the latch 121 are stored in each bit of the RAM (read / write memory) 123 at the timing of each pixel in the x direction.

The memory address to be stored is specified by the address signal t1. The content of the address signal t1 is updated for each pixel in the x direction, and the same content (value) is set for pixels at the same position in the x direction. That is, the signal t1
Corresponds to the pixel position in the x-scan direction. In this example, since the number of pixels in the x direction is 4096, the signal t1 is a 12-bit parallel signal.

The stored contents of the RAM 123 are read out for each pixel in the x scanning direction by the clock pulse t3. The data to be read is the data previously stored at the position in the x direction at that time. Focusing on the connection between the data lines D1 to D6 of the RAM 123 and the latch 121, bits 1, 2, 3, 4, 5 and 6 of the data line of the RAM 123 are bits 2, 3 of the input terminal of the latch 121, respectively. 4,5
6 and 7 are connected in a state of being shifted by 1 bit.

Therefore, the signal (j) input at a certain timing is latched in the bit 1 of the latch 121 and stored in the bit 1 of the RAM 123 before the data of the next pixel is set in the latch 121. Then, it is read from bit 1 of the RAM 123 at a timing delayed by one pixel in the y direction,
It is applied to the bit 2 input terminal D2 of the latch 121.
This signal is latched in bit 2 of the latch 121 at the timing at which the pixel signal that appears at the x position with a delay of one pixel in the y direction is latched in bit 1 of the latch 121.

After that, by repeating this operation, the signal becomes latch 1
21 bits 3, 4, 5, 6 and 7 have timing y
Every time one pixel is advanced in the direction, the data is sequentially transferred. That is, when the signal is latched in bit 7 of the latch 121, each bit 6, 5, 4, 3, 2 and 1 of the latch 121 is
Are 1, 2, and more in the y direction than the signal of bit 7, respectively.
There are signals delayed by 3, 4, 5 and 6 pixels. As a result, at the output terminals Q1 to Q7 of the latch 121, signals of seven pixels adjacent to each other in the y direction at a predetermined x position are obtained at the same timing.

The latch 122 is for adjusting the timing of sending a signal to the circuit connected to the output of the Y delay circuit 120. Therefore, the signals j0 to j6 are almost the same as the signal output from the latch 121.

In FIG. 6a, symbols j1, j2, ... B1, B
2, B3 ... And A1, A2, A3 ... Represent the change of each signal for each pixel in the x direction.
Note that it is different from the signal output by 22.

The signal k output from the Y delay circuit 120 is the X delay circuit 13
Applied to zero. The X delay circuit 130 is composed of one shift register as shown in FIG. signal
(k) is applied to the serial data input terminal of the shift register. From the parallel data output terminals Q1 to Q7 of this shift register, signals (k1, k2, k3, k4, k5, k6 and k
7) is output. This shift register (130)
The data is shifted by one bit each time the clock pulse t4 that is output each time the scanning position in the x direction changes in units of pixels. For example, the signal k applied to this shift register at a certain timing is the next pixel timing (x
Direction) appears in bit 1 of the output terminal (k1), and bits 2, 3, 4, 5, 6 and 7 are generated each time the pixel timing changes.
Are sequentially transferred to.

That is, for example, when the signal of the pixel located at N in the pixel coordinate in the x direction appears as the signal (k7), each signal (k
6, k5, k4, k3, k2, k1) have the same pixel positions in the y direction as in (k7) and in the x direction are N + 1, N + 2, N + 3, N + 4, N + 5 and N + 6, respectively. That is, the signals (k1 to K7) are signals of seven pixels located at pixel positions adjacent to each other in the x direction, and these signals are obtained at the same timing. Therefore, the X delay circuit 130 can also be regarded as a serial-parallel conversion circuit for serial pixel signals.

Signals output from the Y delay circuit 120 (j0 to j6 and k1
~ K7) are applied to the AND circuit 140. The AND gate 141 outputs 1 when the signals (j0 to j6) are all 1, and outputs 0 otherwise. Therefore, the signal (j10) output from the AND gate 141 becomes 1 when the positions in the x direction are the same and seven pixels adjacent in the y direction are all at the black level (relative to TH2). This signal is output by the shift register 143 for a predetermined number of pixels (i
Pixel) and AND gate 1 as signal (j11)
44 is applied.

The AND gate 142 outputs 1 when the signals (k1 to k7) are all 1 and outputs 0 otherwise. Therefore, the signal (k10) output from the AND gate 142 is
Seven pixels that have the same position in the y direction and are adjacent to each other in the x direction have a value of 1 when they are all at the black level (relative to TH2).
The AND gate 144 outputs a logical product of the signal (J11) and the signal (k10), that is, the signal (l).

That is, with respect to the pixel of interest at that time, the first determination unit 71 has halftone information (l) when all 7 pixels in the x direction and 7 pixels around the pixel of interest are at the black level (for TH2). Is determined in 1). The shift register 143 is provided to shift the signal (j11) in the x direction with respect to the signal (j10) in order to adjust the timing of 7 pixels in the x direction and 7 pixels in the y direction.

That is, since the signals (j0 to j6) are at the same position as the signal (k) in the x direction, in order to obtain the signal (j11) at the x position corresponding to the signal (k4) corresponding to the central pixel in the x direction. Then, the signal (j10) is shifted by i pixels (4 pixels in this example) in the x direction. That is, when considering a minute pattern, since many of them are generally circular, it is preferable to arrange the target pixel at the center pixel of the pixel group forming the “+” pattern.

Please refer to FIG. 6b. It should be noted that only the x direction is shown in this figure for easy understanding. Since the digital image signal (C1) is 6 bits, it contains 64 levels of density gradation information. In this example, each part (C11, C12) of the signal (C1) shown in the figure represents a signal obtained by reading a halftone image such as a photograph, and (C13) reads a background (that is, white) image. Shows the signal obtained, (C14) shows the signal obtained by reading the characters written in relatively thick lines (that is, binary density pixels), (C15) shows the characters written in relatively thin lines Shows the signal obtained by reading, and (C16, C17) shows the signal obtained by reading the stain on the document.

In the binarization circuit 110, the level TH2 having a low density is set to the threshold level to perform the binarization of the signal. Therefore, the obtained image signal (j) has a very low image density. Even in this case, the portion where the image exists corresponds to all black pixels. On the other hand, in the signal (e) output from the binarization processing unit 60 in which the intermediate level 32 is set as the threshold value, in the halftone image, a portion having a low density corresponds to a white pixel, and Only the dark areas correspond to black pixels.

The signal (k10) becomes 1 only when black of the image signal appears continuously in the x direction in seven pixels, that is, when the pattern has a size larger than a predetermined value. Therefore, each image signal portion (C11, C12, C
14), the signal (k10) becomes 1, but the other parts (C13, C
It becomes 0 for 15, C16, C17). Normally, this signal (k1
0), the halftone processed signal (d) and the binarized signal (e) are selected, so that the signals (h) shown in FIG. 6b are indicated by A, B and C. The part corresponds to the halftone processed signal (d), and the other parts D, E and F correspond to the binarized signal (e). Where C, D and E
Is a portion of the same character, but D and E (6 pixels in the x direction) corresponding to the contour portion do not reach the 7 pixels which is the determination condition of the halftone information, and are therefore binarized. Each part (C16, C17) of the image signal (C1) has a threshold level T
Since H1 is binarized, stains on the document are not output as a copy image.

The second determination unit 72 will be described with reference to FIG. The second determination unit 72 is simply a circuit that determines the presence or absence of a halftone dot pattern. The signal C2 processed by this circuit is
The signal C1 is simply binarized with respect to the fixed threshold level TH1.
It may be considered that it is the same as the signal (e) output by the binarization processing unit 60.

The second determination section 72 includes an XY delay circuit 150, a mesh detection circuit 160, a first area detection circuit 170, a second area detection circuit 180 and a third area detection circuit 190. The XY delay circuit 150 processes the signal (C2) and outputs the signal (mij), and the mesh detection circuit 160 outputs the signal (mij).
To output a signal (n), and the first area detection circuit 1
70 processes the signal (n) and outputs the signal (p),
The area detection circuit 180 processes the signal (p) and outputs the signal (q), and the third area detection circuit 190 processes the signal (q) and outputs the signal (r).

FIG. 7a shows the configuration of the XY delay circuit 150. Referring to FIG. 7a, this circuit comprises a Y delay circuit 151 and an X delay circuit. The configuration of the Y delay circuit 151 is the same as that of the Y delay circuit 120 shown in FIG. However, since the signal corresponding to the signal (k) is unnecessary, only the seven outputs of the latch 122 are used as the output terminals. That is, the signal output from the Y delay circuit 120 (m11 to m17)
Corresponds to seven pixels having the same x direction and being adjacent to each other in the y direction.

The X delay circuit includes six 7-bit latches 152, 153.
154, 155, 156 and 157. The latch 152 latches the signals (m11 to m17) output from the Y delay circuit, and latches 153, 154, 155, 156 and 15
7 are latches 152, 153, 154 and 155, respectively.
And signals output by 156 (m21 to m27), (m31 to m37), (m
41 to m47), (m51 to m57) and (m61 to m67) are latched in synchronization with the clock pulse t4. Therefore, each signal (m21, m31, m
41, m51, m61 and m71) are signals obtained by delaying the signal (m11) by 1, 2, 3, 4, 5 and 6 pixels in the x direction, respectively.

That is, the XY delay circuits 150 are adjacent to each other,
All signals mij of each pixel of a 7 × 7 pixel matrix composed of 7 pixels in the x direction and 7 pixels in the y direction are output at the same timing.

FIG. 7b shows a specific structure of the mesh detection circuit 160. Referring to FIG. 7b, this mesh detection circuit 1
Reference numeral 60 includes a first mesh detection circuit MS1, a second mesh detection circuit MS2, a third mesh detection circuit MS3, a fourth mesh detection circuit MS4 and a data selector 168. The signal mij output from the XY delay circuit 150 is applied to each of the mesh detection circuits MS1 to MS4.

The fourth mesh detection circuit MS4 is composed of gates 161, 162, 163, 164, 165, 166 and 167, as shown in the figure. In the figure, mij indicated by a symbol with an overline indicates a signal obtained by inverting the logic of the signal indicated by a symbol without the overline. Therefore,
Although not shown, many inverters are inserted between the output terminal of the XY delay circuit 150 and the input terminal of the mesh detection circuit 160. For the sake of convenience, underlines are used instead of overlines in this specification.

Signals m44, m24, m33, are input to the nine input terminals of the gate 161.
m35, m42, m46, m53, m55 and m64 are applied, and gate 162
Signals m44, m24, m33, m35, m42, m46, m to the nine input terminals of
53, m55 and m64 are applied, and signals m44, m13, m14, m15, m22, m26, m31, m37, m4 are applied to 17 input terminals of the gate 163.
1, m47, m51, m57, m62, m66, m73, m74 and m75 are applied, and signals m44, m13, m14,
m15, m22, m26, m31, m37, m41, m47, m51, m57, m62, m66, m73, m7
4 and m75 are applied.

Before describing the operation of the mesh detection circuit 160, consider halftone printing. Fig. 8 shows three types of density (reflectance of 10% and 30%, printed with halftone dots at the same halftone pitch.
And 50%) of the image is shown enlarged to the extent that halftone dots can be easily identified. The hatched portion is the printed (black) portion, and the other portions are the background (white).
Although not shown, when the concentration is 70% and 90%,
When the densities are 10% and 30%, black / white is reversed.

It can be seen from FIG. 8 that when the density is 50%, there is a portion where adjacent dots are in contact with each other and a portion where they are separated from each other. Further, in reality, the inclination between the arrangement direction of the halftone dots and the scanning directions x and y of the scanner is not constant due to the relationship between the scanner and the original when reading the original. In addition, the diameter of the recording dot also changes.

The presence of such halftone dots needs to be determined by the second determination unit 72.

Referring to FIG. 8, in any case, it can be seen that in the halftone-printed original image, there are black dots (dots) on a white background or white dots (dots) on a black background. Therefore, the mesh detection circuit 160 detects, for each pixel of interest, whether or not it corresponds to these dots.

In the fourth mesh detection circuit MS4, 7 × shown in FIG.
The central pixel of the 7-pixel matrix, that is, the target pixel M44 (pixel corresponding to the signal m44) and the symbol ◯ or Δ surrounding it.
From the relationship with the pixel shown in, whether the target pixel M44 is a black dot (there is a black pixel in the white pixel group) or a white dot (there is a white pixel in the black pixel group). Detect whether or not. That is, the gate 161 outputs 0 if the pixel of interest M44 is 1 (black pixel) and all the pixels indicated by the symbol are 0 (white pixel), that is, a signal indicating that there is a black dot, and the gate 162 outputs 0 of the pixel of interest M44. If all the pixels indicated by the symbol ◯ are 0, that is, a signal indicating that there is a white dot is output. If the target pixel M44 is 1 and the pixels indicated by the symbol Δ are 0, 0, that is, a signal indicating that there is a black dot. The gate 166 outputs 0 if the target pixel M44 is 0 and all the pixels indicated by the symbol Δ are 1, that is, a signal indicating that there is a white dot.

Any one of the gates 161, 162, 163 and 166
1 outputs a signal indicating that a black dot or a white dot exists, that is, a signal indicating that a dot exists, 0 otherwise.
That is, the signal indicating that there is no dot is the fourth mesh detection circuit M
It is output from S4 as n4.

Here, with respect to the target pixel M44, two types of array patterns of the pixel group at the position of the symbol ◯ and the pixel group at the position of the symbol Δ are referred to because of changes in the halftone dot pitch and the dot diameter. This is also for the purpose of increasing the detection accuracy.

First mesh detection circuit MS1, second mesh detection circuit M
S2 and the third mesh detection circuit MS3 have the same configuration as the fourth mesh detection circuit MS4. However, the signals mij and mij respectively applied to the input terminals are different from those of MS4. That is, each mesh detection circuit MS1 to MS
In No. 4, the positions of the pixels used to determine the presence / absence of dots are different. This change in condition is set in advance for each copy magnification, in particular considering the change in dot diameter due to the change in copy magnification.

Referring to FIG. 7b, the copy magnification signal line is connected to the selection terminal S of the data selector 168. Therefore, when the copy magnification changes, the signals n1, n2, output from the mesh detection circuits MS1 to MS4 are correspondingly changed.
One of n3 and n4 is selectively output from the data selector 168 as the signal n. That is, in this embodiment, the dot detection condition is automatically changed using the copy magnification as a parameter.

FIG. 10a shows an example of the positional relationship between dots and pixels when reading a halftone image, and FIG. 10b shows an array of signals obtained by binarizing each pixel signal of FIG. 10a with a threshold value TH1.
In these figures, the pixel pitch is 1/16 (mm
/ Pixel), and the halftone dot pitch is 1/5 (mm / pixel). Further, in FIGS. 10a and 10b, the x and y coordinate values correspond to each other.

In this example, looking at the pixel at coordinates (15,4), the pixel of interest is 1 and all 9 pixels indicated by the symbol ◯ in FIG. 9 are 0. It is judged to be present.

Basically, as described above, the signal n indicating the presence / absence of a halftone dot is obtained at the output of the mesh detection circuit 160. However, since the positional relationship between the pixel and the halftone dot changes variously, the process described later is further performed.

FIG. 7c shows a specific configuration of the first area detection circuit 170. In brief, the first area detection circuit 170 uses a predetermined pixel matrix (referred to as a first area) made up of w pixels in the x direction (for example, 8 pixels) and w pixels in the y direction as shown in FIG. Assuming that 1 in this first area
Determine if there are more than one dot. Signal p
Is 1 when the dot exists and 0 when the dot does not exist.

Referring to FIG. 7c, this circuit 170 comprises a read-only memory ROM1, counters CN1, CN2, flip-flops FF1, FF2, read / write memory RAM1, gates G1, G2, G3, G4, G5, G6, an inverter IV.
1 and IV2.

The timing of operation of the circuit of Figure 7c is shown in Figure 12a. The counter CN1 counts the clock pulse t4,
Count up for each pixel in the x direction. When the count value reaches 15, the carry terminal CY becomes high level H. Since a signal obtained by inverting this signal is applied to the preset terminal LD, when the next clock pulse appears, the input terminal D1
The data of D4 are set in the counter. In FIG. 12a, the preset data is 8.

Therefore, the counter CN1 operates as an N-ary counter that counts up each time the clock pulse t4 appears. The value of N can be arbitrarily set in the range of 1 to 16 depending on the value applied to the data input terminals D1 to D4. On the signal line Qx, a signal which becomes a low level L appears for every N clock pulses t4 during one period thereof.

On the other hand, the signal n output for each pixel in the x direction is applied to the flip-flop FF1 via the OR gate G1 and t
The data is latched by FF1 in synchronization with 4th bit. When the signal line Qx is at the high level H, the signal latched by the flip-flop FF1 is applied from its output terminal Q to one input terminal of the OR gate G1 via the AND gate G2.

Therefore, when the signal n becomes 1, the output terminal Q of the flip-flop FF1 maintains the state of 1 (H) until the signal line Qx becomes the low level L. That is, when the counter CN1 is set to the octal counter, the twelfth counter
After a signal n for a certain first pixel appears in the Q of FF1 as a signal O1 as shown in FIG. a, a logical sum of the signal O1 and the next signal n appears in the Q of FF1 as a signal O2. By repeating, when the signal line Qx becomes low level, the result of calculating the logical sum of all signals n of 8 pixels continuous in the x direction, that is, the signal O7 is F
Obtained in Q of F1.

When signal O7 is present, the next clock pulse t4
Signal arrives, the signal is latched in the flip-flop FF2, and the latched signal is output as the signal p. The signal output from the FF2 is the clock pulse t
The data is stored in the read / write memory RAM 1 in synchronism with 5.
The signal t6 designating the address of the memory RAM1 is updated every N pixels in the x direction to a value according to the position in the x direction. The signal t6 has nothing to do with the pixel position in the y direction. Therefore, the memory RAM 1 stores data for one line in the x direction.

At the timing of the clock pulse t41, the memory R
Previous line to AM1 (position where relative coordinate in the y direction is -1)
The data stored in is read out and it is AND gate G
It is applied to one of the input terminals of the OR gate G4 via No.5.

On the other hand, the counter CN2 operates as an N-ary counter that counts up each time the clock pulse t7 appears. The clock pulse t7 is a sub-scanning synchronization pulse output each time the pixel position in the y direction changes. Other actions are
This is the same as the case of the counter CN1.

Therefore, the signal line Qy is normally at the high level H and goes to the low level L once every N pixels in the y direction. If the high level H is applied to the data terminal D of the flip-flop FF2 even once while the signal line Qy is at the high level, the logical sum of the high level H and the input signal is held by the FF1 and the memory RAM1. Reach level H.

That is, when the signal line Qy becomes the low level L, the area F (N line) for N pixels continuous in the y direction is F
The result of calculating the logical sum of all signals (for example, O7) output by F1 is output as the signal p. That is, N ×
For a predetermined pixel matrix having an N (for example, 8 × 8) array, that is, for each first area, if at least one pixel has a signal n of 1, the signal p becomes 1, At other times, p becomes 0. This signal p indicates the presence / absence of dots in the first area detection circuit, that is, the presence / absence of dots.

On the other hand, the data terminals D1 to D4 of the counter CN1 are connected to the data terminals D5 to D8 of the read-only memory ROM1, and the data terminals D1 to D4 of the counter CN2 are the memory R.
It is connected to the data terminals D1 to D4 of the OM1. A copy magnification signal is applied to the address terminal of the memory ROM1. The read-only memory ROM1 stores in advance information about the size of the first area associated with each copy magnification.

For example, in this example, when the copy magnification is 1.0, the size of the first area is set to 8 × 8 pixels.
8 is output to the 4-bit output terminals D1 to D4 of the group, and 8 is also output to the 4-bit output terminals D5 to D8 of the second group. In this case, the counters CN1 and CN2
Is set at the time of presetting, 8, 9, 10, 1
Since it counts 1, 12, 13, 14, 15, 8, 9, 10, ..., It operates as an octal counter. When the copy magnifications are different, the count ranges of the counters CN1 and CN2 are changed, which changes the size of the first area (the number of pixels).

FIG. 7d shows the configurations of the second area detection circuit 180 and the third area detection circuit 190. First, the second area detection circuit 180 will be described.

Generally speaking, in the second area detection circuit 180,
As shown in the figure, two first areas continuous with each other in the x direction and two first areas continuous with each other in the y direction
Assuming a second area composed of four first areas consisting of areas and whether or not there are three or more first areas in which dots are detected (signal p is 1) in this second area. To determine. If there are three or more dot-detected first areas, it indicates that the signal q is set to 1 for a predetermined first area in the second area, and a halftone dot is detected.

The reason why such second area detection processing is performed is to prevent the following erroneous detection. That is, if there is a dot loss due to the document side due to a printing error or the like or a dot detection error due to the copying machine side due to a reading error or the like, at the stage of the signal p, the halftone dot area is actually shaded. It may be judged without a point. In the case of not a halftone image, at the stage of the signal p, for example, a part of a character or dirt on the background may be detected as one dot, and it may be erroneously determined as a halftone area.

The operation timing of the second area detection circuit 180 is 12b
Shown in the figure. This will be described with reference to FIGS. 7d and 12b.
181 is a data selector, 182 and 183 are latches,
Reference numeral 184 is a read / write memory. Data selector 18
1, the latch 182 and the read / write memory 184 are circuits that delay the signal p output for each first area in the y direction by the pixels corresponding to the first area. The output terminals Q1 and Q2 of the latch 182 are connected to the output terminals Q1 and Q2. , 2 adjacent to each other in the y direction
The signals of the two first areas are obtained at the same timing.

The latch 183 outputs the signal output from the latch 182 to the first
This is a circuit for delaying the pixels corresponding to the area in the x direction, and the signals output from the latch 182 to the Q1 and Q2 are output to the output terminals Q1 and Q2 of the latch 183 for one first area and in the x direction. The delayed signal appears. Therefore, the signals p for the output terminals Q1 and Q2 of the latch 182 and the output terminals Q1 and Q2 of the latch 183 are obtained at the same timing in the four first areas included in the second area.

That is, the signals p of the first areas E1, E2, E3 and E4 in FIG. 11 are obtained in 183-Q1, 182-Q1, 183-Q2 and 182-Q2, respectively. These four signals are the gate G1
The signal q is generated by processing at 1, G12, G13, G14 and G15. If three or more of the four signals are 1, the signal q is 1.
become.

For example, in FIG. 11, E1, E2, E3 and E4
If three or more p's are 1, the signal q output to the first area E4 becomes 1. In FIG. 12b, p0, p1, p3, p4, ... Show signals p output for each first area, and q0, q1, ... Show signals q output for each first area. , P0-1, p1-
1, p2-1, ... are p0, p1, p2, ...
Shows a signal delayed by the number of pixels in one first area in the y direction. For example, q1 is p1-1, p1, p2-
It is determined by the four signals 1 and p2.

Next, the third area detection circuit 190 will be described. Roughly speaking, in the third area detection circuit 190, as shown in FIG. 11, four first areas continuous in the x direction are assumed to be the third areas, and at least one of the third areas is a mesh. If there is a dot, the third area is determined as a halftone dot area, and the signal r is set to 1.

The reason why the third area detection process is performed is to prevent moire. That is, due to the scanning method and the structure, the risk of moire is predominantly higher in the main scanning direction than in the sub scanning direction. In the sub scanning direction, there is no moire or it is inconspicuous. In the main scanning direction, generally, when the reading resolution is 16 pixels / mm, moire with a pitch of about 1 to 3 mm occurs depending on the halftone dot pitch and the relative angle between the original and scanning. If the amplitude of the read signal becomes small due to the moire, the accuracy of dot detection is reduced, and an error may occur in dot detection. Therefore, this third area detection process is unnecessary if there is no risk of moire.

In this embodiment, the number of pixels in the x direction in the third area is 3.
2 and the reading resolution is 16 pixels / mm, the third
The area pitch is 2 mm. Referring to FIG. 7d, the third area detection circuit 190 includes a shift register 191 and an OR gate 192. Shift register 191
Shifts the signal q for each x-direction pixel number in the first area in synchronization with the clock pulse t41.

When the signal q becomes 1 at least once among the four first areas continuous in the x direction, the signal r becomes 1 for all the first areas forming the third area including the first area. Set. That is, in FIG. 11, when the signal q becomes 1 in the first area E1 of the third areas, the signal r is also transmitted to the other first areas E2, E5, and E6 forming the third area. Becomes 1.

Next, the operation control unit 80 and the output control unit 90 shown in FIG. 3 will be described. FIG. 13 shows the operation control unit 80 and the output control unit 9.
The structure of 0 is shown.

The operation control unit 80 uses the mode keys K1, K2, K3, K
4, signal processing circuit 81, pull-up circuit (resistor) 8
2, a display driver 83 and display lamps L1, L2, L3 and L4. The signal processing circuit 81 reads the state of the mode keys K1 to K4 and outputs the mode signals g1, g2, g.
3 and g4 are output. That is, when the mode key K1 is turned on, the respective mode signals g1, g2, g3 and g4 become 1, 0, 0 and 0 respectively, and when the mode key K2 is turned on, the respective mode signals g1, g2, g3 and g4 are changed. , 0, 1, 0 and 0 respectively, and when the mode key K3 is turned on, the mode signals g1, g2, g3 and g4 become 0, 0, 1 and 0 respectively, and when the mode key K4 is turned on, each mode The signals g1, g2, g3 and g4 become 0, 0, 0 and 1, respectively. When no mode key is pressed, each mode signal maintains its previous state. In the initial state, each mode signal g1, g2, g3 and g4
Becomes 1, 0, 0 and 0, respectively.

The display driver 83 activates the display lamps L1, L2, L3 and L4 according to the state of the mode signal. That is, the mode signals g1, g2, g3 and g4 are respectively 1,
At 0, 0 and 0, the indicator lamp L1 is energized to
1, 0 and 0 energize the indicator lamp L2 to 0,
0, 1 and 0 energize the indicator lamp L3,
When it is 0, 0 and 1, the display lamp L4 is activated.

Mode signals g1, g2, g3 output by the operation control unit 80
And g4 are applied to the output controller 90.

Next, the output control unit 90 shown in FIG. 13 will be described. The output control unit 90 includes data selectors 91 and 92 and OR gates 93 and 94.

The data selectors 91 and 92 have selection control terminals A and B, respectively.
Is 0,0, the input terminal C0 is selected, the input terminal C1 is selected as 1,0, the input terminal C2 is selected as 0,1, and the input terminal C3 is selected as 1,1. The signal applied to the input terminal is output to the output terminal Y. At the input terminals C0, C1, C2, and C3 of the data selector 91, a signal e, a signal e, a signal d, and a fixed level L, respectively.
(0) is applied. Input terminal C of the data selector 92
The signals e and d are applied to 1 and C2, respectively, and the input terminals C0 and C3 of the data selector 92 are
The signal selected by the data selector 91 is applied. Therefore, the content of the signal h output by the output control unit 90 is as follows.
It looks like the table.

In other words, if the character mode is specified by pressing the mode key K1, the signal (e) obtained by simply binarizing the image data with the fixed threshold value TH1 is used as the image data regardless of whether the original image is halftone. If the photograph mode is designated by pressing the mode key K2, the binary signal (d) obtained by performing halftone processing on the image data by the sub-matrix method will produce an image. It is sent to the printer as data.

When the automatic separation mode is designated by pressing the mode key K3, the image signal is selected according to the result of determination as to whether or not the original image includes halftone information, that is, the signal (f). The halftone processed signal (d) is selected and output to the printer, and for the binary image, the simple binarized signal (e) is selected and output to the printer. It should be noted that the halftone-printed image, even if it is a character or the like, is determined to have halftone information as described above and is halftone processed.

When the magic erase mode is designated by pressing the mode key K4, a signal is selected according to the result of determination as to whether or not the original image contains halftone information, that is, the signal (f). The white pixel level signal is selected and output to the printer, and if there is no halftone information, the simple binarized signal (e) is selected and output to the printer.

Here, the operation of the magic erase mode will be described in an easy-to-understand manner.

In the magic erase mode, in the area determined to have halftone information, all the pixels are replaced with a signal (low level L) corresponding to a white pixel and output to the printer. That is, all the images in the halftone area are erased. In the area determined to have no halftone information, a signal subjected to simple binarization processing is output to the printer.

In the actual copy operation, the following is realized in this magic erase mode. Here, a character string written in a relatively thin line as shown in FIG. 14a.
It is assumed that an image including "ABC", "pqr", "XYZ" and a character "R" written in a thick line exists as a manuscript. For example "p
If you want to delete the character part of "qr",
All you have to do is to paint with a felt-tip pen or the like that has a relatively low density. The character string "pqr" is a binary image, but when filled, the space between the lines is colored, and the entire region is regarded as one relatively large halftone region. This is determined by the first determination unit 71 included in the area determination unit 70. That is, in the determination unit 71, if the density of all areas of a predetermined size or more (7 × 7 pixel matrix) has the density of the threshold value TH2 or more as described above, the area is regarded as a halftone area.

In the area regarded as the halftone area, white pixels are recorded (non-recorded) regardless of the content of the original image (the character "pqr" in this case) and its density. The mark filled with it is erased. In this case, the other "ABC" and "XYZ" characters are processed as a binary image and appear on the copy image (see Figure 14b).

On the other hand, with respect to the character "R" written with a thick line, in the magic erase mode, the part other than the outline part is erased even if no special filling or the like is performed. That is, since an area having a size equal to or larger than a predetermined size is determined to be a halftone area, a portion written with a thick line is regarded as a halftone area and erased as described above. However, regarding the outline portion of the thick line, that is, the portion having a width of up to 7 pixels in the x direction or the y direction from each pixel located at the outermost side of the line in the pixel group corresponding to the thick line, Judged as a binary area. The result of binarization processing with the threshold value TH1 is output as an image signal to the portion determined as the binary area. As a result, only the outline of the line appears black on the copy (see FIG. 14b). That is, in the magic erase mode, all the characters written with thick lines are converted into so-called blank characters (or patterns).

Even when the area is filled with a thin felt-tip pen as described above, the contour portion of the area is processed as a binary area. However, when the density is lower than the threshold level TH1, the binarized result is a white pixel. That is, the outline can be erased by using a writing instrument having a low density for filling.

Further, for example, if there are characters or the like written from the beginning using a felt-tip pen or the like, they are all erased.

Here, the features of the blank copy obtained by this embodiment will be described. The white copy obtained by this embodiment is not limited to characters, but includes symbols, lines, figures, pictures, etc.
Any pattern can be processed as long as it has a thickness of a predetermined value or more. Further, in this embodiment, the outline portion left by the blank is recorded by the binarized image signal and the width thereof is constant, so that a sharp image is obtained without blurring.

Although a method for obtaining a blank copy of this kind has been proposed in the past, in that case, an optically or electrically, logically or individually, a blurred image and a sharp image are obtained, respectively. Since the result is obtained by the exclusive OR of the above, inconveniences such as occurrence of blurring, rounded corners, thick image, and crushing of thin portion in the outline pattern cannot be avoided.

In addition, the image signal is set to 2 by the two threshold levels of high and low.
A method of obtaining two kinds of binarized signals and obtaining a result by exclusive OR of them has also been proposed, but even in that case, there are inconveniences such as uneven line thicknesses and thick images. There is.

Furthermore, in the above two conventional methods, since the exclusive OR is used, a thin line or a character composed thereof,
Whitening processing is also performed on all figures and the like, and in the whitened image, the line becomes thicker than the original. That is, the conventional whitening process is close to the edging process.

On the other hand, in the above-described embodiment, the whitening process is performed only on the image having the thickness equal to or larger than the predetermined value, and thus the thin line portion which does not require the whitening process is recorded as the original. Further, since the outline portion of the original image remains as a blank copy, the size of the pattern does not change. Further, there is no phenomenon that the image is blurred or the corners of the pattern are rounded. The line thickness of the pattern obtained by whitening can be arbitrarily changed by changing the configuration (the number of pixels) of the pixels processed by the first determination unit 71 in this embodiment.

A modified example of the mesh detection circuit and the first area detection circuit is shown in FIG. 15a, and the operation timing of the first area detection circuit 170B is shown in FIG. 15b. A description will be given with reference to each drawing. The mesh detection circuit 160B has the same configuration as the fourth mesh detection circuit MS4 shown in FIG. 7b.

In the first area detection circuit 170B, the circuit that generates the signal Qx is changed to the gate 171, and the circuit that generates the signal Qy is changed to the gate 172. To the three input terminals of the gate 171, the lower 3 bits Q _x0 , Q _x1 and Q _{x2 of the} signal indicating the position of the pixel unit in the x direction are applied, and the gate 17
The lower 3 bits Q _y0 , Q _y1 and Q _{y2 of the} signal indicating the position of the pixel unit in the y direction are applied to the two input terminals 2. Therefore, the signal Qx is 1 for every 8 pixels that are continuous in the x direction.
The level becomes low at a ratio of pixels, and becomes high at other periods. Similarly, the signal Qy has a low level L at a rate of 1 pixel out of every 8 pixels continuous in the y direction, and has a high level H during the other periods.

Therefore, in this example, the detection condition of the mesh detection circuit is fixed, and the size of the first area is fixed to 8 × 8 pixels.

In the above embodiment, the operation mode is not changed unless the designation is changed by the mode keys K1 to K4, but the mode can be arbitrarily programmed for each scanning position of the document by using the ten keys or the like. Then, the control device may automatically change the mode for each scanning position while reading the document.

Further, in the embodiment, in the magic erase mode, the determined portion is deleted in the halftone area and the determined portion is recorded in the binary image area. On the contrary, only the determined portion is recorded in the halftone area. It may be configured. In that case, in the portion determined as the halftone region, the signal subjected to the simple binarization process may be output instead of the signal subjected to the halftone process. By doing so, the portion painted with a felt-tip pen or the like does not appear on the copy. According to this, only the painted portion can be selectively copied. This kind of configuration change can be dealt with only by changing the connection between each input terminal and each signal line of the data selector 91 shown in FIG.

[Effect] As described above, according to the present invention, it is determined whether each area of the original image is a halftone image and the halftone processing and the binarization processing are automatically switched. Even for a document in which binary images such as characters are mixed, both images of photographs and characters can be clearly copied.

Further, in particular, since the presence or absence of the halftone image is detected and the halftone processing is performed on the halftone image, it is possible to prevent the occurrence of moire.

[Brief description of drawings]

FIG. 1 is a plan view showing an operation panel of one type of copying machine embodying the present invention. FIG. 2 is a front view showing a mechanical portion of a copying machine including the operation panel of FIG. FIG. 3 is a block diagram showing an electric circuit of the copying machine shown in FIG. FIG. 4 is a block diagram showing the area determination unit in FIG. FIG. 5 is an electric circuit diagram showing the first determination unit 71 of FIG. 6a and 6b are timing charts showing the operation of the circuit of FIG. 7a, 7b, 7c, and 7d are electrical circuit diagrams showing the configuration of the second determination section 72 shown in FIG. FIG. 8 is an enlarged plan view showing an image halftone-printed with three kinds of densities. FIG. 9 is a plan view showing an array of pixels used by the mesh detection circuit 160 to determine the presence / absence of dots. FIG. 10a is a plan view showing a part of a halftone dot printed image,
FIG. 10b is a plan view showing a binary signal obtained by reading the image of FIG. 10a. FIG. 11 shows the first area assumed by the first determination unit 72,
It is a top view which shows the structure of a 2nd area and a 3rd area. 12a and 12b are timing charts showing the operations of the first area detection circuit 170 and the second area detection circuit 180, respectively. FIG. 13 is an electric circuit diagram showing the configurations of the operation control unit 80 and the output control unit 90. FIG. 14a is a plan view showing an example of a document image, and FIG. 14b is a plan view showing a copy image obtained from the document shown in FIG. 14a. FIG. 15a is a block diagram showing a modification of the mesh detection circuit and the first area detection circuit, and FIG. 15b is a timing chart showing the operation of the first area detection circuit of FIG. 15a. 1: Scanner 2: Printer (recording means) 3: Photosensitive drum 10: Image reading sensor (image reading means) 40: A / D converter 50: Halftone processing section (halftone processing means) 60: Binarization processing Unit (binarization processing unit) 70: Region determination unit (region determination unit) 71: First determination unit 72: Second determination unit 80: Operation control unit 90: Output control unit (control unit) 110: Binarization circuit , 120: Y delay circuit 130: X delay circuit, 140: AND circuit 150: XY delay circuit 160: Mesh detection circuit 170: First area detection circuit 180: Second area detection circuit 190: Third area detection circuit K1, K2, K3, K4: Mode key (operation mode specification means)

Claims (7)

[Claims] 1. An image reading unit which scans an original image and outputs an electric signal corresponding to the image density for each minute region of the image; an electric signal output by the image reading unit is processed, and a level of the signal is processed. Halftone processing means for outputting a binary signal containing halftone information according to the following: an electric signal output by the image reading means is processed, the level of the signal is compared with a predetermined fixed reference level, and their magnitude relation A binarization processing means for outputting a binary signal according to the above; serial-parallel conversion means for simultaneously outputting signals of a plurality of pixels adjacent to each other in the main scanning direction and the sub-scanning direction of the image reading means, the serial-parallel conversion Processing a plurality of signals output by the means, processing the signals output by the pixel detection means for determining whether or not the pixel of interest and the surrounding pixels in the signal of each pixel have a dot pattern arrangement; Multiple pixels A first area detecting unit that determines the presence or absence or the number of pixels that have detected a halftone dot pattern in the first area that includes the first area detecting unit that processes a signal output from the first area detecting unit; A halftone dot detection unit having a second region detection unit for determining the presence / absence of a halftone dot pattern for each second region formed of a plurality of sets is provided; an original image is processed by processing an electric signal output from the image reading unit. Area determination means for determining whether halftone information is included, and if the arrangement of black level pixels or white level pixels of the original image is a halftone dot, area determination means; Recording means for performing binary recording on a predetermined recording medium; and, when the area determining means determines that halftone information is present, a signal output from the halftone processing means is applied to the recording means, and the area determining means If it determines that there is no halftone information, A digital copying apparatus comprising: a control unit that outputs a signal output by the binarization processing unit to the recording unit. 2. The digital copying apparatus according to claim 1, wherein the second area is a plurality of first areas arranged in the main scanning direction and the sub scanning direction of the image reading means. . 3. The second area detecting means, when the number of the first areas determined to have a halftone dot pattern is a predetermined number or more among a plurality of first areas forming one second area. Outputting a signal indicating the presence of a dot pattern
The digital copying machine according to the item (1). 4. The halftone dot detecting means processes a signal output from the second area detecting means, and the presence or absence of a halftone dot pattern for each third area which is a set of a plurality of the first areas. A third aspect of the present invention is provided with a third area detecting means for determining
The digital copying machine according to the item (1). 5. The digital copying apparatus according to claim 4, wherein the third area is a plurality of first areas arranged in the main scanning direction of the image reading means. 6. The third area detecting means, when the number of the first areas determined to have a halftone dot pattern is a predetermined number or more among a plurality of first areas forming one third area, The digital copying apparatus according to claim (4), which outputs a signal indicating the presence of a dot pattern. 7. The area reference means sets a second reference in which the level of the electric signal output by the image reading means is set to a predetermined level corresponding to a density level lower than the reference level of the binarization processing means. When a binary signal is obtained by comparing with the level, and the binary signal indicates the black corresponding level of the original image, the predetermined number or more consecutive pixels appear in the main scanning direction and the sub scanning direction of the image reading unit. Claims (1), (2), further comprising size determining means for determining whether there is halftone information
The digital copying apparatus of paragraph (3), paragraph (4), paragraph (5), or paragraph (6).