JPH0635847A - Command reception system for scsi protocol control lsi - Google Patents

Abstract

PURPOSE:To provide a command reception system for SCSI protocol control LSI which can reduce the CPU program load of a device and improve the system efficiency. CONSTITUTION:When the message sent from an initiator via an SCSI bus is received together with the command of an LSI containing a buffer storing the commands, the buffer stores plural pairs of messages and commands sent from the initiator within the storage capacity of the buffer (St.1-St.20). The SCSI bus is disconnected while no message nor command is received. Then, an interruption is produced to a CPU when the capacity of the buffer is filled with the pairs of messages and commands. Therefore, the program burden on the CPU is reduced and the SCSI bus is disconnected by the original action of the LSI (St.19) when the command reception is finished. Thus, the bus occupying time is shortened.

Description

Detailed Description of the Invention

[0001]

The present invention relates to SCSI (Small Comp
computer system interface) LSI that controls the protocol
In particular, the command receiving system is configured to reduce the load on the CPU.

[0002]

2. Description of the Related Art SCSI is an interface standard for connecting an initiator such as a personal computer or a host computer to a terminal device such as a disk device, and its details are specified by JIS.

FIG. 6 shows the whole system connected by this SCSI, and a plurality of initiators 11,
12, 13 and the terminals 21 to 25 connected to the initiator by the SCSI bus 8, and a plurality of local units (LUs) such as disk drives connected to the terminals.
N) 31, 32, 33, and the terminal devices 21 to 25
Includes an LSI for controlling the SCSI protocol, and a CPU that decodes commands and messages from the initiators 11 to 13 and executes processing according to them.

The initiator 11 is a selected terminal device.
A command for instructing write (READ) or read (WRITE) of data, a message for specifying the LUN 31 to be operated, or the like is sent to the 24 via the SCSI bus 8. These commands and messages are temporarily stored in the buffer of the LSI of the terminal device 24, the CPU decodes them, and the write or read operation in the designated LUN 31 is executed.

When using SCSI, the initiator
When sending a command instructing the operation of a specific LUN31, 11 also sends a queue message that specifies the waiting order of the operation of the LUN31, so that a large number of commands can be executed without waiting for the end of the operation of the LUN31. Can be sent. The value of this queue can be specified in 256 ways by a 1-byte signal.

The command with a queue message is 1
Each set is held in the LSI buffer of the terminal device 24 and then read into the interrupt register of the CPU. In this way, the CPU reading commands accompanied by queue messages one after another, in order from the command with the smallest queue value, Causes the LUN 31 to execute the commanded operation.

As shown in FIG. 4, the conventional LSI for controlling the SCSI protocol includes an ID holding circuit 2 for taking in the ID of an initiator that sends a message or a command, and a buffer for holding a message and a command received from the initiator. 5, a control bus control circuit 3 for directly inputting / outputting to / from the SCSI bus 8, a message counter 7 for counting the number of bytes of a received message, and a micro sequencer including a ROM 41 storing a processing program in the LSI 1. 4 and.

The micro sequencer 4 is a CPU to C
When the wait command for instructing the standby for receiving the SCSI command is received through the PU bus 9, the control signal is sent to each block of the LSI 1 and the processing program is executed in the procedure shown in FIG.

Step 1: Waiting for the selection of the initiators 11 to 13 and selecting the device, the initiator 11
Then, the micro sequencer 4 which has obtained the information through the control bus control circuit 3 sends a control signal to the ID holding circuit 2 to hold the ID of the initiator 11. This retained I
D is data for informing the CPU of which initiator the command transmission destination is.

Step 3: The micro sequencer 4
Controls whether the attention signal is on in the control bus 82 of the SCSI bus 8.
It is identified by the status signal sent from the bus control circuit 3.
The SCSI protocol specifies that an attention signal be turned on to the control bus 82 when a message is transmitted. When the attention signal is not on, only the command is received, so the process proceeds to step 14.

Step 4: When the attention signal is on, the value of the data bus 81 is transferred by 1 byte to the buffer 5 (when transferring to the buffer, the micro sequencer 4 buffers the control signal and the addressing signal). Step 5; Send a control signal to the message counter 7 to store the number of bytes in the message.

Step 6; the received message is a LUN
Identify whether 31 is an Identify message. The Identify message can specify 8 LUNs by using 3 bits in 1 byte.

Step 7; Next, it is identified whether the attention signal is on, and if not, step 14
To move to command reception.

Step 8: When the attention signal is ON, the value of the data bus 81 is transferred by 1 byte to the buffer 5, Step 9: The number of bytes of the message counter 7 is incremented, Step 10: The received message is Identifies whether it is a queue message. If it is a queue message, step 11; further, the queue message of the second byte is transferred to the buffer 5, and step 12; the number of bytes of the message counter 7 is incremented.

In this way, the Identify message and the message regarding the queue are received up to a total of 3 bytes, transferred to the buffer 5, and the number of transferred bytes is set in the message counter 7. The value of the message counter 7 is data that tells the CPU the range of the message.

Step 13: When the attention signal is not turned on, Step 14: First, data is received to receive the command.
Transfer one byte of the bus 81 to the buffer 5.

Step 15: This 1-byte value defines the command length, and Step 16 transfers the data on the data bus 81 to the buffer 5 to receive the command of the specified command length.

Step 17: When the amount of data transferred to the buffer 5 reaches a predetermined command length, Step 18: The micro sequencer 4 issues a normal end interrupt to the CPU.

When the normal termination interrupt occurs, the CPU receives the I of the initiator held in the ID holding circuit 2.
D, the number of bytes of the message stored in the message counter 7, and the code of the message and the command stored in the buffer 5 are read into the normal end interrupt data storage area of the register of the CPU.

If the received data is not an Identify message or a queue message in step 6 or step 10, or if the attention signal is on in step 13, the processing in LSI 1 is interrupted and the CPU is abnormal. An end interrupt is generated and the subsequent processing is entrusted to the CPU.

As described above, the conventional LSI 1 generates an interrupt to the CPU each time it receives a set of messages and commands, and waits for the next command from the CPU. During this time,
The LSI 1 holds the connection with the SCSI bus 8.

[0022]

However, each time a set of messages or commands is received from the initiator, the CPU
In the conventional command reception method that generates interrupts to the system, the number of initiators connected to the system increases (so-called multi-initiator environment), and if the device is frequently accessed, the CPU program load becomes heavy. Also, there is a problem that the overall efficiency of the system cannot be increased because the bus occupation time increases.

The present invention solves the above-mentioned conventional problems, and provides a command reception system for an LSI that can reduce the program load on the CPU of the device and improve the overall efficiency of the system. Has an aim.

[0024]

In view of the above, the present invention provides a command receiving system for an LSI for controlling the SCSI protocol, which is provided with a buffer for holding messages and commands received from an initiator via a SCSI bus. As long as the storage capacity of the buffer is not exceeded, a plurality of sets of messages and commands received from the initiator are held in the buffer, and the SCSI bus is disconnected while the messages and commands are not received.

[0025]

Therefore, the LSI continues to hold a plurality of sets of messages and commands received from the initiator until the storage capacity of the buffer is full, and when the buffer is full, an interrupt is issued to the CPU. Therefore, CP
The U does not need to respond each time a message or command is received, so the program load is reduced.

Further, since the SCSI bus is disconnected by the unique operation of the LSI when the reception of the command is completed, the bus occupation time is short.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the command receiving system according to the embodiment of the present invention, the LSI shown in FIG. 2 is used for its implementation.

This LSI 1 has an ID holding circuit 2 for taking in the ID of an initiator that sends a message or command.
A buffer 51 for holding the ID, message and command received from the initiator, a switch 6 for switching the connection to the buffer 51 to the ID holding circuit 2 or the SCSI data bus 81, and a control for directly inputting / outputting to / from the SCSI bus 8. A bus control circuit 3 and a micro sequencer 4 containing a ROM 41 storing a program for processing in the LSI 1 are provided. Since the buffer 51 needs to hold more data than the conventional one,
The capacity is increased.

The micro sequencer 4 is a CPU to S
When the wait command for instructing the reception waiting of the CSI command is received, the control signal is sent to each block of the LSI 1 and the processing program is executed in the procedure shown in FIG.

Step 1: Waiting for the selection of the initiator, and if there is an initiator that has selected the device, the micro sequencer 4 which has obtained the information through the control bus control circuit 3 sends a control signal to the switch 6. Then, the ID holding circuit 2 is connected to the buffer 51, and step 3; the ID of the initiator held in the ID holding circuit 2 is transferred to the buffer 51.

Switch 4; Then, the switch 6 is returned to the data bus 81 side, and Step 5; Whether the attention signal is in the ON state or not is discriminated by the status signal sent from the control bus control circuit 3. When the attention signal is not on, only the command is received, so that the process proceeds to step 13.

Step 6; When the attention signal is on, the micro sequencer 4 transfers 1 byte of the value of the data bus 81 to the buffer 51, and Step 7: Id that the received message specifies the LUN.
Identifies whether the message is an entify message.

Step 8; Next, it is determined whether the attention signal is on, and if not, step 13
To move to command reception.

Step 9: When the attention signal is on, the value of the data bus 81 is transferred by 1 byte to the buffer 51. Step 10: It is discriminated whether the received message is a queue message. If it is a queue message, step 11; the queue message of the second byte is further transferred to the buffer 51.

In this manner, the Identify message and the message related to the queue are received up to a total of 3 bytes and transferred to the buffer 51.

Step 12: When the attention signal is no longer on, the process proceeds to the reception of a command, but Step 13: the micro sequencer 4 precedes the reception of the command by a delimiter code (for separating the message from the command). For example, 7Fh; a code that is impossible as a message) is transferred to the buffer 51.

Step 14; Next, transfer 1 byte of the data bus 81 to the buffer 51, and Step 15: Determine the command length to be received by the value of 1 byte.

Step 16: Transfer the data on the data bus 81 to the buffer 51, and Step 17: When the amount of data transferred to the buffer 51 reaches a predetermined command length, Step 18: Through the control bus control circuit 3, The disconnect message is transferred to the initiator, and step 19: the SCSI bus 8 is set to the free state.

Step 20: After that, the process returns to the state of waiting for selection from the initiator (step 1).
However, if the unused portion of the buffer 51 is 16 bytes or less, it is determined that no more data can be retained (up to 17 bytes may be used from selection to command reception), and the step 21: micro sequencer 4 generates a normal end interrupt to the CPU.

The contents of the data held in the buffer 51 at this time are shown in FIG. When the normal termination interrupt occurs, the CPU reads the buffer 51 from the beginning, decodes the ID of the selected initiator, the received message, and the command, and executes the processing according to the decoded ID.

If the received data is not an Identify message or a queue message in step 7 or step 10, or if the attention signal is on in step 12, the processing in LSI 1 is interrupted and the CPU is abnormal. An end interrupt is generated and the subsequent processing is entrusted to the CPU.

As described above, in the command receiving system of the embodiment, if the CPU issues an instruction once to the LSI, the LSI will issue a plurality of sets of messages and commands until the buffer 51 built therein is full. It is possible to receive and to disconnect the bus 8 during the reception.

Of course, the contents of commands and messages are not limited to those illustrated. Further, as the delimiter between the message and the command, any method can be used as long as it can substantially separate the two.

Further, this command acceptance system can be adopted in a system of one initiator. In this case, it is not necessary to buffer the ID of the initiator.
No need to hold at 51.

[0045]

As is apparent from the above description of the embodiments, in the command receiving system of the present invention, the CPU of the device has the buffer built in the LSI even under the system environment where the device is frequently accessed. S until 51 is full
Since it is released from the control of the CSI protocol, the CPU
It is possible to reduce the burden on the user and concentrate on other processing such as servo processing. Therefore, the number of CPUs can be reduced in a device that conventionally requires a plurality of CPUs.

Further, since the LSI performs the process of returning to the bus free at the end of the reception of the message and the command, the occupied time of the bus is short, so that the bus of the entire system can be effectively used. The efficiency of can be improved.

[Brief description of drawings]

FIG. 1 is a flow chart showing a procedure of an embodiment in a command reception system of the present invention,

FIG. 2 is a block diagram showing a configuration of an LSI used in the above embodiment,

FIG. 3 is a diagram showing a data holding state in a buffer of the LSI in the above embodiment,

FIG. 4 is a block diagram showing a configuration of an LSI used in a conventional command reception system,

FIG. 5 is a flow diagram showing a procedure of a conventional command reception system,

FIG. 6 is a diagram illustrating a system connected by a SCSI bus.

[Explanation of symbols]

 1 LSI 2 ID holding circuit 3 Control bus control circuit 4 Micro sequencer 41 ROM 5, 51 Buffer 6 Switch 7 Message counter 8 SCSI bus 81 Data bus 82 Control bus 9 CPU bus 11-13 Initiator 21-25 Device 31 ~ 33 LUN

Claims (1)

[Claims] 1. A command reception system of a SCSI protocol control LSI provided with a buffer for holding a message and a command received from an initiator via a SCSI bus, wherein the command is received from the initiator unless the storage capacity of the buffer is exceeded. A method for receiving commands of a SCSI protocol control LSI, characterized in that a plurality of sets of the messages and commands are held in the buffer, and the SCSI bus is disconnected while the messages and commands are not received. .