JPH0635695A - Data processor - Google Patents

Abstract

PURPOSE:To realize a data processor in which the high speed of the processing of data or an instruction can be attained by adapting the error judging processing of the data or the instruction to the data processing speed of a processor. CONSTITUTION:An instruction fetch stage 7 fetches the data and a redundant signal 5 synchronously with the processing of a processor 10. The instruction fetch stage 7 supplies the fetched data and the redundant signal 5 to an even/odd judging circuit 12, and supplies the data to an instruction decode stage 8. The even/odd judging circuit 12 judges whether or not the data can be used from the data, redundant signal 5, and parity valid signal 4, and supplies an even/odd judged result signal 11 indicating the judged result to the decode stage 8. The decode stage 8 decodes the supplied data, and judges whether or not the data can be used from the even/odd judged result signal 11 supplied from the even/ odd judging circuit 12. When the data can not be used, the decode state 8 stops the decode. When the data can be used, the decode stage 8 supplies the decoded data or an instruction to an instruction executing stage 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for reading out data or an instruction to which an error judgment code is added and executing the data or the instruction.

[0002]

2. Description of the Related Art Data or instructions to which an error judgment code is added are read out, and it is judged whether or not there is an error in these data or instructions, and if there is no error, data for executing these data or instructions. There is a processing device. Figure 5
FIG. 3 is a schematic configuration diagram of the data processing device. In FIG. 5, an address signal of data to be read is supplied from the instruction execution stage 90 of the processor 100 to the memory 1 via the address bus 3 and the address decoder 2. Then,
The data corresponding to the address supplied from the memory 1 is output to the data and instruction bus 61, and at the same time, the redundant signal 50 which is an error determination code added to this data.
Are supplied to the even / odd determination circuit 120 of the external determination circuit 150. The even / odd determination circuit 120 compares the redundant signal 50 with the data on the bus 6 to determine the validity of the data. If the data is not valid, the even-odd determination circuit 120 sets one input terminal of the AND circuit 190 to the “H” level. When the instruction fetch stage 70 fetches the data on the bus 6, the instruction fetch stage 70 sets the read / write signal 140 supplied to the other input end of the AND circuit 190 to the “H” level. Therefore, when there is an error in the data, the bus error signal 130 output from the AND circuit 190 is
It becomes "H" level. The bus error signal 130 is supplied to the instruction fetch stage 70, and when the signal 130 is at the “H” level, the instruction fetch stage 70 determines that there is an error in the data. If not, the data fetched by the instruction fetch stage 70 is supplied to the instruction execution stage 90 via the instruction decode stage 80.

FIG. 6 is a circuit configuration example of the even-odd determination circuit 120. The even / odd determination circuit 120 is a NOT circuit 120.
A to 120C, 121A to 120C, AND circuit 122
A to 122D and an OR circuit 123. Then, the data 60 on the bus 6 is supplied to the NOT circuits 120A and 120B, and the redundant signal 50 is sent to the NOT circuit 12.
It is supplied to 0C.

As an example of the data processing device,
Control system of electronic computer described in JP-A-2-44432, information processing device described in JP-A-58-181150, or read data transfer system described in JP-A-56-27456 Etc.

[0005]

By the way, in the above data processing apparatus, it is desired to speed up data or instruction processing, and the data or instruction processing of the processor 100 itself is
It is getting faster. However, the external decision circuit 150 for deciding an error in the data or instruction has a limited processing speed, and is lower than the processing speed of the processor 100. Therefore, the processor 100 has to have a high-speed processing capability, but its processing speed must be adapted to the low-speed external determination circuit 150, which makes it difficult to speed up the data processing of the entire data processing apparatus.

Therefore, a data processor is disclosed in Japanese Patent Laid-Open No. 56-2.
It is conceivable to configure as described in Japanese Patent No. 7456. That is, the data is transferred to the external logic device before the error determination of the data, and then the error detection circuit executes the error determination of the data. If there is an error in the data, the fact that there is an error is transmitted to the external logical device, and if the data can be corrected, the data is corrected and transferred to the external logical device. The external logic unit re-executes the processing with the corrected data. If the previously supplied data is unprocessed, the external logic device performs the process according to the corrected data. With this configuration, it is possible to speed up the data processing of the external logic device when there is no error in the data.

However, simply increasing the speed of the data processing of the external logic device makes it asynchronous with the error detection circuit, and when the data error occurs, the external logic device cannot determine which data is the error. Will end up. Therefore, the data processing speed of the external logic device must be adapted to the processing speed of the error detection circuit, which makes it difficult to increase the processing speed of the data processing device.

An object of the present invention is to realize a data processing device in which error determination processing of data or instructions is adapted to the data processing speed of a processor and the processing of data or instructions is speeded up.

[0009]

In order to solve the above-mentioned object, the present invention is configured as follows. An instruction execution unit that executes supplied data or instructions, an address decoder that decodes and outputs an address signal output from the instruction execution unit, and outputs a redundant signal valid signal,
Data and instructions are stored, and when reading out the data or instructions, the storage means outputs the data or instructions according to the address signal output from the address decoder, and outputs the redundant signal of the data or instructions, and the storage means. An instruction fetch unit that fetches the output data or instruction and the redundant signal, and 1 or 0 of binary information of the data or instruction fetched by the instruction fetch unit.
And an odd / odd judgment unit that outputs an even / odd judgment result signal indicating whether data or an instruction can be used or not, based on the total number of the redundant signals and the redundant signal and the redundant signal valid signal output from the address decoder. According to the even / odd judgment result signal output from the unit, it is judged whether the data or the instruction fetched by the instruction fetch unit can be used or not, and if the data or the instruction can be used, the data or the instruction is decoded and the instruction is executed. And an instruction decoding unit that supplies the unit.

Further, an instruction executing section for executing the supplied data or instruction, an address decoder for decoding and outputting an address signal output from the instruction executing section, a data and instruction are stored, and data or instruction is read out. Sometimes, according to the address signal output from the address decoder,
A storage unit that outputs data or an instruction and outputs a redundant signal of the data or the instruction, an instruction fetch unit that fetches the data or the instruction output from the storage unit, and the data or the instruction output from the storage unit Of 2
Based on the total number of 1 or 0 of the evolution information and the redundant signal, it is determined whether the data or the instruction is available or not, and the data or the instruction is available or not in synchronization with the operation of the instruction fetch unit. A determination unit that outputs a determination signal indicating whether it is possible, and according to the determination signal that is output from the determination unit, determines whether the data or instruction fetched by the instruction fetch unit is available or not, and if available, Includes an instruction decoding unit that decodes the data or instruction and supplies the instruction or execution unit with the instruction decoding unit.

[0011]

In the first cycle, the even-odd judgment unit judges whether the data or the instruction is usable or not. Then, in the next cycle, the even / odd determination result signal of the data or the instruction is supplied to the instruction decoding unit. At this time, since the instruction decoding unit decodes the data or the instruction determined by the even / odd determination unit as a target, the determination result of the even / odd determination unit and the target data of the decoding unit correspond correctly. After that, the even / odd determination unit supplies the data decoded by the instruction decoding unit or the even / odd determination result signal of the instruction to the decoding unit.
As a result, the instruction fetch unit can transfer the data or instruction to the instruction decode unit in the next stage without waiting for the determination result of the even / odd determination unit.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic block diagram of a data processing apparatus according to an embodiment of the present invention. In FIG. 1, the processor 1
0 includes an instruction fetch stage 7, an instruction decode stage 8, an instruction execution stage 9, and an even / odd determination circuit 12. Further, 1 is a memory such as a FIFO (First in first out) cache memory, and this memory 1 stores data or instructions necessary for the processor 10 to operate. The memory 1 can read and write necessary data or instructions according to the address signal supplied from the address decoder 2.

An address signal is supplied from the instruction execution stage 9 to the address decoder 2 via the address bus 3. Then, the address decoder 2 supplies the decoded address signal to the memory 1, and also supplies the parity valid signal 4 indicating whether the redundant signal 5 described later is valid or invalid to the even / odd determination circuit 12. The memory 1 supplies data or an instruction corresponding to the supplied address signal to the instruction fetch stage 7 via the data and instruction bus 6. Also, memory 1
Also supplies the redundant signal 5 of the data or instruction supplied to the instruction fetch stage 7 to the instruction fetch stage 7.

The instruction fetch stage 7 fetches the data or instruction and the redundant signal 5 in synchronization with the pipeline processing of the processor 10. Then, the instruction fetch stage 7
The fetched data or instruction and the redundant signal 5 are supplied to the even / odd determination circuit 12, and the data or instruction is supplied to the instruction decoding stage 8. The even / odd determination circuit 12 determines whether the data or instruction is based on the number of “1” or “0” of the binary information forming the data or instruction, the redundancy signal 5 of “1” or “0”, and the parity valid signal 4. Determine if it is available or not. Then, the even-odd judgment result signal 1 indicating this judgment result
1 is supplied to the instruction decode stage 8.

The instruction decode stage 8 decodes the data or instruction supplied from the instruction fetch stage 7, and
Even / odd judgment result signal 11 supplied from the even / odd judgment circuit 12
Determines whether data or instructions are available. If the data or instruction is not available, the decode stage 8 stops decoding. If the data or instruction is available, the instruction decode stage 8 supplies the decoded data or instruction to the instruction execution stage 9. Then, the instruction execution stage 9 operates the processor 10 according to the data or the instruction supplied from the instruction decode stage 8.

FIG. 2 is an operation time chart of the example of FIG. In FIG. 2, (A) is a synchronization clock,
(B) is an address signal on the address bus 3, (C)
Indicates data on the bus 6, and (D) indicates the redundant signal 5.
Also, (E) is the operation of the instruction fetch stage 7, and (F) is
The operation of the instruction decode stage 8 and (G) show the operation of the instruction execution stage 9.

First, in the first cycle S1 from time To to T1, the data A and the redundant signal α are fetched by the instruction fetch stage 7. Next, in the second cycle S2 from time T1 to time T2, the data B and the redundant signal β
And are fetched into the instruction fetch stage 7. Further, the instruction decoding stage 8 decodes the data A. Then, in the third cycle S3 from time T2 to time T3, the data C and the redundant signal γ are fetched by the instruction fetch stage 7. Further, the instruction decode stage 8 decodes the data B, and the instruction execution stage 9 executes the processing of the data A. 20 is a processor setup time.

Now, the operation of the even / odd determination circuit 12 will be described. The even / odd determination circuit 12 determines whether the data A is usable or impossible in the first cycle S1. Then, in the second cycle S2, the even / odd determination result signal 11 of the data A
Are supplied to the instruction decoding stage 8. At this time, since the instruction decode stage 8 is decoding the data A, the target data is the even-odd judgment result signal 11
Is consistent with Thereafter, the even / odd determination circuit 12 outputs the even / odd determination result signal 11 of the data B when the instruction decoding stage 8 is decoding the data B, and outputs the even / odd determination result signal 11 of the data C when the data is C. . As a result, the processor 10 can execute data processing in synchronization with the first, second, third cycles, ....

On the other hand, consider the case where the conventional data processing apparatus of FIG. 5 is operated in the cycle of FIG.
The even / odd determination circuit 120 in the example of FIG. 5 determines whether the data A is usable or impossible in the first cycle S1. Then, in the second cycle S2, the bus error signal 130
To the instruction fetch stage 70. At this time, the instruction fetch stage 70 is fetching the data B instead of the data A. Therefore, an erroneous determination is made that the determination result of the data A is the determination result of the data B. Therefore, the instruction fetch stage 70 keeps the data A until the second cycle.
Must be retained. On the other hand, in the case of the example of FIG. 1, the fetch stage 7 can fetch the data B in the second cycle. Therefore, it can be understood that the data processing of the processor 10 in the example of FIG. 1 is significantly accelerated as compared with the data processing of the processor 100 in the example of FIG.

As described above, according to one embodiment of the present invention, there is provided a data processing device in which the error determination processing of data or instructions is adapted to the data processing speed of the processor and the processing of data or instructions is speeded up. Can be realized.

FIG. 3 is a schematic block diagram of a data processing apparatus according to another embodiment of the present invention, in which components equivalent to those in FIG. 1 are designated by the same reference numerals. In FIG. 3, the memory 1
The redundant signal 5 from is supplied to the even / odd determination circuit 12 of the external determination circuit 15. The even / odd determination circuit 12 is also supplied with data or an instruction from the data / instruction bus 6.
The decision signal of the even / odd decision circuit 12 is supplied to one input terminal of the AND circuit 13. The read / write signal 140 from the instruction fetch stage 7 is supplied to the other input terminal of the AND circuit 13. When the redundant signal cannot be used, the AND circuit 19 supplies the bus error signal 13 to the synchronizing circuit 18. The synchronizing signal 17 from the instruction fetch stage 7 is also supplied to the synchronizing circuit 18. And
The synchronization circuit 18 supplies the synchronization error signal 16 synchronized with the operation of the processor 10 to the instruction decode stage 8.

FIG. 4 is an operation time chart of the example of FIG. In FIG. 4, (A) is a synchronization clock,
(B) is an address signal on the address bus 3, (C)
Indicates data on the bus 6, and (D) indicates the redundant signal 5.
Further, (E) shows the synchronization error signal 16, (F) shows the operation of the instruction fetch stage 7, (G) shows the operation of the instruction decode stage 8, and (H) shows the operation of the instruction execution stage 9. .

First, in the first cycle S1 from the time points To to T1, the data A is fetched by the instruction fetch stage 7. Next, in the second cycle S2 from time T1 to time T2, the data B is fetched by the instruction fetch stage 7. Further, the instruction decoding stage 8 decodes the data A. Then, in the third cycle S3 from time T2 to time T3, the data C is fetched by the instruction fetch stage 7. Further, the instruction decode stage 8 decodes the data B, and the instruction execution stage 9 executes the processing of the data A. 20 is a processor setup time.

Here, the operation of the external judgment circuit 15 will be described. In the first cycle S1, the even / odd determination circuit 12 determines whether the data A can be used or not, and the bus error signal 1
3 is supplied to the synchronizing circuit 18. Then, in the second cycle S2, the synchronization circuit 18 causes the synchronization error signal 16
(A · α) is supplied to the instruction decode stage 8. At this time,
Since the instruction decoding stage 8 is decoding the data A as a target, it matches the data that is the target of the synchronization error signal 16. After that, the external determination circuit 15
When the instruction decoding stage 8 is decoding the data B, the synchronization error signal 16 (B.beta.) Of the data B is output, and when the instruction C is the data C, the synchronization error signal 16 (C.γ) of the data C is output. Output. As a result, the processor 1
0 can execute data processing in synchronization with the first, second, third cycles, .... In the example of FIG. 3 described above, the same effect as that of the example of FIG. 1 can be obtained.

In the above-mentioned example, the reading of data or instructions was described, but writing of data or instructions to the memory 1 can also be performed. That is, in the example of FIGS. 1 and 3, the data or instruction to be written from the instruction fetch stage 7 and its redundant signal are supplied to the memory 1 via the bus 6. The memory 1 stores the above-mentioned data or instruction and its redundant signal at the address supplied from the address decoder 2.

The above-described data processing apparatus of the present invention can be applied to many other things such as image processing in an MRI apparatus. In particular, when applied to the image processing in the MRI apparatus, the image processing can be speeded up and the inspection time can be shortened.

[0027]

Since the present invention is constructed as described above, it has the following effects. An instruction execution unit, an address decoder that decodes an address signal and outputs a redundant signal valid signal, a storage unit that outputs data or an instruction according to the address signal from the address decoder, and a redundant signal, and a storage unit Instruction fetch unit for fetching the data or instruction from the instruction and the redundant signal, the total number of 1 or 0 of the binary information of the data or instruction fetched by the instruction fetch unit, the redundant signal, and the redundancy from the address decoder. Based on the signal valid signal and
Whether the data or instruction fetched by the fetch unit is usable or not is determined according to the even / odd determination unit that outputs an even / odd determination result signal indicating whether or not the data or instruction is usable, and the even / odd determination result signal from the even / odd determination unit. And an instruction decoding unit that decodes the data or the instruction and supplies the decoded data or instruction to the instruction executing unit when the determination is possible. Therefore, the error determination processing of data or instructions can be adapted to the data processing speed of the processor, and the data processing device in which the processing of data or instructions is speeded up can be realized.

Further, according to the present invention, an instruction executing section, an address decoder for decoding and outputting an address signal from the instruction executing section, and a memory for outputting data or an instruction and a redundant signal according to the address signal from the address decoder. Means, an instruction fetch unit for fetching data or instructions from the storage means, and the data or instructions can be used based on the total number of 1 or 0 of the binary information of the data or instructions from the storage means and the redundant signal. Whether the data is fetched or not is fetched by the instruction fetch unit according to the determination signal output from the determination unit and the determination unit that outputs a determination signal indicating whether the data or the instruction is usable in synchronization with the instruction fetch unit. An instruction decoding unit that determines whether or not the data or instruction can be used, and if the data or instruction is usable, decodes the data or instruction and supplies the instruction or decoding unit with the instruction decoding unit. Therefore, similarly to the above, it is possible to adapt the data or instruction error determination processing to the data processing speed of the processor, and to realize a data processing device in which the data or instruction processing is speeded up.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

FIG. 2 is an operation time chart of the example of FIG.

FIG. 3 is a schematic configuration diagram of another embodiment of the present invention.

FIG. 4 is an operation time chart of the example of FIG.

FIG. 5 is a schematic configuration diagram of a conventional example of a data processing device.

FIG. 6 is a circuit diagram of an example of an even / odd determination circuit.

[Explanation of symbols]

 1 memory 2 address recorder 3 address bus 4 redundant signal valid signal 5 redundant signal 6 data and instruction bus 7 instruction fetch stage 8 instruction decode stage 9 instruction execution stage 10 processor 11 even / odd decision circuit 12 even / odd decision circuit 13 bus error signal 15 external Judgment circuit 16 Synchronization error signal 17 Synchronization signal 18 Synchronization circuit

Claims (3)

[Claims] 1. An instruction executing unit for executing supplied data or an instruction, and an address signal output from the instruction executing unit,
An address decoder that outputs a redundant signal valid signal while outputting, stores data and an instruction, and outputs the data or the instruction according to the address signal output from the address decoder when reading the data or the instruction. Storage means for outputting a redundancy signal of an instruction, data or instruction output from the storage means, an instruction fetch unit for fetching the redundancy signal, and binary information of data or instruction fetched by the instruction fetch unit 1 or 0, the redundant signal, and the redundant signal valid signal output from the address decoder to output an even-odd determination result signal indicating whether the data or the instruction can be used or not. According to the even / odd judgment result signal output from the even / odd judgment unit,
An instruction decoding unit that determines whether the data or instruction fetched by the instruction fetch unit is available or not, and if the data or instruction is available, decodes the data or instruction and supplies the instruction or execution unit with the instruction decoding unit; A data processing device characterized by the above. 2. An instruction executing section for executing supplied data or an instruction, and an address signal output from the instruction executing section,
An address decoder for outputting and data and instructions are stored, and when reading out the data or instructions, the storage means for outputting the data or instructions according to the address signal output from the address decoder and outputting the redundant signal of the data or instructions. An instruction fetch unit that fetches data or an instruction output from the storage unit, a total number of 1 or 0 of binary information of the data or instruction output from the storage unit, and a redundant signal, A determination unit that determines whether the data or instruction is available or not, and outputs a determination signal indicating whether the data or instruction is available or unavailable in synchronization with the operation of the instruction fetch unit, and is output from the determination unit. According to the determination signal that is made, it is determined whether the data or instruction fetched by the instruction fetch unit can be used, and if it is available, An instruction decoding unit that decodes the data or instruction and supplies the instruction or execution unit to the instruction execution unit. 3. The data processing device according to claim 1 or 2, when writing data or an instruction, the instruction fetch unit stores the data or the instruction and the redundant signal of the data or the instruction in the storage means. The data processing device is characterized in that the storage means stores the supplied data or instruction and the redundant signal at the address indicated by the address signal from the address decoder.