JPH06350585A - Timing extract circuit - Google Patents

Abstract

PURPOSE:To attain high speed locking at training and to improve the stability of the system by providing an overflow control circuit and controlling a voltage controlled oscillator and a programmable counter so as to generate a received sampling clock. CONSTITUTION:An output of an overflow control circuit 103 is converted into an analog signal by a D/A converter 104, an analog low pass filter 105 limits the band of the analog signal and the input subjected to band limit is a control voltage of a voltage controlled oscillator 106. A programmable counter 107 frequency-divides an oscillating frequency of the oscillator 106 by 1/N (natural number) to generate a sampling clock 2. Furthermore, the counter 107 references a counter control signal 108 for each M[T] (M is a natural number and T is a predetermined period), and when the count is positive, the initial value of the counter is set to N-1 and when the value is negative, the initial value of the counter is set to N+1 to adjust the sampling phase. However, the counter 107 does not refer to the signal 108 after phase locking.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing extraction circuit, and more particularly to a timing extraction circuit applied to an echo canceller type digital subscriber line transmission system using a pair metallic cable.

[0002]

2. Description of the Related Art A timing extraction circuit in a digital subscriber line transmission system is used for the purpose of extracting a sampling clock from a received signal at an optimum phase.

FIG. 4 is a block diagram showing a transceiver configuration used in a digital subscriber line transmission system.
This transceiver includes a transmission circuit 12 for transmission, a reception circuit 9 for reception, a hybrid circuit 8 for separating a transmission / reception signal, an echo canceller 10 and a subtractor 14 for suppressing an echo which is a wraparound of the transmission signal, and a waveform. A waveform equalizer circuit 11 for equalizing, a decision feedback equalizer 6 and a subtractor 15 for removing intersymbol interference after the decision point.
And a determination circuit 5 for calculating the determination value 3 and the determination error 4
And a timing extraction circuit 1 for exchanging signals at a multi-valued level with an opposing transceiver.

FIGS. 5 and 6 are block diagrams showing an example of a conventional timing extraction circuit. However,
6 is a block diagram showing a digital timing extraction circuit, and FIG. 6 is a block diagram showing an analog timing extraction circuit. Conventionally, the timing extraction circuit is
Generally, as a phase comparator, a pre-cursor zero-cross estimation type phase comparator capable of baud rate timing extraction is used ([May 1976, iE.E.
ETransaction on communication,
Volume COM-24, No. 5 (IEEE TRANSAC
TIONS ONCOMMUNICATIONS, VO
L. COM-24, NO5, MAY 1976)).

The timing extraction circuit shown in FIG. 5 includes a pre-cursor zero-cross estimation type phase comparator 101 having a judgment value 3 and a judgment error 4 as inputs, and a digital low-pass filter 102 having an output of the phase comparator 101 as an input. Phase control circuit 201 that receives the output of digital low-pass filter 102, and output of phase control circuit 201 and oscillator 202
And the programmable counter 107 that receives the output of

Next, the operation of the timing extraction circuit of FIG. 5 will be described. The phase comparator 101 generates phase information based on the judgment value 3 and the judgment error 4. This phase information is band-limited by the digital low-pass filter 102. The oscillator 202 uses N (N
Is an integer, the larger the value, the finer the sampling phase can be adjusted). The programmable counter 107 divides the output of the oscillator 202 by N to generate the sampling clock 2. The phase control circuit 201 advances the sampling phase by advancing the counter of the programmable counter 107 if the output of the digital low-pass filter 102 is positive, and advances the sampling phase if the output of the digital low-pass filter 102 is negative.
Delay the phase by returning the counter of.

The timing extraction circuit shown in FIG. 6 includes a pre-cursor zero-cross estimation type phase comparator 101 having a judgment value 3 and a judgment error 4 as inputs, and a digital low-pass filter 102 having the output of the phase comparator 101 as an input. The D / A converter 104 that receives the output of the digital low-pass filter 102, the analog low-pass filter 105 that receives the output of the D / A converter 104, and the voltage-controlled oscillator 106 that receives the output of the analog low-pass filter 105.
And a frequency dividing circuit 203 which receives the output of the voltage controlled oscillator 106 as an input.

Next, the operation of the timing extraction circuit of FIG. 6 will be described. The output of the digital low-pass filter 102 generated similarly to the analog method is the D / A converter 1
It is converted into an analog value by 04. D / A converter 10
The output of No. 4 is band-limited by the analog low-pass filter 105 and becomes the control voltage of the voltage-controlled oscillator 106.
Similar to the digital method, the free-running oscillation frequency of the voltage controlled oscillator 106 becomes N times the sampling clock 2 and is divided by the frequency dividing circuit 203 by N to become the sampling clock 2 (where N is the characteristic of the timing extractor). Does not affect).

[0009]

However, these conventional timing extraction circuits have the following problems.

In the digital method, the estimated waveform of the echo canceller is displaced at the time of the phase jump, and the echo suppression amount is primarily deteriorated, and a correction circuit for this is required. As a solution to this problem, there is a method of increasing the frequency division ratio of the oscillation frequency and the sampling frequency to reduce the phase jump width. However, this method has a problem that it is difficult to realize the higher the transmission speed of the system.

In the analog system, the stability of the system after the phase pull-in should be small in the variable frequency width of the voltage controlled oscillator, but there is a problem that the phase pull-in time becomes long if the variable frequency width is made small.

An object of the present invention is to provide a timing extraction circuit that solves such a problem.

[0013]

A timing extraction circuit according to the present invention uses a pre-cursor zero-cross estimation type phase comparator for inputting a decision value and a decision error and an output of the pre-cursor zero-cross estimation type phase comparator. A digital low-pass filter, an overflow control circuit that receives the output of the digital low-pass filter, a D / A converter that receives the first output of the overflow control circuit, and an output of the D / A converter. An analog low-pass filter, a voltage-controlled oscillator that receives the output of the analog low-pass filter, and a programmable counter that receives the output of the voltage-controlled oscillator and the second output of the overflow control circuit. Characterize.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The timing extraction circuit 100 according to the present embodiment includes a pre-cursor zero-cross estimation type phase comparator 101 having a judgment value 3 and a judgment error 4 as inputs, and a digital low-pass filter 102 having an output of the phase comparator 101 as an input.
An overflow control circuit 103 that receives the output of the digital low-pass filter 102; a D / A converter 104 that receives the output of the overflow control circuit 103;
An analog low-pass filter 105 that receives the output of the A / A converter 104, a voltage-controlled oscillator 106 that receives the output of the analog low-pass filter 105, and an output of the voltage-controlled oscillator 106 and an output of the overflow control circuit 103. And a programmable counter 107 that operates.

FIG. 2 is a block diagram showing the structure of the overflow control circuit for explaining the inside of the overflow control circuit 103. This overflow control circuit 1
Reference numeral 03 denotes a level comparator 112 having a digital low-pass filter output as an input 111, an input 111, a positive set value 113, a negative set value 114, and a counter control signal 110 which is an output of the level comparator 112. It is composed of a selector 115 for input.

Next, the operation of this embodiment will be described with reference to FIGS. 1 and 2. The phase information is generated by the pre-cursor zero-cross estimation type phase comparator 101 and the digital low-pass filter 102 using the judgment value 3 and the judgment error 4 as in the conventional timing extraction circuit. This phase information takes a negative (positive) value when the sampling phase leads the optimum phase, and takes a positive (negative) value when the phase lags. The output of the digital low pass filter 102 is input to the overflow control circuit 103.

Now, the operation of the overflow control circuit 103 will be described with reference to FIG. Input 111
(Digital low-pass filter output) is the level comparator 1
It is compared by 12 with a preset level. The set value has two values, positive and negative, and the value is determined by the characteristics of the phase comparator. The level comparator 112 outputs a value of +1 when the input 111 is larger than the positive set value, a value of -1 when the input 111 is smaller than the negative set value, and a value of 0 otherwise. Output to. The output 116 (to the D / A converter) is the selector 115.
When the counter control signal 108 is +1, it is set to the positive set value 113 of the level comparator 112, and when the counter control signal 108 is −1, it is set to the negative set value 114 of the level comparator 112. When the control signal 108 is 0, it becomes the input 111.

Here again, referring back to FIG. 1, the output of the overflow control circuit 103 (the output 116 of FIG. 2) is the D / A.
The analog value is converted into an analog value by the converter 104, and the analog low-pass filter 105 band-limits the analog value.
The control voltage is 06. Programmable counter 107
Generates a sampling clock 2 by dividing the oscillation frequency of the voltage controlled oscillator 106 by N (N is a natural number), as in the conventional timing extraction circuit (digital method). The program counter 107 refers to the counter control signal 108 every M [T] (M is a natural number, T is one cycle of the sampling clock), and if the value is +1, sets the initial value of the counter to N-1. If the value is -1, the initial value of the counter is set to N + 1 and the sampling phase is adjusted. However, the program counter 107 refers to the counter control signal 108 only when the phase is pulled, and does not refer to it after the phase is pulled.

FIG. 3 is a diagram showing the characteristics of the voltage controlled oscillator 106, showing the characteristics of the input voltage and the output frequency. The voltage controlled oscillator used in the present embodiment may have a small frequency variable width (a range that can follow the allowable deviation defined by the standard), which improves the stability of the system after timing extraction.

[0021]

As described above, the timing extraction circuit of the present invention is provided with the overflow control circuit, controls the voltage controlled oscillator and the programmable counter, and generates the reception sampling clock. This has the effect of making it possible to improve the stability of the system after pull-in and timing extraction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a timing extraction circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of an overflow control circuit in FIG.

FIG. 3 is a diagram showing characteristics of a voltage controlled oscillator.

FIG. 4 is a block diagram showing a transceiver configuration of a digital subscriber line transmission system.

FIG. 5 is a block diagram showing a configuration (digital system) of a conventional timing extraction circuit.

FIG. 6 is a block diagram showing a configuration (analog method) of a conventional timing extraction circuit.

[Explanation of sign]

 1 Timing Extraction Circuit 2 Sampling Clock 3 Judgment Value 4 Judgment Error 5 Judgment Circuit 6 Judgment Feedback Equalizer 7 Pair Metallic Cable 8 Hybrid Circuit 9, 12 Reception Circuit 10 Echo Canceller 11 Waveform Equalization Circuit 13 Transmission Data 14, 15 Subtraction Device 100 Timing extraction circuit of the present invention 101 Precursor zero-cross estimation type phase comparator 102 Digital low-pass filter 103 Overflow control circuit 104 D / A converter 105 Analog low-pass filter 106 Voltage-controlled oscillator 107 Programmable counter 108 Counter control signal 111 Digital low-pass filter Output 112 Level comparator 113 Positive set value 114 Negative set value 115 Selector 116 Selector output 201 Phase control circuit 202 Oscillator 203 Frequency divider circuit

Claims (2)

[Claims] 1. A pre-cursor zero-cross estimation type phase comparator which inputs a judgment value and a judgment error, a digital low-pass filter which inputs an output of the pre-cursor zero-cross estimation type phase comparator, and an output of the digital low-pass filter. Overflow control circuit for input, D / A converter for inputting first output of the overflow control circuit, analog low-pass filter for inputting output of the D / A converter, output of analog low-pass filter And a programmable counter that receives the output of the voltage controlled oscillator and the second output of the overflow control circuit as an input. 2. The overflow control circuit, a level comparator having the digital low-pass filter output as an input, the digital low-pass filter output, a positive set value,
2. The timing extraction circuit according to claim 1, further comprising a selector having a negative set value and a counter control signal output from the level comparator as inputs.