JPH06350509A - Intermittent radio receiver - Google Patents

Abstract

PURPOSE:To provide an intermittent radio receiver which does not lower battery saving efficiency in an intermittent receiving method utilizing a PLL system. CONSTITUTION:A decoder part 15 outputs control signals Clock, Data and LE to a PLL circuit 31 for controlling a set frequency value inside the PLL circuit 31 and outputs a control signal PS to the PLL circuit 31 and a timer 33 for controlling intermittent operation timing at the PLL circuit 31. On the other hand, the decoder part 15 controls the operation start timing of the PLL circuit 31 by controlling timing for turning the control signal PS to 'Hi' corresponding to margin time Tp 0 and (t) previously set inside the decoder part 15 and measured time data inputted from the timer 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermittent radio receiver, and more particularly, to an intermittent radio receiver for intermittently receiving by a PLL system.

[0002]

2. Description of the Related Art Some conventional intermittent radio receivers such as pagers control the frequency of a radio signal received by a PLL (Phase Locked Loop) system. For example, a circuit of a PLL control system as shown in FIG. Some have configurations.

In FIG. 5, reference numeral 1 is a PLL circuit, and V
The frequency output from a CO (Voltage Controlled Oscill-ator) circuit 2 is input to the fin terminal, and a control voltage is output from the out terminal to the VCO circuit 2 based on the result of comparison with a set frequency value. It controls to output the frequency signal of. Further, the LD terminal in the PLL circuit 1 is a terminal for notifying the outside that the VCO frequency input into the PLL circuit 1 has reached the set value (“Hi” when it reaches, “Low” when it does not reach). is there. In FIG. 5, the PLL circuit 1 and the VCO circuit 2 form a synthesizer 3.

Denoted at 4 is a decoder section for controlling the oscillation frequency of the PLL circuit 1, which outputs control signals Clock, Data and LE for controlling the frequency set value in the PLL circuit 1 to PL.
The control signal PS for controlling the intermittent operation timing in the PLL circuit 1 is output to the PLL circuit 1 while being output to the L circuit 1. Here, when the control signal PS is "Hi", the PLL operation is started, and when it is "Low", the PLL operation is stopped.

FIG. 6 shows a timing chart of PLL control during intermittent reception in the PLL control system of FIG.

In FIG. 6, data (a) is continuously transmitted from a transmitter (station). Now, for example,
If the data indicated by the shaded areas in the figure is the data to be received, the decoder 4 considers the rising time of the PLL circuit 1 and receives the control signal PS before the timing of receiving the data for a preset time Tp. Is "Hi" and P
The LL circuit 1 is operated (see (b) of the same figure). The time required for the VCO frequency input into the PLL circuit 1 to reach the set frequency is as shown in FIG.
Is To time after "Hi".

Therefore, the margin time Tp is "Tp> To
Is set to ".

[0008]

However, in the intermittent radio receiver which controls the reception frequency of the radio signal by utilizing such a conventional PLL control system, the above-mentioned PLL is used.
Since the time To until the VCO frequency input into the circuit 1 reaches the set frequency changes due to changes in the ambient temperature and the power supply voltage, the above margin time Tp is the maximum within the conceivable operating environment conditions. “Tp> To for To
Must be set so that, in a normal use environment, a margin time Tp that is longer than originally necessary is set, so that Tp-To = ΔT becomes large, and a pager or the like cannot be used. The intermittent radio receiver has a problem that the battery saving efficiency is lowered due to the intermittent reception and the battery life is shortened.

An object of the present invention is to prevent the battery saving efficiency from being lowered in the intermittent receiving method using the PLL system.

[0010]

The means of the present invention are as follows.

The present invention is, in an intermittent radio receiver for obtaining a required oscillation signal by a phase-locked loop circuit, measuring means for measuring the rise time of the phase-locked loop circuit, and the rise time measured by this measuring means and the advance time. A control means for outputting an intermittent signal for operating the phase locked loop circuit to the phase locked loop circuit earlier than the reception timing by a time obtained by adding the set margin time is provided.

[0012]

The operation of the means of the present invention is as follows.

According to the present invention, in the intermittent radio receiver for obtaining the required oscillation signal by the phase locked loop circuit,
The rising time of the phase locked loop circuit is measured by the measuring means, and the control means adds the rising time measured by the measuring means and a preset margin time earlier than the reception timing by the time added. Is output to the phase locked loop circuit.

Therefore, the unnecessary operation time of each reception timing in the intermittent radio receiver can be shortened, and the battery saving efficiency of the intermittent radio receiver can be improved. As a result, the life of the battery can be extended by using it for a pager or the like.

[0015]

EXAMPLES Examples will be described below with reference to FIGS.

1 to 4 are diagrams showing an embodiment of a pager to which the intermittent radio receiver of the present invention is applied.

First, the structure will be described. FIG. 1 is a block diagram of a pager. In this figure, the pager includes an antenna 11, a receiver 12, a synthesizer 13,
The demodulation unit 14, the decoder unit 15, the ID-ROM 16, the sound output unit 17, the control unit 18, the ROM 19, the RAM 20, the key input unit 21, the LCD driver 22 and the LCD 23.

The antenna 11 receives a calling signal wirelessly transmitted from a pager service company (not shown) or the like and outputs it to the receiving unit 12. The receiver 12 intermittently receives the ringing signal input from the antenna 11, amplifies the received signal, and outputs the amplified signal to the demodulator 14. The frequency of the received signal is reduced by the oscillation frequency input from the synthesizer 13.

The demodulating section 14 demodulates the received signal amplified and input by the receiving section 13 and outputs it to the decoder section 15.

The synthesizer 13, as shown in FIG.
It is composed of an LL circuit 31, a VCO circuit 32, and a timer 33, and is connected to the decoder unit 15.

The decoder section 15 controls the control signals Clock, Data, which control the set frequency value in the PLL circuit 31.
A control signal P that outputs LE to the PLL circuit 31 and controls the intermittent operation timing in the PLL circuit 31.
The S is output to the PLL circuit 31 and the timer 33. Further, the decoder unit 15 sets the control signal PS to “H” based on the margin time Tp0 and the margin time t set in advance in the decoder unit 15 and the measurement time data input from the timer 33.
The timing for setting the i ″ is controlled, and the operation start timing of the PLL circuit 31 is controlled.

The PLL circuit 31 has a control signal Clock for controlling the set frequency value input from the decoder unit 15,
The PLL operation is controlled by Data and LE, and the intermittent operation timing is controlled by the control signal PS input from the decoder unit 15. The PLL circuit 31 is
The control signal PS input from the decoder unit 11 is “H
The PLL operation is started at the timing of "i", and the control voltage is applied from the out terminal to the VCO circuit 32 based on the result of comparing the frequency output input from the VCO circuit 32 to the fin terminal with the set frequency value. The output is controlled so as to output a constant frequency signal, and the PLL circuit 31 outputs a signal LD indicating that the VCO frequency in the PLL circuit 31 has reached the set value from the LD terminal to the timer 33 and the decoder. It is output to the unit 15.

The VCO circuit 32 outputs the oscillation signal of the set frequency to the processing circuit of the subsequent stage according to the voltage control signal input from the PLL circuit 31.

The timer 33 starts the PLL from when the control signal PS input from the decoder section 15 becomes "Hi".
The time until the signal LD is input from the circuit 31, that is, the time from the start of the PLL operation until the VCO frequency reaches the set value is measured, and the measured time data is output to the decoder unit 15.

Further, in FIG. 1, the decoder unit 15 is
It is determined whether or not the calling number of the calling signal input from the demodulation unit 14 matches its own identification number by referring to the ID-ROM 6 in which the identification number is registered in advance. If they match, the signal is received. Then, the call detection signal is output to the control unit 18, the sound signal is output to the sound unit 17, and the notification sound is output to notify that there is a call. Also,
The decoder unit 15 outputs the message information received together with the calling signal to the control unit 18 based on the request input from the control unit 18.

The ID-ROM 16 forms a memory area for registering its own identification number.

The sound output unit 17 is composed of an amplifier, a speaker, and the like, and outputs a notification sound for informing that there is a call from the speaker by the sound output signal input from the decoder unit 15.

The control unit 18 is composed of a CPU, a timer, an input register for holding key input operation data in the key input unit 21, and the like, and various control programs stored in the ROM 19 and received messages input from the decoder unit 15. RAM 20 for storing information and key input information
Are connected.

The control unit 18 controls each unit in the pager according to message information input from the decoder unit 15 and an input instruction signal input from the key input unit 21 based on various control programs stored in the ROM 19. Then
The message information received by the receiving process is stored in the RAM 20, the message information is read from the RAM 20, output to the LCD driver 22, and displayed on the LCD 13.

A ROM (Read Only Memory) 19 stores various control programs executed by the CPU in the control unit 18.

RAM (Random Access Memory) 20
Forms a memory area for storing received message information, and exchanges message information with the control unit 18.

The key input unit 21 is composed of a ten-key pad, a mode key, etc., and outputs an instruction of each key to the control unit 18.

The LCD driver 22 outputs and displays the key character pattern on the LCD 23 based on the message information input from the control unit 18.

Next, the operation of this embodiment will be described.

First, the operation of the intermittent radio receiver 10 in the initial state will be described with reference to the timing chart shown in FIG.

In the initial state, when receiving the data indicated by the diagonal lines in FIG. 2A, the decoder unit 15 preliminarily sets "Tp0>To" for the maximum To as in the conventional case. The control signal PS is set to "Hi" earlier than the reception timing by the margin time Tp0 set therein ((b) in the figure), and the operation of the PLL circuit 31 is started. At this time, in the timer 33 in the synthesizer 13, the control signal PS input from the decoder unit 15 is “H”.
The time measurement is started at the same time as i ”, and the PLL circuit 31
By ending the time measurement by the signal LD input from the above, the time To0 shown in FIG. 7C is measured and the measured time data (To0) is output to the decoder unit 15.

Next, from the initial state shown in FIG. 3 to the reception n timing shown in FIG. 4, the decoder section 15
Is the time Tp (n) (To
(n-1) + t) is earlier than the reception timing by the control signal P
S is set to “Hi” (see FIG. 9B), and the PLL circuit 31
To start the operation of.

The rising time To in the PLL circuit 31
4 is caused by changes in the ambient temperature and the power supply voltage, the rise time To does not significantly change in the time between two consecutive reception timings.
The margin time t indicated by can be set to be considerably small.

Therefore, the margin time Tp is set on the basis of the measured rise time To of the PLL circuit 31 at the immediately preceding reception timing.
In such a situation that the value increases, "Tp (n)> Tp (n-1)" at each reception timing, that is, the relationship of the rising time To is "To (n)> To (n-1). ) ”, And always
The PLL circuit 31 can be operated only for the unnecessary operation time of “Tp (n) −To (n) = t ± α”.

As a result, the unnecessary operation time of each reception timing in the intermittent radio receiver can be shortened, the battery saving efficiency can be improved, and the life of the battery built in the pager or the like can be extended. .

[0041]

According to the present invention, the unnecessary operation time of each reception timing in the intermittent radio receiver can be shortened, and the battery saving efficiency of the intermittent radio receiver can be improved. As a result, the life of the battery can be extended by using it for a pager or the like.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a pager to which an intermittent radio receiver of the present invention is applied.

FIG. 2 is a block diagram of the synthesizer shown in FIG.

FIG. 3 is a timing chart of signals of respective parts in the intermittent radio receiver in FIG. 1 in an initial state.

FIG. 4 is a timing chart of signals of respective parts in the intermittent radio receiver of FIG. 1 after the initial state.

FIG. 5 is a block diagram of a main part of a conventional intermittent radio receiver.

6 is a timing chart of signals of respective parts in the intermittent radio receiver of FIG.

[Explanation of symbols]

 11 antenna 12 receiving part 13 synthesizer 14 demodulating part 15 decoder part 16 ID-ROM 17 sound output part 18 control part 19 ROM 20 RAM 21 key input part 22 LCD driver 23 LCD 31 PLL circuit 32 VCO circuit 33 timer

Claims (1)

[Claims] 1. In an intermittent radio receiver for obtaining a required oscillation frequency signal by a phase-locked loop circuit, a measuring means for measuring a rise time of the phase-locked loop circuit, a rise time measured by the measuring means and a preset value. An intermittent radio receiver comprising: a control means for outputting an intermittent signal for operating the phase locked loop circuit to the phase locked loop circuit earlier than the reception timing by a time obtained by adding the margin time.