JPH06350132A - Semiconductor luminous element array - Google Patents

Semiconductor luminous element array

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Publication number
JPH06350132A
JPH06350132A JP16408493A JP16408493A JPH06350132A JP H06350132 A JPH06350132 A JP H06350132A JP 16408493 A JP16408493 A JP 16408493A JP 16408493 A JP16408493 A JP 16408493A JP H06350132 A JPH06350132 A JP H06350132A
Authority
JP
Japan
Prior art keywords
light emitting
layer
semiconductor
film
semiconductor crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16408493A
Other languages
Japanese (ja)
Inventor
Takehisa Koyama
剛久 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP16408493A priority Critical patent/JPH06350132A/en
Publication of JPH06350132A publication Critical patent/JPH06350132A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a high quality semiconductor luminous element array having uniform luminous element characteristics at low cost by forming a high resistance portion in the upper part of a semiconductor crystal layer through ion implantation, thus electrically separating a luminous element, forming electrodes on a flat surface, and thereby integrating such luminous elements at a higher density. CONSTITUTION:A buffer layer 3 and a reflection layer 4 are formed on a substrate 2, and a cladding layer 5, a luminous layer 6, a cladding layer 7 and a contact layer 8 are formed on the reflection layer 4 in this order. Ion implantation is performed using a Au film 9 as a mask to separate a luminous element 11. Electrodes 13 are led out through the upper face of a SiN reflection preventive film 12 formed on the upper face of a semiconductor crystal layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体発光素子アレイ
に係り、特に面発光型半導体発光素子を有する半導体発
光素子モノリシックアレイに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device array, and more particularly to a semiconductor light emitting device monolithic array having surface emitting semiconductor light emitting devices.

【0002】[0002]

【従来の技術】従来より、半導体発光素子を高密度に集
積してアレイ化したものが、光プリンタ用光源、あるい
は光を用いた情報処理用素子などに使用されている。近
年、プリンタの小型化高画質化により、発光素子のより
高い集積度が求められている。基板上に順次積層させた
半導体結晶層を電気的に分離して、発光素子を列状に形
成する半導体発光素子モノリシックアレイでは、発光素
子を分離する方法として、不純物拡散法や、メサ型エッ
チング法などが用いられている。
2. Description of the Related Art Conventionally, a semiconductor light emitting element integrated in high density to form an array has been used as a light source for an optical printer or an information processing element using light. In recent years, due to the miniaturization of printers and the improvement in image quality, higher integration of light emitting elements is required. In a semiconductor light-emitting element monolithic array in which light-emitting elements are formed in rows by electrically separating semiconductor crystal layers sequentially stacked on a substrate, impurity diffusion methods and mesa-type etching methods are used as methods for separating light-emitting elements. Are used.

【0003】不純物拡散法を用いた半導体発光素子アレ
イでは、拡散マスクと発光部分の半導体結晶層との界面
に不純物が拡散しやすく、発光部分にまで拡散が広が
り、発光出力が低下したり、発光素子間のばらつきが生
じたりして製造歩留まりが悪くなるという欠点があっ
た。そこで、基板表面に凹凸を形成して各発光素子を分
離するメサ型エッチング法が多く用いられている。
In a semiconductor light emitting device array using the impurity diffusion method, impurities are easily diffused at the interface between the diffusion mask and the semiconductor crystal layer in the light emitting portion, and the diffusion spreads to the light emitting portion, which lowers the light emission output or emits light. There is a drawback that the manufacturing yield is deteriorated due to variations among the elements. Therefore, a mesa-type etching method is widely used in which unevenness is formed on the substrate surface to separate each light emitting element.

【0004】次に、メサ型エッチング法による従来の半
導体発光素子アレイの一例を図3、及び図4と共に説明
する。図3は、従来の半導体発光素子アレイの一例の構
造を示す列方向の部分拡大断面図であり、図4は、従来
の半導体発光素子アレイの一例の構造を示す列方向に垂
直な方向の部分拡大断面図である。両図において、従来
例の半導体発光素子アレイ21は、n−GaAs基板2
上に、n−GaAsバッファ層3、n−Al0.45Ga
0.55Asとn−AlAsとを1組として、25組積層し
た反射層4、n−Al0.7 Ga0.3 Asクラッド層5、
p−Al0.3 Ga0.7 As発光層6、p−Al0.7 Ga
0.3 Asクラッド層7を順次積層した半導体結晶層を、
エッチングによる分離溝15によって分離した複数個の
発光素子11を有し、電極接合部を除く半導体結晶上
面、及び分離溝15表面には、SiN反射防止膜12が
形成してある。基板2の下面全面には電極13が設置し
てある。かつ個々の発光素子11のクラッド層7の上面
にはコンタクト層8を介して電極13を設置して、メサ
型のエッチング溝上を這うようにして電極13を引き出
してある。
Next, an example of a conventional semiconductor light emitting element array by the mesa type etching method will be described with reference to FIGS. 3 and 4. FIG. 3 is a partially enlarged sectional view in the column direction showing the structure of a conventional semiconductor light emitting device array, and FIG. 4 is a portion in the direction perpendicular to the column direction showing the structure of an example of a conventional semiconductor light emitting device array. It is an expanded sectional view. In both figures, the semiconductor light emitting element array 21 of the conventional example is an n-GaAs substrate 2
N-GaAs buffer layer 3 and n-Al 0.45 Ga
25 sets of reflective layers 4, n-Al 0.7 Ga 0.3 As clad layers 5, each including 0.55 As and n-AlAs as one set,
p-Al 0.3 Ga 0.7 As light emitting layer 6, p-Al 0.7 Ga
A semiconductor crystal layer in which 0.3 As clad layer 7 is sequentially laminated,
It has a plurality of light emitting elements 11 separated by a separation groove 15 by etching, and a SiN antireflection film 12 is formed on the upper surface of the semiconductor crystal except the electrode junction and the surface of the separation groove 15. An electrode 13 is provided on the entire lower surface of the substrate 2. In addition, an electrode 13 is provided on the upper surface of the clad layer 7 of each light emitting element 11 via a contact layer 8, and the electrode 13 is drawn out so as to crawl on the mesa type etching groove.

【0005】ここで、上記反射層4のそれぞれの膜は、
干渉によって反射率を最大にするよう選ぶ物で、発光層
6から基板2側に発光された光をこの反射層4によって
反射されて基板2による光吸収を無くするものである。
通常この膜厚dは、部材の屈折率をn、発光中心波長を
λpとしたとき膜厚dは次式で与えられる。 d=λp/4n また、組数を増やすことにより、反射層4の性能(最大
反射率)を向上することができる。
Here, each film of the reflection layer 4 is
The material is selected to maximize the reflectance by interference, and the light emitted from the light emitting layer 6 to the substrate 2 side is reflected by the reflective layer 4 to eliminate the light absorption by the substrate 2.
Usually, this film thickness d is given by the following equation when the refractive index of the member is n and the emission center wavelength is λp. d = λp / 4n Further, the performance (maximum reflectance) of the reflective layer 4 can be improved by increasing the number of sets.

【0006】SiN反射防止膜12は、出力される光の
光出力面での反射成分を干渉により除去し、透過率を最
大にする物であると共に、電極13と半導体結晶層との
間に介在させて、絶縁体としても働く。通常膜厚dは、
部材の屈折率をn1 、発光中心波長をλpとしたとき膜
厚dは次式で与えられる。 d=λp/4n1 また、屈折率の異なる膜をそれぞれ前述した膜厚dの条
件で、複数積層すれば更に反射防止の効果が得られる。
The SiN antireflection film 12 removes the reflected component of the output light on the light output surface by interference and maximizes the transmittance, and is interposed between the electrode 13 and the semiconductor crystal layer. Let it also work as an insulator. The normal film thickness d is
When the refractive index of the member is n 1 and the emission center wavelength is λp, the film thickness d is given by the following equation. d = λp / 4n 1 Further, if a plurality of films having different refractive indices are laminated under the conditions of the film thickness d described above, the effect of antireflection can be further obtained.

【0007】[0007]

【発明が解決しようとする課題】ところで、上述したよ
うな構造の従来例の半導体発光素子アレイ21におい
て、エッチングにより分離溝を形成する段階で、エッチ
ングは全方向に進む特性があるため、溝の必要な深さに
よって発光素子間に必要な距離の制約が大きい。しか
も、発光部分までエッチングが広がりやすく、エッチン
グ溝の形状は、ばらつきが生じやすい。従って、発光素
子の間隔を非常に小さくして、かつ発光素子の特性を均
一にする、高密度で高品質な半導体発光素子アレイを作
成することが困難であった。また、電極14は、メサ型
の分離溝上を這うようにして引き出しているので、蒸着
などによって電極14を形成させた場合、メサ型の肩の
部分が薄くなり、応力の影響で亀裂が入り易くなる為、
電極14の厚さにむらができ、電気抵抗にばらつきがで
きた。その結果、発光出力にばらつきが生じていた。ま
た、断線等の欠陥も生じ易くて、製造歩留まりが悪くな
るという欠点があった。
By the way, in the conventional semiconductor light emitting element array 21 having the above-described structure, when the isolation groove is formed by etching, the etching has a characteristic of advancing in all directions. The required depth greatly limits the distance between the light emitting devices. Moreover, the etching easily spreads to the light emitting portion, and the shape of the etching groove is likely to vary. Therefore, it has been difficult to produce a high-density and high-quality semiconductor light-emitting element array in which the distance between the light-emitting elements is extremely small and the characteristics of the light-emitting elements are uniform. Further, since the electrode 14 is pulled out so as to crawl on the mesa-shaped separation groove, when the electrode 14 is formed by vapor deposition or the like, the mesa-shaped shoulder portion becomes thin, and cracks easily occur due to the influence of stress. Because,
The thickness of the electrode 14 was uneven, and the electric resistance was varied. As a result, the light emission output varies. Further, there is a defect that defects such as disconnection are likely to occur and the manufacturing yield is deteriorated.

【0008】そこで、本発明は上記の点に着目してなさ
れたものであって、半導体結晶層を基板上に構成し、電
気的に分離して発光素子を複数個形成した半導体発光素
子アレイにおいて、より高密度に発光素子を集積して、
発光素子特性を均一にする高品質な半導体発光素子アレ
イを低コストで提供することを目的とする。
Therefore, the present invention has been made by paying attention to the above points, and in a semiconductor light emitting device array in which a semiconductor crystal layer is formed on a substrate and a plurality of light emitting devices are electrically isolated to form a plurality of light emitting devices. , By integrating light-emitting elements in higher density,
It is an object of the present invention to provide a high-quality semiconductor light emitting device array that makes the light emitting device characteristics uniform at low cost.

【0009】[0009]

【課題を解決するための手段】本発明の半導体発光素子
アレイは、基板上に、伝導型の異なる半導体結晶層で発
光層を挟み込むように接合して積層した半導体結晶層
を、電気的に分離して発光素子を複数個形成した半導体
発光素子アレイにおいて、前記半導体結晶層にイオンを
注入して前記発光素子を電気的に分離し、前記半導体結
晶層上面に、反射防止膜を形成し、前記複数の発光素子
に接続する一方側の各々の電極を前記反射防止膜上面を
通って引き出した構成としたことにより上述の目的を達
成するものである。
In the semiconductor light emitting device array of the present invention, a semiconductor crystal layer in which semiconductor light emitting layers having different conductivity types are bonded and sandwiched so as to sandwich a light emitting layer on a substrate is electrically separated. In the semiconductor light emitting device array having a plurality of light emitting devices formed therein, ions are injected into the semiconductor crystal layer to electrically separate the light emitting devices, and an antireflection film is formed on the upper surface of the semiconductor crystal layer. The above-mentioned object is achieved by adopting a configuration in which each electrode on one side connected to a plurality of light emitting elements is drawn out through the upper surface of the antireflection film.

【0010】[0010]

【実施例】以下、図1、図2を参照して本発明の一実施
例を説明する。なお、上述した従来例と同様の構成部
分、または従来例と対応する構成部分には、同様の符号
を用いてその説明を省略することがある。図1は、本発
明の半導体発光素子アレイの一実施例の構造を示す部分
拡大平面図で、図2は、本発明の半導体発光素子アレイ
の一実施例の構造を示す列方向の部分拡大断面図であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The same components as those of the above-described conventional example or components corresponding to those of the conventional example are denoted by the same reference numerals, and the description thereof may be omitted. FIG. 1 is a partially enlarged plan view showing a structure of an embodiment of a semiconductor light emitting device array of the present invention, and FIG. 2 is a partially enlarged sectional view in a column direction showing a structure of an embodiment of a semiconductor light emitting device array of the present invention. It is a figure.

【0011】両図において、半導体発光素子アレイ1
は、まずn−GaAs基板2上に、Seを添加しキャリ
ア濃度が2×1018cm-3で膜厚0.5μm のn−GaA
sバッファー層3を積層し、続いてSeを添加しキャリ
ア濃度が2×1018cm-3で膜厚が51nmのn−Al0.45
Ga0.55Asと膜厚59nmのn−AlAsとを1組とし
て、25組積層した反射膜4を積層する。
In both figures, the semiconductor light emitting device array 1 is shown.
First, n-GaA having a carrier concentration of 2 × 10 18 cm −3 and a film thickness of 0.5 μm was prepared by adding Se onto the n-GaAs substrate 2.
s buffer layer 3 is laminated, and then Se is added to make n-Al 0.45 having a carrier concentration of 2 × 10 18 cm −3 and a film thickness of 51 nm.
The reflective film 4 is formed by stacking 25 sets of Ga 0.55 As and n-AlAs having a film thickness of 59 nm as one set.

【0012】さらに反射膜4上に、Seを添加しキャリ
ア濃度が1×1018cm-3で膜厚が5μm のn−Al0.7
Ga0.3 Asクラッド層5と、Znを添加しキャリア濃
度が5×1017cm-3で膜厚が0.5μm のp−Al0.3
Ga0.7 As発光層6と、Znを添加しキャリア濃度が
8×1017cm-3で膜厚が2μm のp−Al0.7 Ga0.3
Asクラッド層7と、Znを添加しキャリア濃度が3×
1018cm-3で膜厚が0.1μm のp−GaAsコンタク
ト層8とを積層する。これらはすべて有機金属気相成長
法(MOCVD法)または、分子線エピタキシー法(M
BE法)等を用いて行う。
Further, Se is added on the reflective film 4 to make n-Al 0.7 having a carrier concentration of 1 × 10 18 cm -3 and a film thickness of 5 μm.
Ga 0.3 As clad layer 5 and Zn-added p-Al 0.3 with a carrier concentration of 5 × 10 17 cm -3 and a film thickness of 0.5 μm.
Ga 0.7 As light emitting layer 6 and Zn-added p-Al 0.7 Ga 0.3 with a carrier concentration of 8 × 10 17 cm -3 and a film thickness of 2 μm.
As clad layer 7 and Zn are added so that the carrier concentration is 3 ×
A p-GaAs contact layer 8 having a thickness of 10 18 cm −3 and a thickness of 0.1 μm is laminated. These are all metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (M
BE method) or the like.

【0013】続いて蒸着法またはスパッタ法により半導
体層上にAu膜9を積層し、フォトレジスト膜を塗布す
る。リソグラフィー技術を用いフォトレジスト膜に所望
のパターンを形成する。レジスト膜によってマスクされ
ていない部分のAu膜は、イオンミリング法や、スパッ
タ法によって除去する。続いて残ったAu膜9をエッチ
ングマスクとして、プロトン照射を行い、マスク外の部
分に表面から3μm の深さまでの高抵抗部分10を形成
して発光素子11を分離させる。リソグラフィー技術、
スパッタ法を用いAu膜の一部分を削除し、電極として
用いる。アンモニアと過酸化水素水の混合溶液からなる
エッチング液により、Au膜9との接合部分を残して、
p−GaAsコンタクト層8を取り除いた後、気相成長
法(CVD法)により、絶縁膜でもあるSiN反射防止
膜12を膜厚97nmで、p−Al0.7 Ga0.3 Asクラ
ッド層7上面全体に形成する。
Subsequently, an Au film 9 is laminated on the semiconductor layer by vapor deposition or sputtering, and a photoresist film is applied. A desired pattern is formed on the photoresist film using a lithography technique. The part of the Au film which is not masked by the resist film is removed by the ion milling method or the sputtering method. Subsequently, using the remaining Au film 9 as an etching mask, proton irradiation is performed to form a high resistance portion 10 up to a depth of 3 μm from the surface on the portion outside the mask to separate the light emitting element 11. Lithography technology,
A part of the Au film is removed by using the sputtering method and used as an electrode. An etching solution composed of a mixed solution of ammonia and hydrogen peroxide water is used to leave a bonding portion with the Au film 9
After removing the p-GaAs contact layer 8, a SiN antireflection film 12 which is also an insulating film is formed to a film thickness of 97 nm on the entire upper surface of the p-Al 0.7 Ga 0.3 As clad layer 7 by a vapor phase growth method (CVD method). To do.

【0014】次に、リソグラフィー技術、及びスパッタ
リングにより、反射防止膜12上面に、発光素子11上
に残されたAu膜9に接続して引き出すようにした電極
13を、基板2下面全面に電極14を形成させる。
Next, an electrode 13 is formed on the upper surface of the antireflection film 12 by a lithographic technique and sputtering so as to be connected to the Au film 9 left on the light emitting element 11 and drawn out. To form.

【0015】以上のような構成よりなる本発明の一実施
例の半導体発光素子アレイ1は、イオンの注入によっ
て、半導体結晶層上部に高抵抗部分10を形成して、発
光素子を電気的に分離したものであって、このイオンの
量、深さは、正確に制御でき、イオンに与えるエネルギ
ーを制御することによって進入深さの制御が容易で、照
射されたイオンは、直進性が強いので発光部分にまで広
がらない。従って、発光素子の特性に影響を及ぼすこと
なく、発光素子間隔を小さくすることができ、より多く
の発光素子に分離することができる。つまり、非常に高
密度に発光素子が集積された高品質な半導体発光素子ア
レイを提供することができる。また、電極13は、平坦
なSiN反射防止膜12上に形成するので、容易に電極
13の厚さを均一にすることができ、電極13電気抵抗
のばらつきを少なくすることができる。その結果、発光
出力も均一化することができる。また、電極13の断線
等の欠陥が減少し、製造歩留まりが向上する。
In the semiconductor light emitting device array 1 of one embodiment of the present invention having the above-described structure, the high resistance portion 10 is formed on the semiconductor crystal layer by ion implantation to electrically separate the light emitting devices. The amount and depth of the ions can be accurately controlled, and the penetration depth can be easily controlled by controlling the energy applied to the ions. Does not spread to the part. Therefore, it is possible to reduce the distance between the light emitting elements without affecting the characteristics of the light emitting elements, and it is possible to divide the light emitting elements into more light emitting elements. That is, it is possible to provide a high-quality semiconductor light emitting element array in which light emitting elements are integrated in a very high density. Moreover, since the electrode 13 is formed on the flat SiN antireflection film 12, the thickness of the electrode 13 can be easily made uniform, and variations in the electric resistance of the electrode 13 can be reduced. As a result, the light emission output can be made uniform. Moreover, defects such as disconnection of the electrode 13 are reduced, and the manufacturing yield is improved.

【0016】なお、本実施例で用いた具体的な数値や、
材料名等は説明のために使用したにすぎないものであっ
て、本発明に係わる半導体発光素子アレイは、それらに
限定されることはなく、半導体発光素子アレイが使用さ
れる状況において適宜変更可能である。
The specific numerical values used in this embodiment and
The material names and the like are used only for the purpose of explanation, and the semiconductor light emitting element array according to the present invention is not limited to them, and can be appropriately changed in a situation where the semiconductor light emitting element array is used. Is.

【0017】[0017]

【発明の効果】本発明に係る半導体発光素子アレイは、
発光素子がより高密度に集積されて、しかも、発光特性
の優れた高品質なものであり、低コストで提供可能であ
る。
The semiconductor light emitting device array according to the present invention is
Since the light emitting elements are integrated with higher density and have high quality with excellent light emitting characteristics, it can be provided at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体発光素子アレイの一実施例の構
造を示す部分拡大平面図である。
FIG. 1 is a partially enlarged plan view showing the structure of an embodiment of a semiconductor light emitting device array of the present invention.

【図2】本発明の半導体発光素子アレイの一実施例の構
造を示す列方向の部分拡大断面図である。
FIG. 2 is a partially enlarged sectional view in a column direction showing a structure of an embodiment of a semiconductor light emitting device array of the present invention.

【図3】従来の半導体発光素子アレイの一例の構造を示
す列方向の部分拡大断面図である。
FIG. 3 is a partially enlarged sectional view in a column direction showing a structure of an example of a conventional semiconductor light emitting element array.

【図4】従来の半導体発光素子アレイの一例の構造を示
す列方向に垂直な方向の部分拡大断面図である。
FIG. 4 is a partial enlarged cross-sectional view in a direction perpendicular to a column direction, showing a structure of an example of a conventional semiconductor light emitting device array.

【符号の説明】[Explanation of symbols]

1 半導体発光素子アレイ 2 基板 4 反射層 5 クラッド層(半導体結晶層) 6 発光層 7 クラッド層(半導体結晶層) 8 コンタクト層 9 Au膜 10 高抵抗部分 11 発光素子 12 反射防止膜 13 電極 1 Semiconductor Light Emitting Element Array 2 Substrate 4 Reflective Layer 5 Clad Layer (Semiconductor Crystal Layer) 6 Light Emitting Layer 7 Clad Layer (Semiconductor Crystal Layer) 8 Contact Layer 9 Au Film 10 High Resistance Part 11 Light Emitting Element 12 Antireflection Film 13 Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板上に、伝導型の異なる半導体結晶層で
発光層を挟み込むように接合して積層した半導体結晶層
を、電気的に分離して発光素子を複数個形成した半導体
発光素子アレイにおいて、 前記半導体結晶層にイオンを注入して前記発光素子を電
気的に分離し、前記半導体結晶層上面に、発光波長の透
過率を最大にするような反射防止膜を形成し、前記複数
の発光素子に接続する一方側の各々の電極を前記反射防
止膜上面を通って引き出したことを特徴とする半導体発
光素子アレイ。
1. A semiconductor light-emitting element array in which a plurality of light-emitting elements are formed by electrically separating a semiconductor crystal layer, which is formed by bonding and laminating a light-emitting layer between semiconductor crystal layers having different conductivity types, on a substrate. In, in order to electrically separate the light emitting element by implanting ions into the semiconductor crystal layer, an antireflection film that maximizes the transmittance of the emission wavelength is formed on the upper surface of the semiconductor crystal layer, A semiconductor light emitting device array, wherein each electrode on one side connected to the light emitting device is drawn out through the upper surface of the antireflection film.
JP16408493A 1993-06-08 1993-06-08 Semiconductor luminous element array Pending JPH06350132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16408493A JPH06350132A (en) 1993-06-08 1993-06-08 Semiconductor luminous element array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16408493A JPH06350132A (en) 1993-06-08 1993-06-08 Semiconductor luminous element array

Publications (1)

Publication Number Publication Date
JPH06350132A true JPH06350132A (en) 1994-12-22

Family

ID=15786478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16408493A Pending JPH06350132A (en) 1993-06-08 1993-06-08 Semiconductor luminous element array

Country Status (1)

Country Link
JP (1) JPH06350132A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924502B2 (en) 2000-06-21 2005-08-02 Sharp Kabushiki Kaisha Semiconductor light emitting device for stably obtaining peak wave length of emission spectrum
JP2007208041A (en) * 2006-02-02 2007-08-16 Shinko Electric Ind Co Ltd Semiconductor device and method for manufacturing the same
US7964884B2 (en) * 2004-10-22 2011-06-21 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924502B2 (en) 2000-06-21 2005-08-02 Sharp Kabushiki Kaisha Semiconductor light emitting device for stably obtaining peak wave length of emission spectrum
US7964884B2 (en) * 2004-10-22 2011-06-21 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same
US7999279B2 (en) 2004-10-22 2011-08-16 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same
US8008101B2 (en) 2004-10-22 2011-08-30 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same
US8039861B2 (en) 2004-10-22 2011-10-18 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same
US8143640B2 (en) 2004-10-22 2012-03-27 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same
US8274094B2 (en) 2004-10-22 2012-09-25 Seoul Opto Device Co., Ltd. GaN compound semiconductor light emitting element and method of manufacturing the same
JP2007208041A (en) * 2006-02-02 2007-08-16 Shinko Electric Ind Co Ltd Semiconductor device and method for manufacturing the same

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