JPH06350091A - Structure and manufacture of dmos provided with large durability against latch-up - Google Patents

Abstract

PURPOSE: To provide a doubly-diffused MOS(DMOS) device, having resistance against a drain dV/dt, higher than that endured by conventional DMOS devices, until the occurrence of latch up. CONSTITUTION: A plurality of source regions (e.g. 12) in a DMOS device are interconnected with P-conductive type regions (e.g. 15) at the corners. By this arrangement, parasitic bipolar transistor operation which causes latch up in a high dV/dt condition can be suppressed, and higher resistance against avalanche energy can be attained.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to metal-oxide-semiconductor devices, and more particularly to double-diffused metal-oxide-semiconductor devices.

[0002]

2. Description of the Related Art Conventional double-diffused metal-oxide-semiconductor (DM)
OS) device breaks down DMOS device (break dow
n) and destroys the parasitic bipolar transistor
Olar transistor) is adversely affected. Typically, parasitic bipolar transistors, when energized,
DMOS when this parasitic bipolar transistor is turned off
Has a lower breakdown voltage than the device can withstand.

For example, FIG. 1 shows an N-channel DMOS.
A schematic cross-section of a portion of a transistor is shown. This DM
The OS transistor has a source, a drain and a gate, and a channel for this transistor is shown to be formed between the N + type region and the N type drain when the surface of the P type layer is inverted by an appropriate voltage on the gate. Be done. Parasitic NPN bipolar transistors are shown for simplicity with respective emitters and collectors of the source and drain of the DMOS transistor. The base of this bipolar transistor is formed by the P layer. When excess carriers in the bulk of the device (N-type drain region) are swept into the junction of the N + and P-type layers (emitter-collector region of the parasitic bipolar transistor), the parasitic bipolar transistor is forward biased. This typically occurs when the drain voltage of a DMOS device changes too quickly. For example, when switching a highly inductive load, the drain voltage changes at a rate of hundreds of volts per microsecond, which makes this parasitic bipolar transistor conductive and, if no precaution is taken. , DMOS
Destroy the transistor. This also occurs when carriers are generated by avalanche breakdown of N-type region / P-type layer junctions. This also applies to other MOS control transistors, for example insulated gate bipolar transistors (IGBTs).

[0004]

Accordingly, there is a need to provide a DMOS (or IGBT) device that is highly resistant to damage from fast drain (collector) voltage transitions and avalanche breakdown. Furthermore, a DMOS having a higher avalanche energy endurance for a given drain (collector) voltage breakdown or transition current.
(Or IGBT) devices are required to be provided.

[0005]

These and other objects of the invention are achieved in accordance with claims 1 and 7.
The foregoing features of the invention, as well as the invention itself, can be more fully understood from the following detailed description of the drawings.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention can be generally understood from FIG. 2, in which a MOS control transistor 10 is a substrate 11 of a first conductivity type having a main (top) surface, and a main surface of the substrate 11 Laterally displaced of a second conductivity type extending to a depth
Main body (first) region 12, main body (first) region 12 extending from the main surface of substrate 11 to a depth shallower than the first depth
A second region 13 of the first conductivity type in each of the above, and a conductive gate layer 14 overlying the major surface of the substrate 12 between these body (first) regions 12. Further, the transistor 10 is a body (first) disposed in the substrate 11.
It includes a third region 15 of a second conductivity type that interconnects regions 12.

More specifically, transistor 10 is embodied herein using oxide layer 16 to dielectrically isolate pockets of silicon material 17 in substrate 11 from bulk substrate 11. Transistor 10 need not necessarily utilize dielectric isolation, although dielectric isolation is effective for integrated circuit fabrication using transistor 10 shown herein. The pockets of material 17 have a wide resistivity range, and the low resistivity buried layer 18 helps form a low resistance contact to the rest of the material 17. Layer 1
The portion above the buried layer 18 of No. 7 is referred to herein as the common drain layer 19, the purpose of which will be described later.

Formed in the main surface (top) of layer 19 are a plurality of regions 12, here referred to as body regions 12, of opposite conductivity type to that of layer 19. A smaller area 13 is formed in the body area 12.
Region 13 is of the same conductivity type as that of layer 19.
At the approximate center of the body region is a deeper portion 24 having the same conductivity type as that of body region 12. The resistivity of this deep portion 24 is lower than that of the body region 12, and the resistivity of region 13 is lower than both of them. The depth below the surface of layer 19 in body region 12 is in region 1
The depth of the body region 12 at the approximate center is deeper than at the periphery.
The combination of regions 12 and 13, as will be explained later,
"Source" or "emitter" for transistor 10
To form.

Body region 12 interconnecting body regions 12
There is a region 15 with the same conductivity type as, but for this purpose it will be explained in detail later. As a result of this, an interconnected grid of body regions 12 is formed with "open" regions of layer 19 at its surface between body regions 12. Preferably, region 15 is formed at the same time that body region 12 is formed.

At the center of the body region 12, the region 1
There is a low resistance layer 25 extending along the surface of 2 and 15. Layer 25 makes a low resistance contact between metal layer 21 (discussed below) and body region 12 and helps reduce the resistance along region 15 between the plurality of body regions 12. The resistivity of layer 25 is preferably lower than the bulk resistance of regions 12 and 15 and body regions 12 and 1
It has the same conductivity type as 5. Note that layer 25 is not absolutely necessary and can be removed from region 12 and / or region 15.

Transistor 1 covering the surface of layer 19
There is a grid of interconnected polysilicon runners 14 forming a zero gate. Each of the runners 14 is encapsulated within a gate oxide layer 20 of insulator and a second later formed insulating layer 20 '. Insulators 20 and 20 'are runners 1
4 has the function of isolating it from the conductive material surrounding it. The runner 14 and oxide layers 20, 20 'are disposed on the surface of layer 19 such that regions 12 and 13 are "exposed" for later contact, as will be described later. Preferably, runner 14 is formed from a layer of low resistivity (highly doped) polysilicon having openings therein to expose regions 12 and 13.

Note that in order for the polysilicon runners 14 to be interconnected, there must be a location where the polysilicon runners 14 are bonded together. The bonding is typically performed at the corners and, as shown in FIG. 2, the underlying region 15 is not formed by regions 15 that are not present at the corners of region 12. The reason for this will become more apparent later in connection with the discussion of the steps of the manufacturing process as an example of the description.

A metal layer 21 covers polysilicon runner 14 for contacting regions 12 and 13 across transistor 10. Metal layer 21 functions as a "source" or "emitter" contact for transistor 10. Note that both regions 12 and 13 are connected (shorted) to each other by the metal layer 21. Metal runner 23
Makes contact with the buried layer 18 through the contact layer 22 and forms a "drain" or "collector" for the transistor 10. If the conductivity type of buried layer 18 is the same as that of layer 19, then transistor 10
Is a DMOS transistor. However, if the conductivity type of buried layer 18 is the opposite of the conductivity type of layer 19, then transistor 10 is an insulated gate bipolar transistor (IGGT). In either case, the transistor 10
Is a MOS control transistor. To reduce the parasitic bipolar effect described above, region 15 interconnects body regions 12 to reduce the gain of the parasitic bipolar transistor,
This is accomplished by shorting body regions 12 together and helping to collect excess carriers from layer 19 that would otherwise cause forward biasing of the parasitic transistors in transistor 10.

Another implementation of the invention is shown in FIG. The transistor 30 includes a base region 12, a region 13,
It is similar to the transistor 10 shown in FIG. 2 except for the structure of the low resistivity layer 25 and the deep region 24. More specifically,
The deep region 24 substantially creates the connection region 15 and joins the body regions 12 together. Here, layer 25, which is closer to the region than the layer, is confined to the approximate center of the surface of body region 12 and need not extend along the surface of regions 12 and 15. Region (layer) 2 corresponding to opposite conductivity type 13
Surrounding 5 and located entirely within the body region 12. Thus, a channel for the transistor 30 described above is formed across the surface of the body region 12 between the region 13 and the common layer 19. The depth of deep region 24 is deeper than or equal to the depth of body region 12, the resistivity of deep region 24 is less than that of body region 12, and the resistivity of region 13 is Note that it is lower than both.

[0015] In more detail fabrication step as an example, the transistor 10 in FIG. 2 is manufactured by the following process as an example. Starting with a substrate 11 having a layer 17 of a first conductivity type silicon (eg N type) having a buried layer 18, a patterned photoresist (not shown) is deposited on the surface of the layer 17, Contact region 22 connected to the buried layer 18
Are first formed, for example, by implanting a dopant having the same conductivity type as that in the buried region 18. The buried layer 22 and the contact layer 22 are, for example, N type and I type for the DMOS transistor 10.
It is of P type for GBT.

The photoresist is removed, another photoresist is deposited, and deep regions 24 therein are patterned to create openings formed by implanting P-type dopants. The photoresist is removed and a thin oxide layer 20 is grown on layer 17, this thickness being the desired gate oxide thickness of transistor 10.
Next, a layer of polysilicon is deposited on the oxide layer 20,
Doped to have low resistance. Polysilicon is patterned to create a grid-like gate structure 14 having openings therein to expose the surface layer 19. As mentioned above, the lattice of the gate layer 14 is "complete.
e) "or" continuous "lattice.
That is, interconnects in the lattice are removed at various locations to form regions 15, as described below.

Body region 12 is formed by implanting P dopants in layer 19 using polysilicon as a mask. Sufficient implantation (eg 1200
(C for 200 minutes), the typical depth of body region 12 extends from the surface of layer 19 by approximately 4 microns, for example. For deep regions 24, typical depths extend up to about 6 microns by way of example. Next, a photoresist is deposited and patterned to expose the surface of the substrate 11, where a shallow low resistivity layer 25 is formed later.
It is formed by implanting a high concentration of a type of dopant. The photoresist is then removed and another photoresist is deposited so that the surface of layer 19 in body region 12 is exposed to form region 13 by heavily implanting N-type dopants. Patterned. These openings in the photoresist are arranged so that the formed region 13 does not significantly impinge on the channel portion of the body region 12 as described above. The photoresist is then removed.

Next, silicon dioxide, P-glass or boro-phosphosilicate glass, B
A PG) passivation layer 20 ′ is deposited and patterned to leave a layer above the polysilicon 14. The oxide layer 20 on the body region 12 is then removed and a metal layer 21 is deposited.

For transistor 30 of FIG. 3, the processes described above are performed substantially simultaneously. Process differences include implant forming body region 12, deep region 24 and shallow low resistivity region 25. For transistor 30, the body region implant is limited to forming region 12 and the deep region implant continues beyond region 12 to form region 15. The implant forming region 25 is now restricted to the approximate center of region 12 for the low resistance contact between metal 21 and body region 12. As is clear from FIG. 3, this is not a requirement, but region 13
Surrounds region 25.

An exemplary result DMOS transistor 10 was formed in substrate 11 using the following doping concentrations and sizes. Body area 12 P type, 480 ohm / square area 13 N type, 20 ohm / square layer 19 N type, 4-5 ohm-cm deep area 24 P type, 80 ohm / square shallow area 25 P type, 80 ohm / square

If one has an area 15 and the other uses substantially the same DMOS transistor 10 without it, each driving an inductive load, the device with the area 15 will have the area Much more robust than the equivalent device without the 15. The amount of energy (avalanche energy) dissipated in the test transistor when switching the inductive load was measured using industry standard measurement methods. Avalanche energy is expressed as the product of the breakdown voltage of the device and the total charge applied to the device. For the purposes here, the total charge is at the time of avalanche,
It is defined as the product of the current injected into the device and the time that the current is applied to a near "square" pulse of current. As a result of the measurement, the DMOS transistor having the region 15 required about 10 times as much avalanche energy before the transistor was destroyed as compared with the transistor having no region 15. It has also been discovered that the latching current for the IGBT increases as well when the region 15 is added to the conventional IGBT structure.

While the preferred implementation of the invention has been described, it will be appreciated by those skilled in the art that other implementations incorporating the inventive concept may be used. Therefore, the present invention is not limited to the disclosed implementations, but only by the spirit and scope of the appended claims.

[Brief description of drawings]

FIG. 1 DM as an example showing a parasitic bipolar transistor.
It is a schematic sectional drawing of an OS transistor.

FIG. 2 is a schematic cross-sectional view of the first embodiment of the present invention.

FIG. 3 is a schematic sectional view of a second embodiment of the present invention.

[Explanation of symbols]

 10 MOS Control Transistor 11 Substrate 12 First Region 13 Second Region 14 Conductive Gate Layer

Claims (11)

[Claims] 1. A MOS control transistor (eg, 1
0) wherein the transistor is: a substrate of a first conductivity type having a major surface (eg 17); a plurality of second conductivity types extending from the major surface of said substrate to a first depth. A first region laterally spaced (eg, 1
2); and a second region of the first conductivity type (eg, 13 present in each of the first regions and extending from the major surface of the substrate to a depth less than the first depth). ); And the transistor further comprises: a third region (eg, 15) of a second conductivity type disposed in the substrate for interconnecting the first region. 2. The first region is arranged in rows and columns, and the third region interconnects any given first region to a first region immediately adjacent thereto. The transistor according to claim 1, wherein: 3. A metal conductor (eg, 21) for interconnecting the plurality of first regions to make contact with the first regions to form terminals of a transistor is further included; The transistor of claim 2 wherein said metal conductor contacts within each of said first regions a second region therein. 4. The transistor according to claim 3, wherein the resistivity of the third region is smaller than the resistivity of the substrate. 5. A fourth region of the first conductivity type (eg, 18, 2) disposed in the substrate and forming a terminal of a transistor spaced apart from the first region.
The transistor of claim 4, further comprising 2). 6. A fourth region (eg, 18, 22) disposed within said substrate and forming a terminal of said first spaced apart transistor is further included. Item 4 transistor. 7. A method of manufacturing a MOS control transistor (eg 10) having a substrate of a first conductivity type (eg 17) having a major surface, the method comprising: the major surface of said substrate. Forming a plurality of laterally spaced first regions (eg, 12) of a second conductivity type extending from the first to the first depth; and within each of the first regions described above. Forming a region (eg, 13) of a first conductivity type extending from the major surface of the substrate to a depth less than said first depth; the method further comprises: Forming a third region (eg, 15) of a second conductivity type for contacting the first region and interconnecting the first region. the method of. 8. The method further comprises depositing a metal conductor (eg, 21) for contacting said first and said second regions; said conductors defining said first and second regions. The method for manufacturing a transistor of claim 7, wherein the method comprises interconnecting to form a first terminal of the transistor. 9. The third region has a resistivity less than that of the substrate; and the first region is a given first region in which the third region is. 9. The method for manufacturing a transistor of claim 8 arranged in rows and columns to interconnect with the immediately adjacent first region. 10. A fourth region of a first conductivity type disposed in the substrate and forming a second terminal of a transistor located away from the first region (eg,
18. The method for manufacturing a transistor of claim 9, further comprising the step of forming 18, 22). 11. A fourth region of a second conductivity type (eg, a second region) disposed in the substrate and forming a second terminal of a transistor located away from the first region.
18. The method for manufacturing a transistor of claim 9, further comprising the step of forming 18, 22).