JPH06349990A - Manufacture of resin-sealed semiconductor element using lead frame - Google Patents
Manufacture of resin-sealed semiconductor element using lead frameInfo
- Publication number
- JPH06349990A JPH06349990A JP5139694A JP13969493A JPH06349990A JP H06349990 A JPH06349990 A JP H06349990A JP 5139694 A JP5139694 A JP 5139694A JP 13969493 A JP13969493 A JP 13969493A JP H06349990 A JPH06349990 A JP H06349990A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- resin
- chip
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、表面実装用の半導体素
子を対象に、リードフレームを用いて組立てたＴＯタイ
プの樹脂封止型半導体素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a TO type resin-sealed semiconductor element, which is a surface mount semiconductor element and is assembled by using a lead frame.
【０００２】[0002]
【従来の技術】まず、頭記半導体素子の従来における製
造方法を図３により説明する。なお、図中で１はリード
フレーム、１ａはリードフレームのチップマウント部、
１ｂはチップマウント部１ａから同一方向に引出した外
部リード部、１ｃは外部リード部１ｂの相互間を連結し
たタイバー、１ｄはリードフレーム１のピッチ送り穴、
２は半導体チップ、３はボンディングワイヤ、４は封止
樹脂を示す。そして、半導体素子を組み立てるには、ま
ず（ａ),（ｂ）図で示すようにリードフレーム１のチッ
プマウント部１ａに半導体チップ２をマウントし、続い
て半導体チップ２と外部リード部１ｂとの間にワイヤ３
をボンディングする。次にこの組立体をトランスファモ
ールド金型に挿入し、（ｃ）図のようにリードフレーム
上で半導体チップ２の周域を樹脂４で封止するようモー
ルド成形した後、さらにリードフレーム１のタイバー１
ｃをカットして（ｄ）図のように個片素子に分割する。2. Description of the Related Art First, a conventional method for manufacturing a semiconductor device will be described with reference to FIG. In the figure, 1 is a lead frame, 1a is a chip mount portion of the lead frame,
Reference numeral 1b is an external lead portion drawn out in the same direction from the chip mount portion 1a, 1c is a tie bar connecting the external lead portions 1b to each other, 1d is a pitch feed hole of the lead frame 1,
2 is a semiconductor chip, 3 is a bonding wire, and 4 is a sealing resin. Then, in order to assemble the semiconductor element, first, as shown in FIGS. (A) and (b), the semiconductor chip 2 is mounted on the chip mounting portion 1a of the lead frame 1, and then the semiconductor chip 2 and the external lead portion 1b are connected. Wire 3 in between
To bond. Next, this assembly is inserted into a transfer mold and molded as shown in (c) on the lead frame so that the peripheral area of the semiconductor chip 2 is sealed with resin 4, and then the tie bar of the lead frame 1 is further formed. 1
c is cut and divided into individual elements as shown in FIG.
【０００３】また、かかる半導体素子の製品は、プリン
ト配線板に対しピン挿入実装する仕様のものは（ｄ）図
のように外部リード部１ｂが真っ直ぐに伸びたまま市場
に供給するのに対し、表面実装仕様のものについては、
（ｄ）図の半導体素子製品に対して２次加工を行い、
（ｅ）図のように封止樹脂４から突出した外部リード部
１ｂのアウタ部分にリード曲げ加工を施すとともに、チ
ップマウント部１ａ，および外部リード部１ｂの不要部
分をＸ−Ｘラインに沿いカットして表面実装用の半導体
素子を得るようにしている。In addition, as for the product of such a semiconductor device, the product of the specification of inserting the pin into the printed wiring board is supplied to the market while the external lead portion 1b is extended straight as shown in FIG. For surface mount specifications,
Secondary processing is applied to the semiconductor device product shown in (d),
(E) As shown in the figure, the outer portion of the external lead portion 1b protruding from the sealing resin 4 is subjected to lead bending processing, and unnecessary portions of the chip mount portion 1a and the external lead portion 1b are cut along the XX line. Then, a semiconductor element for surface mounting is obtained.
【０００４】[0004]
【発明が解決しようとする課題】ところで、前記のよう
にリード曲げ加工を２次加工として樹脂封止された半導
体素子の製品に対して行うようにした従来の製造方法で
は、リード曲げ加工に伴って加わる応力により、樹脂パ
ッケージと外部リードとの接着面が剥離したり、樹脂パ
ッケージに亀裂が入るなどの欠陥が多々発生し、このこ
とが製品の良品率，信頼性を低下させる大きな原因とな
っている。By the way, in the conventional manufacturing method in which the lead bending process is performed on the resin-encapsulated semiconductor element product as the secondary process as described above, the lead bending process is accompanied by Due to the applied stress, many defects such as peeling of the adhesive surface between the resin package and external leads and cracking of the resin package occur, which is a major cause of lowering the yield rate and reliability of the product. ing.
【０００５】本発明は上記の点にかんがみなされたもの
であり、その目的は頭記した半導体素子を対象に、前記
課題を解決して高信頼性の製品を生産性よく製造できる
ようにした樹脂封止型半導体素子の製造方法を提供する
ことにある。The present invention has been made in view of the above points, and a purpose thereof is a resin for the above-mentioned semiconductor element to solve the above-mentioned problems and to manufacture a highly reliable product with high productivity. It is to provide a method for manufacturing a sealed semiconductor device.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の製造方法は、外部リード部にあらかじめ所
定のリード曲げ加工を施したリードフレームに対して、
該リードフレームのチップマウント部に半導体チップを
マウントし、かつ半導体チップと外部リード部との間に
ワイヤボンディングを施した後に、リードフレーム上で
半導体チップの周域を樹脂封止し、さらにタイバーをカ
ットして個別素子に分割して製造するものとする。In order to achieve the above object, the manufacturing method of the present invention is directed to a lead frame whose external lead portions are preliminarily subjected to a predetermined lead bending process.
After mounting the semiconductor chip on the chip mounting portion of the lead frame and performing wire bonding between the semiconductor chip and the external lead portion, the peripheral area of the semiconductor chip is resin-sealed on the lead frame, and a tie bar is further provided. It shall be manufactured by cutting and dividing into individual elements.
【０００７】そして、前記の製造方法においては、外部
リード部のアウタ側先端がチップマウント部の下面とほ
ぼ同じレベルに並ぶようにリード曲げ加工を施すものと
する。また、前記の製造方法で用いるリードフレームと
しては、チップマウント部，および該チップマウント部
から同一方向に引出した外部リード部を、向かい合わせ
に２列に配列してパターン形成したリードフレームを用
いることができる。In the manufacturing method described above, the lead bending process is performed so that the outer ends of the outer lead portions are arranged at substantially the same level as the lower surface of the chip mount portion. As the lead frame used in the above-mentioned manufacturing method, use is made of a pattern formed by arranging the chip mount part and the external lead parts drawn out in the same direction from the chip mount part in two rows facing each other. You can
【０００８】[0008]
【作用】上記のようにリード曲げ加工を、樹脂封止を行
う以前の段階であらかじめリードフレームに対して施し
ておくことにより、樹脂封止後にはリード曲げの２次加
工が必要なく、かつリード曲げの２次加工に起因する製
品の欠陥発生が回避されるので、これにより高信頼性の
製品が得られる。しかもリード曲げ加工は、１枚のリー
ドフレームを単位としてリードフレーム上に形成されて
いる複数組のパターンを一括して実施することができる
ので生産性も向上する。By performing the lead bending processing on the lead frame in advance before the resin sealing as described above, the secondary processing of the lead bending is not required after the resin sealing, and This avoids the occurrence of product defects due to the bending secondary processing, and thus provides a highly reliable product. In addition, since the lead bending process can be performed collectively for a plurality of sets of patterns formed on the lead frame in units of one lead frame, the productivity is also improved.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。なお、各実施例中で図３に対応する同一部材には
同じ符号が付してある。 実施例１：図１（ａ）〜（ｅ）において、まず（ａ）図
にパターン形成されたリードフレーム１の展開図を示
す。次に、リードフレーム１をプレス加工し、（ｂ）図
のようにリードフレームに対してチップマウント部１ａ
に沈み込み，および外部リード部１ｂに曲げ加工を施
す。この場合に、半導体素子の表面実装を考慮して外部
リード部１ｂのアウタ側先端部がチップマウント部１ａ
の下面と同一レベルに並ぶように曲げ加工を行うものと
する。続いてリードフレーム１の上でチップマウント部
１ａに半導体チップ２をマウントし、さらに（ｃ）図の
ように半導体チップ２と外部リード部１ｂとの間にワイ
ヤ３をボンディングした後、トランスファモールド法に
より、（ｄ）図のように半導体チップ２の周域に封止樹
脂４をモールド成形する。その後にリードフレーム１の
各外部リード部１ｂの間を連結しているタイバー１ｃを
カットし、（ｅ）図のような個別素子に分割された製品
が完成する。Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same members corresponding to those in FIG. 3 are designated by the same reference numerals. Example 1 In FIGS. 1A to 1E, first, a developed view of a lead frame 1 having a pattern formed is shown in FIG. Next, the lead frame 1 is pressed, and the chip mount portion 1a is attached to the lead frame as shown in FIG.
And the outer lead portion 1b is bent. In this case, in consideration of the surface mounting of the semiconductor element, the tip of the outer lead portion 1b on the outer side is the chip mount portion 1a.
Bending shall be performed so that it is aligned with the lower surface of the. Then, the semiconductor chip 2 is mounted on the chip mount portion 1a on the lead frame 1, and the wire 3 is further bonded between the semiconductor chip 2 and the external lead portion 1b as shown in FIG. Thus, the sealing resin 4 is molded in the peripheral area of the semiconductor chip 2 as shown in FIG. After that, the tie bar 1c connecting between the external lead portions 1b of the lead frame 1 is cut to complete a product divided into individual elements as shown in FIG.
【００１０】前記の製造工程から判るように、リード曲
げ加工は樹脂封止を実施する以前の段階でリードフレー
ム１に対しあらかじめ行うので、樹脂封止後はリード曲
げの２次加工が不要となる。したがって、封止樹脂４に
リード曲げ加工の影響が及ぶことがなく、外部リード部
１ｂと封止樹脂４との間には良好な接着状態が確保され
る。As can be seen from the above manufacturing process, the lead bending process is performed on the lead frame 1 before the resin sealing, so that the secondary process of the lead bending is not necessary after the resin sealing. . Therefore, the lead bending process does not affect the sealing resin 4, and a good adhesion state is secured between the external lead portion 1b and the sealing resin 4.
【００１１】実施例２：図２（ａ),（ｂ）は、実施例１
で述べた製造方法の工程に供給するリードフレームの応
用実施例を示すものである。この実施例では、生産性を
高める目的から１枚のリードフレーム１に対し、チップ
マウント部１ａ，外部リード部１ｂ，タイバー１ｃを組
とするパターンが、チップマウント部同士を突き合わせ
ようにして２列向かい合わせに形成されている。なお、
１ｅはチップマウント部１ａの間にまたがって形成した
連結部である。Example 2 FIGS. 2A and 2B show Example 1
9 shows an application example of the lead frame supplied to the steps of the manufacturing method described above. In this embodiment, for the purpose of improving productivity, one lead frame 1 is provided with a pattern in which the chip mount portions 1a, the external lead portions 1b, and the tie bars 1c are paired in two rows so that the chip mount portions abut each other. It is formed facing each other. In addition,
Reference numeral 1e is a connecting portion formed across the chip mount portions 1a.
【００１２】このように、１枚のリードフレーム１に組
立パターンを２列に並べて形成したリードフレームを用
いることにより、生産性が向上する。しかも、あらかじ
めリード曲げ加工を施したリードフレームは図３に示し
た従来のリードフレームと比べて幅寸法が短小となるの
で、図２のように２列配列としてパターン形成したリー
ドフレームを、既設のリードフレーム自動供給装置をそ
のまま利用して供給することが可能となる。As described above, by using the lead frame in which the assembly patterns are arranged in two rows on one lead frame 1, the productivity is improved. In addition, since the lead frame which has been subjected to the lead bending process in advance has a smaller width dimension than the conventional lead frame shown in FIG. 3, the lead frame patterned as a two-row array as shown in FIG. It is possible to use the lead frame automatic supply device as it is for supply.
【００１３】[0013]
【発明の効果】以上述べたように、本発明によれば、樹
脂封止を行う以前の段階であらかじめリードフレームに
対してリード曲げ加工を施しておくことにより、樹脂封
止後にはリード曲げの２次加工が必要なく、かつリード
曲げの２次加工に起因する製品の欠陥発生が回避される
ので、これにより高信頼性の製品を生産性よく提供する
ことができる。As described above, according to the present invention, the lead bending is performed on the lead frame in advance before the resin sealing, so that the lead bending after the resin sealing is performed. Since no secondary processing is required and the occurrence of product defects due to the secondary processing of lead bending is avoided, a highly reliable product can be provided with high productivity.
【図１】本発明の実施例１に対応する製造方法の説明図
であり、（ａ）はリードフレームの展開図、（ｂ）はリ
ード曲げ加工を施したリードフレームの側面図、（ｃ）
はリードフレームに半導体チップを搭載した状態図、
（ｄ）は樹脂封止を施した状態図、（ｅ）は完成した個
片素子の外観斜視図FIG. 1 is an explanatory view of a manufacturing method corresponding to a first embodiment of the present invention, (a) is a developed view of a lead frame, (b) is a side view of a lead frame subjected to lead bending processing, and (c).
Is a state diagram of mounting a semiconductor chip on a lead frame,
(D) is a state diagram in which resin sealing is applied, and (e) is an external perspective view of the completed individual element
【図２】本発明の実施例２に用いるリードフレームの構
成図であり、（ａ）は平面図、（ｂ）は側面図2A and 2B are configuration diagrams of a lead frame used in Embodiment 2 of the present invention, in which FIG. 2A is a plan view and FIG. 2B is a side view.
【図３】従来における製造方法の説明図であり、（ａ),
（ｂ）はリードフレームの平面図，側面図、（ｃ）は樹
脂封止後の組立状態図、（ｄ）は個片素子に分割した状
態図、（ｅ）はリード曲げなどの２次加工を施した半導
体素子の側面図FIG. 3 is an explanatory view of a conventional manufacturing method, (a),
(B) is a plan view and side view of the lead frame, (c) is an assembled state view after resin sealing, (d) is a state view divided into individual elements, and (e) is a secondary processing such as lead bending. Side view of semiconductor element
１ リードフレーム １ａ チップマウント部 １ｂ 外部リード部 １ｃ タイバー ２ 半導体チップ ３ ボンディングワイヤ ４ 封止樹脂 1 lead frame 1a chip mount part 1b external lead part 1c tie bar 2 semiconductor chip 3 bonding wire 4 sealing resin
Claims (3)
げ加工を施したリードフレームに対して、該リードフレ
ームのチップマウント部に半導体チップをマウントし、
かつ半導体チップと外部リード部との間にワイヤボンデ
ィングを施した後に、リードフレーム上で半導体チップ
の周域を樹脂封止し、さらにタイバーをカットして個別
素子に分割することを特徴とするリードフレームを用い
た樹脂封止型半導体素子の製造方法。1. A semiconductor device is mounted on a chip mounting portion of a lead frame, the outer lead portion of which is subjected to a predetermined lead bending process.
In addition, after performing wire bonding between the semiconductor chip and the external lead portion, the periphery of the semiconductor chip is resin-sealed on the lead frame, and the tie bar is further cut to divide into individual elements. A method for manufacturing a resin-sealed semiconductor element using a frame.
ード部のアウタ側先端がチップマウント部の下面とほぼ
同じレベルに並ぶようにリード曲げ加工を施したことを
特徴とするリードフレームを用いた樹脂封止型半導体素
子の製造方法。2. The lead frame according to claim 1, wherein a lead bending process is performed so that the outer ends of the outer lead parts are arranged at substantially the same level as the lower surface of the chip mount part. And a method for manufacturing a resin-sealed semiconductor element.
マウント部，および該チップマウント部から同一方向に
引出した外部リード部を、２列向かい合わせに配列して
パターン形成したリードフレームを用いることを特徴と
するリードフレームを用いた樹脂封止型半導体素子の製
造方法。3. The manufacturing method according to claim 1, wherein a chip mount section and an external lead section drawn out in the same direction from the chip mount section are arranged in a pattern facing each other in two rows, and a patterned lead frame is used. A method for manufacturing a resin-encapsulated semiconductor element using a lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5139694A JPH06349990A (en) | 1993-06-11 | 1993-06-11 | Manufacture of resin-sealed semiconductor element using lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5139694A JPH06349990A (en) | 1993-06-11 | 1993-06-11 | Manufacture of resin-sealed semiconductor element using lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06349990A true JPH06349990A (en) | 1994-12-22 |
Family
ID=15251246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5139694A Pending JPH06349990A (en) | 1993-06-11 | 1993-06-11 | Manufacture of resin-sealed semiconductor element using lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06349990A (en) |
-
1993
- 1993-06-11 JP JP5139694A patent/JPH06349990A/en active Pending
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