JPH06349841A - Bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance and parasitic resistance caused by a structure of a connection part between a base lead out electrode and a base epitaxial layer and to further improve operation speed by making the base lead-out electrode connected with the base epitaxial layer at a sidewall thereof. CONSTITUTION:This device has an insulation film 4 having an opening part in an upper surface of a collector layer which consists of a first conductivity type buried layer 2 formed in one main surface of a semiconductor substrate 1 and a first conductivity type epitaxial layer 3 and is electrically separated mutually by the insulation film 4. It also has a base lead out electrode comprosed of a conductive film including a second conductivity type polycrystalline semiconductor film 10 on the insulation film 4 and a base comporsed of a second conductivity type epitaxial layer 7 on a region of the opening part. In such a bipolar transistor, the base lead-out electrode 10 is connected with thesecond conductivity type base epitaxial layer 7 at a sidewall thereof. For example, a sidewall of the base epitaxial layer 7 is tilted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor suitable for high speed operation and its manufacturing method.

[0002]

2. Description of the Related Art Prior art relating to the present invention, namely,
For a self-aligned bipolar transistor using an epitaxial layer as a base, see 1990 IMD Technical Digest, (1990).
Year) 607 to 610, (1990 IEDM
Technical Digest, pp. 607-610).

A bipolar transistor according to this conventional technique will be described with reference to FIG. That is, an insulating film 6 having an opening on the upper surface of a collector layer formed of an n-type buried layer 2 and an n-type epitaxial layer 3 formed on a p-type Si substrate 1 and electrically isolated from each other by an insulating film 4. And a base lead electrode 1 made of a p-type polycrystalline Si film on the insulating film 6
0, a base layer made of the p-type epitaxial layer 7 is provided on the opening region, and the polycrystalline Si base extraction electrode 10 and the base epitaxial layer 7 overlap each other in the opening region with a certain width. Connections are made on the horizontal surface via the p-type polycrystalline Si film 9. Furthermore, the base extraction electrode 1
0 and the emitter made of the n-type polycrystalline Si film 14 are separated by the insulating film 11 formed on the side wall of the base extraction electrode.

[0004]

In the above prior art, the polycrystalline Si base extraction electrode 10 and the base epitaxial layer 7 overlap in the opening region and are connected in the horizontal plane. As a result, the overlapped portion in the opening region on the upper surface of the collector layer becomes the external base region and does not contribute to the essential operation of the bipolar transistor. Therefore, there is a problem that the existence of the region causes the parasitic capacitance and reduces the operation speed of the transistor.

On the other hand, as shown in FIG. 8, when the area of this overlapping region is reduced to reduce the parasitic capacitance, the connecting portion 9 between the base extraction electrode and the base epitaxial layer becomes narrow and elongated. There is also a problem that the external base resistance increases and the operating speed of the transistor is not sufficiently improved.

An object of the present invention is to reduce the parasitic capacitance and the parasitic resistance due to the structure of the connecting portion between the base extraction electrode and the base epitaxial layer in the self-aligned bipolar transistor using the epitaxial layer as the base, and to improve the operating speed. It is to further improve.

[0007]

According to the present invention, in order to reduce the parasitic capacitance, the base extraction electrode is connected to the side wall of the base epitaxial layer so that there is almost no overlap between the two layers in the opening region. The contact width of the base extraction electrode and the semiconductor substrate around the opening is constant regardless of the location and is extremely small, 100 nm or less.

In order to prevent the connection portion between the base extraction electrode and the base epitaxial layer from being narrowed and elongated and the external base resistance from increasing, the side wall of the base epitaxial layer is inclined not obliquely but vertically.
Further, whether the insulating film on the upper surface of the collector layer is gradually thinned at the edge around the opening, or the upper surface of the insulating film is at the same height as the upper surface of the collector layer in the opening. Alternatively, the insulating film is made up of at least two types of insulating films, and the film having the larger film thickness of the upper layer of the insulating films recedes outward from the periphery of the opening by a certain dimension. Further, the inner side wall of the base extraction electrode is located inside the periphery of the opening.

Further, in order to further reduce the external base resistance, the base lead electrode is formed of a two-layer film of a metal film and a polycrystalline Si film or a metal silicide film and a polycrystalline Si film. Further, in that case, the distance between the metal film or the metal silicide film and the side wall of the base epitaxial layer is constant around the base epitaxial layer and is very small.

The following means are used to form a bipolar transistor having this structure. That is, on the collector region formed on the semiconductor substrate, first, an island region formed of a multilayer film including a Si oxide film and a Si nitride film is formed,
Next, a thin film containing a Si nitride film is formed on the side wall of this island region. The contact width around the opening between the base extraction electrode and the semiconductor substrate is determined by the thickness of the sidewall film.
After that, a Si oxide film is selectively formed on a portion of the collector region which is not covered by the island region and its sidewall film by a thermal oxidation method. After removing the side wall film, a polycrystalline Si film is deposited, and the polycrystalline S film on the island region is further deposited.
The i film is selectively removed, and then an oxidized Si film is selectively formed on the surface of the remaining polycrystalline Si film by a thermal oxidation method. This polycrystalline Si film serves as a base extraction electrode. Then, after removing the multilayer film forming the island region, an epitaxial layer is selectively formed on the semiconductor substrate having the exposed single crystal surface, and a polycrystalline semiconductor film is selectively formed on the exposed sidewall of the polycrystalline Si film at the same time. By this step, the connecting portion between the base extraction electrode and the base epitaxial layer having the above structure is formed. After this step, the bipolar transistor is completed through the steps of forming an insulating film on the side wall of the polycrystalline semiconductor film and forming an emitter made of the polycrystalline semiconductor film by the same method as the conventional technique.

The following means can be used as a method for forming a bipolar transistor having a similar structure.
First, on the collector region formed on the semiconductor substrate,
After sequentially forming the first insulating film, the second insulating film having a larger film thickness, the polycrystalline semiconductor film, and the third insulating film, an opening reaching the upper surface of the first insulating film is formed in the collector region. Next, the sandwiched second insulating film is side-etched from the side wall by a certain size. Next, after depositing a thin polycrystalline Si film on the entire surface of the substrate, a portion of the polycrystalline Si film in contact with the third insulating film and the first insulating film is selectively removed. Next, after removing the first insulating film, an epitaxial layer is selectively formed on the semiconductor substrate having the exposed single crystal surface, and a polycrystalline semiconductor film is selectively formed on the exposed portion of the polycrystalline semiconductor film at the same time. By this step, the connecting portion between the base extraction electrode and the base epitaxial layer having such a structure is formed.

In the method of forming a bipolar transistor, instead of the step of selectively forming an epitaxial layer on a semiconductor substrate having an exposed single crystal surface and a polycrystalline semiconductor film on an exposed portion of the polycrystalline semiconductor film at the same time, Epitaxial layer on the semiconductor substrate with single crystal surface exposed,
A polycrystalline semiconductor film is simultaneously formed on all the rest of the substrate,
Thereafter, a bipolar transistor having a similar structure can be formed by using a step of selectively removing the polycrystalline semiconductor film on the insulating film on the base lead electrode.

The following means can also be used as a method for forming a bipolar transistor having a similar structure.
First, an epitaxial layer is formed on the collector region formed on the semiconductor substrate, and a polycrystalline semiconductor film having the same composition is formed on the insulating film at the same time. Next, an island-shaped region made of a multilayer film including at least a Si oxide film and a Si nitride film is formed on the collector region, and a Si oxide film is further formed on the side wall thereof.
Next, with the island-shaped multilayer film as a mask, the exposed epitaxial layer and the polycrystalline semiconductor film on the insulating film are removed.
In this case, CCl4 is used as the etching gas so that the sidewalls of the remaining epitaxial layer are inclined. Next, an insulating film and a p-type polycrystalline Si film are sequentially deposited, the p-type polycrystalline Si film on the upper surface and the sidewall of the island region is removed by photolithography and dry etching, and the exposed sidewall of the epitaxial layer is inclined. The insulating film of is also removed by dry etching. The width of the opening formed on the side wall of the epitaxial layer is determined by the thickness of the p-type polycrystalline Si film. Next, a p-type polycrystalline Si film is further grown on the exposed portion of the epitaxial layer and the polycrystalline Si film to form a connecting portion between the epitaxial layer and the base lead electrode.
Next, after exposing the polycrystalline Si film on the island-shaped region, a metal film or a metal silicide film is selectively formed on the island-shaped region and on the base extraction electrode, that is, on the exposed portion of the polycrystalline Si film. . By this step, the metal film or metal silicide film and the epitaxial layer are arranged in a very short distance in a self-aligned manner. Next, an insulating film is deposited, and then the insulating film on the island region is removed by a normal planarization process. Next, the multilayer film in the island region is entirely removed by etching to expose the underlying epitaxial layer. After this step,
By the same method as the conventional technique, a bipolar transistor is completed through steps such as forming an insulating film on the side wall of the opening and then forming an emitter made of a polycrystalline semiconductor film.
When an n-type polycrystalline Si film is used as the lowermost layer of the multilayer film in the island region, the n-type polycrystalline Si film can be used as it is as an emitter by undergoing almost the same steps as the above-mentioned forming method. It will be possible.

[0014]

In the bipolar transistor according to the above-mentioned forming method, since the base extraction electrode is connected to the side wall of the base epitaxial layer, the overlap between the two layers in the collector upper opening region is very small. Furthermore, the contact width around the opening between the base extraction electrode and the semiconductor substrate can be arbitrarily determined by the thickness of the sidewall film of the island-shaped region described in the method for forming a transistor, and thus is constant regardless of the location. , And 10
It is easily smaller than 0 nm, which is smaller than the area of the intrinsic region of the transistor, and can be made zero. As a result, the area of the opening area that does not contribute to the essential operation of the transistor, that is, the area ratio of the external base, can be made significantly smaller than in the case of the conventional technique, and the parasitic capacitance of the transistor can be reduced. Can be significantly reduced.

Further, in the bipolar transistor of this structure, the side wall of the base epitaxial layer is inclined not obliquely but vertically so that the contact area with the base extraction electrode can be made large. Also, the insulating film on the upper surface of the collector layer is gradually thinned at the edge around the opening, or the upper surface of the insulating film is at the same height as the upper surface of the collector layer in the opening, or
The insulating film consists of multiple types of insulating film, and the thicker film above it recedes outward from the periphery of the opening by a certain dimension. There is no large step in the connecting part. Further, the side wall of the base extraction electrode is located inside the periphery of the opening, and the base extraction electrode and the base epitaxial layer are close to each other. With the above characteristics, in the bipolar transistor having the above structure, even when the area of the external base is reduced, the base extraction electrode and the base epitaxial layer can be connected to each other without a narrow and narrow connecting portion. As a result, the external base resistance does not increase as a result of reducing the area of the external base region as in the case of the conventional technique.

Further, in the bipolar transistor of this structure, it is possible to use a metal film or metal silicide film laminated with a polycrystalline Si film for the base extraction electrode, and the metal film or metal silicide film and the base epitaxial layer. Since the distance between and can be made very small in a self-aligned manner, it is possible to further reduce the external base resistance without deteriorating this effect.

[0017]

EXAMPLES In the following examples, npn-type bipolar transistors will be described, but pnp-type bipolar transistors having the same structure except that n-type and p-type impurities are exchanged can be realized by the same forming method. Further, it is possible to form both the npn type and the pnp type on the same substrate at the same time if the steps of introducing the impurities are made different.

A first embodiment of the present invention will be described with reference to FIGS. First, FIG. 1 shows a vertical sectional view of a bipolar transistor of the present invention. 1 is a p-type single crystal Si substrate, 2 is a high-concentration n-type buried layer, 3 is a low-concentration n-type Si epitaxial layer,
4 is a SiO ₂ film, 5 is a p-type impurity diffusion layer, and 6 is SiO ₂
Film, 7 p-type SiGe epitaxial layer, 8 n-type impurity diffusion layer, 9 p-type polycrystalline SiGe film, 10 p-type polycrystalline Si film, 11 SiO ₂ film, 12 Si ₃ N ₄ film, Thirteen
Is an SiO ₂ film, 14 is an n-type polycrystalline Si film, and 15 is SiO 2.
_{The two} films, 16, 17, and 18 are metal films. The high-concentration n-type buried layer 2 and the low-concentration n-type Si epitaxial layer 3 constitute a collector, and the metal film 18 serves as a collector electrode. The intrinsic base is composed of the p-type SiGe epitaxial layer 7, and the p-type impurity diffusion layer 5 corresponds to the graft base. The p-type polycrystalline SiGe film 9 and the p-type polycrystalline Si film 10 serve as base extraction electrodes, and the metal film 17 serves as a base electrode. The n-type impurity diffusion layer 8 and the n-type polycrystalline Si film 14 constitute an emitter, and the metal film 16 serves as an emitter electrode. The base extraction electrode and the emitter are composed of SiO ₂ film 11, Si ₃ N ₄
It is electrically separated by the membrane 12.

FIG. 2 is an enlarged view of the main part of FIG. The dimension of the portion A in the figure is 0 or more, that is, the side wall inside the base extraction electrode is inside the peripheral edge of the collector region upper opening. Further, the base extraction electrode and the single crystal Si substrate are in contact with each other around the opening, but the width of that portion, that is, the dimension B in the figure is constant around the opening, and is as small as about 50 nm. Has become.
Further, the SiO ₂ film 6 on the collector region is gradually thinned around the opening, and no steep step is generated in that portion.

A method of manufacturing the bipolar transistor of this embodiment will be described with reference to cross-sectional views (a) to (f) of each step. However, the electrode lead-out portions of the base and the collector are exactly the same as in the conventional case, and are therefore omitted.

First, the n-type buried layer 2 and the n-type epitaxial layer 3 are formed on the Si substrate 1 by a known ordinary method, and then the SiO ₂ film 4 for element isolation is formed. next,
The SiO ₂ film 20, the Si ₃ N ₄ film 21, the polycrystalline Si film 22 and the Si ₃ N ₄ film 23 are sequentially deposited by a normal vapor phase growth method. Furthermore, the Si ₃ N ₄ film 23, the polycrystalline Si film 22, and the Si ₃ N ₄ film 21 are formed by photolithography and anisotropic etching.
Is selectively removed to form an island region made of the multilayer film on the element-isolated collector region (a).

Next, Si ₃ N is formed by a normal vapor phase growth method.
After depositing the _four films 24 and 25 and the polycrystalline Si film, those films in regions other than the side wall portions of the multilayer island region are removed by anisotropic etching. Further, after removing the polycrystalline Si film on the side wall by ordinary wet etching, a SiO ₂ film 6 is formed on the collector region by a thermal oxidation method. In this case, the position of the edge of the SiO ₂ film 6 is Si _{3 on the} side wall.
Si ₃ so that it is almost directly under the surface of the N ₄ film 24.
The thicknesses of the N ₄ films 24 and 25 and the polycrystalline Si film are determined (b).

Next, the Si ₃ N ₄ film 25 is anisotropically etched, and the SiO ₂ film 20 exposed thereby is further etched.
Are removed by wet etching, and then a polycrystalline Si film 10 is deposited by a vapor phase growth method. Next, the polycrystalline Si film on the island region is selectively removed by photolithography and etching, and the remaining polycrystalline Si film is patterned as a base extraction electrode. The SiO ₂ film 13 is formed on the Si film. Further, boron ions are implanted into the polycrystalline Si film by the ion implantation method, and boron is diffused in the polycrystalline Si film and the low-concentration n-type Si epitaxial layer 3 by the subsequent heat treatment, so that the p-type polycrystalline Si film 10 and the p-type The diffusion layer 5 is formed (c).

Next, by wet etching, Si ₃
N ₄ film 23, polycrystalline Si film 22, Si ₃ N ₄ films 21 and 2
4, the SiO ₂ film 20 is removed (d).

Next, by a vapor phase growth method or a molecular beam epitaxy method at a low substrate temperature of 800 ° C. or lower, p-type S having a Si: Ge ratio of 4: 1 is formed on the single crystal Si substrate.
A p-type polycrystalline SiGe film 9 having the same composition is selectively formed on the sidewalls of the iGe mixed crystal epitaxial layer 7 and the polycrystalline Si film (e).

Next, after depositing a SiO ₂ film 11 and the Si ₃ N ₄ film 12 by a conventional vapor deposition method, to remove the Si ₃ N ₄ film 12 other than the side wall portion by anisotropic etching, and further wet The SiO ₂ film 11 on the epitaxial layer 7 exposed by etching is removed. Further, after depositing the polycrystalline Si film 14 by a normal vapor phase growth method, P ions are implanted and heated by an ion implantation method to diffuse P into the polycrystalline Si film 14 and the epitaxial layer 7, and n The type diffusion layer 8 is formed. Further, the polycrystalline Si film 14 is patterned by photolithography and etching (f). Further, after this step, the electrodes of the emitter, the base and the collector are all formed by the usual method to complete the bipolar transistor of FIG.

In forming the epitaxial base layer, as shown in FIG.
As shown in (e), p-type SiG is formed on the single crystal Si substrate.
A p-type polycrystalline SiGe film 9 is selectively formed on the sidewalls of the e-epitaxial layer 7 and the polycrystalline Si film so that no film is deposited on the oxide film. However, instead of this process, the p-type SiGe epitaxial layer is formed on the single crystal Si substrate, and the p-type polycrystalline S is formed on the entire surface of the other substrate.
It is also possible to use a method of forming an iGe film and then selectively removing the p-type polycrystalline SiGe film other than the sidewall portion of the polycrystalline Si film. The distinction between the selective deposition method and the blanket deposition method in the vapor phase growth method is a known technique, and depends on whether or not HCl is contained in the reaction gas. That is, when HCl is included, selective deposition is performed, and when HCl is not included, overall deposition is performed.

A method of selectively removing the polycrystalline SiGe film other than the side wall portion in the case where the entire surface is deposited will be described with reference to FIGS. 11 (a) to 11 (d). First, p on the entire surface of the substrate
The stage where the formation of the type SiGe epitaxial layer 7 and the p-type polycrystalline SiGe film 9 is completed is (a). Next, a photoresist 33 is applied to the entire surface of the substrate (b). Next, the photoresist is etched back by anisotropic etching so that it remains only on the opening on the collector (c). Next, the p-type polycrystalline SiGe film 9 on the SiO ₂ film 13 and on the side wall is removed by isotropic etching so that it is left only on the side wall of the polycrystalline Si film (d). This method also shows
It is possible to form the bipolar transistor of the first embodiment of the present invention shown in FIG.

According to the present embodiment, the area of the external base region can be reduced to about 1/4 without increasing the base resistance, as compared with the case of the prior art, so that the capacitance between the base and collector can be reduced. It can be halved.

Next, the bipolar transistor of the second embodiment of the present invention will be explained with reference to FIG. However, in this figure, the base electrode and collector electrode portions of the transistor are the same as in FIG. The names of the respective parts in FIG. 3 are the same as those in the first embodiment of the present invention shown in FIG. The difference between the first embodiment and this embodiment is the shape of the insulating film 6 on the collector region. In this embodiment, the insulating film 6 is not gradually thinned around the opening as in the first embodiment, but its upper surface is the upper surface of the low-concentration n-type Si epitaxial layer 3 in the opening. At the same height. That is, the insulating film 6
And the upper surface of the junction portion of the epitaxial layer 3 is flat.

The manufacturing method of the bipolar transistor of this embodiment is the same as that of the first embodiment described with reference to FIG. 9 except a part, but the different part will be described with reference to FIG. . The process up to the step shown in FIG. 9A is the same as in the first embodiment. After that, Si ₃ N ₄ films 24 and 25
The formation of is also the same as in the first embodiment. But,
In the case of the second embodiment, instead of forming the SiO ₂ film 6 immediately after that, the SiO ₂ film 20 exposed on the substrate surface is removed by anisotropic etching as shown in FIG. The epitaxial layer 3 is dug to a certain depth. Further, the SiO ₂ film 27 and the Si ₃ N ₄ film 28 are formed on the side wall of the formed step by the usual vapor growth method and anisotropic etching. Then, as shown in FIG. 12B, a SiO ₂ film 6 is formed by thermal oxidation. Also in this embodiment, since there is no step at the connecting portion between the base extraction electrode and the epitaxial base layer and the portion can be prevented from being narrow and elongated, the same effect as that of the first embodiment can be obtained.

Next, the bipolar transistor of the third embodiment of the present invention will be explained with reference to FIG. However, in this figure, the base electrode and collector electrode portions of the transistor are the same as in FIG. The names of the respective parts in FIG. 4 are almost the same as those in the first embodiment of the present invention shown in FIG. However, 19 is a Si ₃ N ₄ film. The difference between the first embodiment and this embodiment is that the insulating film on the collector region is made of Si in the first embodiment.
In contrast to the O ₂ film 6, the SiO ₂ film 6 is used in this embodiment.
And the Si ₃ N ₄ film 19 is a two-layer film. The thickness of these films is 30 nm for the SiO ₂ film 6 and 19 nm for the Si ₃ N ₄ film.
Is 100 nm, and the Si ₃ N ₄ film is thicker. Si
The edge of the ₃ N ₄ film 19 is near the opening, that is, the SiO ₂ film 6
Is located 100 nm outside from the edge of. Other structures in this embodiment are the same as those in the first embodiment.

A method of manufacturing the bipolar transistor of this embodiment will be described with reference to FIGS. First, the n-type buried layer 2 and n
After the type epitaxial layer 3 is formed, a SiO ₂ film 4 for element isolation is formed. Next, the SiO ₂ film 6, the Si ₃ N ₄ film 19 and the polycrystalline Si film 1 are formed by a normal vapor phase growth method.
0, the SiO ₂ film 13 is sequentially deposited. Then, by implanting boron ions into the polycrystalline Si film 10 by an ion implantation method and heating the polycrystalline Si film 10, the polycrystalline Si film 10 is doped with a high concentration of p.
A mold (a).

Next, by photolithography and anisotropic dry etching, the SiO ₂ film 13, polycrystalline Si film 10, S
The i ₃ N ₄ film 19 is selectively removed, and an opening reaching the upper surface of the SiO ₂ film 6 is formed in the element-isolated collector region. Further, the Si ₃ N ₄ film 19 is set back by 100 nm from the side wall of the opening by etching using a phosphoric acid solution (b).

Next, a film thickness of 25 nm is formed by an ordinary vapor phase growth method.
Then, an extremely thin polycrystalline Si film 26 is deposited. Then, by anisotropic dry etching, the polycrystalline Si film 2 on the upper surface of the SiO ₂ film 13 and its side surfaces at the opening, and the bottom surface of the opening is formed.
Remove 6. Further, boron is diffused from the polycrystalline Si film 10 to the polycrystalline Si film 26 by heating, and then the exposed SiO ₂ film 6 is removed by wet etching (c).

Next, by the same method as in the first embodiment, a p-type SiGe mixed crystal epitaxial layer 7 having a Si / Ge ratio of 4: 1 and a polycrystalline Si substrate are formed on a single crystal Si substrate.
A p-type polycrystalline SiGe film 9 having the same composition is formed on the side wall of the film (d).

Thereafter, the bipolar transistor of FIG. 4 is completed through the process of FIG. 8 (e) by the same method as in the first embodiment. According to this embodiment, as in the case of the first embodiment, the area of the external base region can be reduced to about 1/4 as compared with the case of the conventional technique without increasing the base resistance. , The capacitance between base and collector is 1/2
It is possible to

Next, the bipolar transistor of the fourth embodiment of the present invention will be explained with reference to FIG. The names of the respective parts in FIG. 5 are almost the same as those in the third embodiment of the present invention shown in FIG. However, 30 is a metal silicide film. In this embodiment, instead of the polycrystalline Si film 10 in the third embodiment, a laminated film of the polycrystalline Si film 10 and the metal silicide film 30 is used as a base lead electrode. Further, in this embodiment, the sidewall of the intrinsic base p-type SiGe epitaxial layer 7 is inclined. Other structures in this embodiment are basically the same as those in the third embodiment.

A method of manufacturing the bipolar transistor of this embodiment will be described with reference to FIGS. First, in FIG. 13, an n-type buried layer 2 and an n-type epitaxial layer 3 are formed on a Si substrate 1 by a known ordinary method, and then a SiO ₂ film 4 for element isolation is formed. Next, the substrate temperature 80
By the vapor phase growth method or the molecular beam epitaxy method at a low temperature of 0 ° C. or lower, p-type Si and G
a SiGe mixed crystal epitaxial layer 7 in which the ratio of e is 4: 1,
A p-type polycrystalline SiGe film 9 having the same composition is formed on the SiO ₂ film 4.
Are simultaneously formed (a).

Next, the SiO ₂ film 20, the Si ₃ N ₄ film 21, the polycrystalline Si film 22 and the Si ₃ N ₄ film 23 are sequentially deposited by the normal vapor phase growth method. Furthermore, by photolithography and anisotropic dry etching, Si ₃ N ₄ film 23, polycrystalline Si
The film 22 and the Si ₃ N ₄ film 21 are selectively removed to form an island-shaped region made of the multilayer film on the collector region where the element is separated. Furthermore, after depositing a SiO ₂ film 27 by a conventional vapor deposition method, removing the SiO ₂ film in the region other than the side wall portions of the island-like multilayer film by anisotropic dry etching. Further, using the island-shaped multilayer film as a mask, the exposed SiGe mixed crystal epitaxial layer 7, p-type polycrystalline SiG
The e film 9 is removed by anisotropic etching. In this case, Si left by using CCl4 as an etching gas
The side wall of the Ge mixed crystal epitaxial layer 7 is inclined (b).

Next, after removing the SiO ₂ film 27 by wet etching, the p-type polycrystalline Si film 1 to which the SiO ₂ film 6, the Si ₃ N ₄ film 19 and the B are added by the usual vapor phase growth method.
0 is sequentially deposited (c).

Next, a photoresist film 33 is applied on the entire surface, and then the photoresist on the island regions is selectively removed by photolithography and dry etching (d).

Next, the polycrystalline Si film 10 on the upper surface and the side wall of the island region is removed by anisotropic dry etching, and the exposed Si ₃ N ₄ film 19 on the inclined side wall of the base epitaxial layer 7 is also changed. It is removed by isotropic dry etching (e).

Next, after removing the photoresist film 33, the S on the side wall of the island region is etched by etching with a phosphoric acid solution.
At the same time as removing the i ₃ N ₄ film 19, the polycrystalline Si film 10 and the S
The Si ₃ N ₄ film 19 sandwiched between the iO ₂ films 6 is side-etched. Further, the SiO ₂ film 6 on the inclined side wall of the base epitaxial layer 7 is removed by anisotropic dry etching (f).

Next, in FIG. 14, a p-type polycrystalline Si film 29 is selectively grown on the exposed portions of the SiGe mixed crystal epitaxial layer 7 and the polycrystalline Si film 10. Then the p
After patterning the type polycrystalline Si film as a base extraction electrode, the Si ₃ N ₄ film 23 on the island region is removed by dry etching to expose the polycrystalline Si film 22 (a).

Next, a metal silicide film 30 is selectively formed on the exposed portion of the polycrystalline Si film by a usual method. After that, the SiO ₂ film 31 is deposited by a normal vapor phase growth method (b). Next, the SiO ₂ film 31 on the island region is removed by a normal polishing method until the metal silicide film 30 is exposed (c). Next, after the exposed metal silicide film 30 on the island region is removed by dry etching,
The polycrystalline Si film 22 is also removed by wet etching (d).

Next, after depositing the the Si ₃ N ₄ film 12 by a conventional vapor deposition method, to remove the Si ₃ N ₄ film other than the side wall portion by anisotropic dry etching was further exposed by wet etching epitaxial The SiO ₂ film 6 on the layer 7 is removed. Further, after depositing the polycrystalline Si film 14 by a normal vapor phase growth method, phosphorus ions are implanted by an ion implantation method and heated to diffuse P into the polycrystalline Si film 14 and the epitaxial layer 7, thereby forming an n-type The diffusion layer 8 is formed. At the same time, the p-type polycrystalline Si film 10 causes B
Are diffused to form a p-type diffusion layer 5. Further, the polycrystalline Si film 14 is patterned by photolithography and etching (e). After this step, the emitter, base and collector electrodes are all formed by the usual method to complete the bipolar transistor shown in FIG.

According to the present embodiment, in addition to the effect similar to that of the first embodiment, the metal silicide film 30 slightly overlaps the sidewall of the intrinsic base epitaxial layer with the p-type polycrystalline Si film 10 interposed therebetween, which is extremely effective. The external base resistance is about 2 / compared to the first embodiment due to the small and constant distance.
It is possible to reduce it to 3.

Next, a bipolar transistor of the fifth embodiment of the present invention will be described with reference to FIG. The names of the respective parts in FIG. 6 are the same as those in the fourth embodiment of the present invention shown in FIG. The structural difference between this embodiment and the fourth embodiment is only the shape of the n-type polycrystalline Si film 14, but the manufacturing method is quite different.

A method of manufacturing the bipolar transistor of this embodiment will be described with reference to FIGS. First, the n-type buried layer 2 and n
After the type epitaxial layer 3 is formed, a SiO ₂ film 4 for element isolation is formed. Next, a p-type SiGe mixed crystal epitaxial layer 7 having a Si / Ge ratio of 4: 1 is formed on the single crystal Si substrate by a vapor phase growth method at a substrate temperature of 800 ° C. or lower or a molecular beam epitaxy method. , SiO ₂
A p-type polycrystalline SiGe film 9 having the same composition is simultaneously formed on the film 4. Up to this step is the same as in the case of the fourth embodiment described in FIG. 11 (a).

Next, the n-type polycrystalline Si film 14 containing P, the SiO ₂ film 32, and the polycrystalline Si are added by a normal vapor phase growth method.
The film 22 and the Si ₃ N ₄ film 23 are sequentially deposited. Further, these multilayer films are selectively removed by photolithography and anisotropic dry etching to form island regions made of the multilayer film on the element-isolated collector region. Further, after depositing the SiO ₂ film 27 by a normal vapor phase growth method,
By anisotropic dry etching, the SiO ₂ film in the region other than the sidewall portion of the island-shaped multilayer film is removed. Further, using the island-shaped multilayer film as a mask, the exposed SiGe mixed crystal epitaxial layer 7 and the p-type polycrystalline SiGe film 9 are removed by anisotropic etching. In this case, CCl4 is used as an etching gas so that the sidewall of the SiGe mixed crystal epitaxial layer 7 left is inclined (b).

Next, the p-type polycrystalline Si film 1 to which the SiO ₂ film 6, Si ₃ N ₄ film 19 and B are added by the usual vapor phase growth method.
0 is sequentially deposited (c). Next, FIG. 1 in the case of the fourth embodiment
3 (d) (e) (f) and FIGS. 14 (a) (b) (c).
The p-type polycrystalline Si film 1 is formed by a method similar to that shown in FIG.
0, a metal silicide film 30, and a SiO ₂ film 31 are formed (d).

Next, by heating, n-type polycrystalline Si
P in the film is diffused into the epitaxial layer 7 to form the n-type diffusion layer 8, and at the same time, the p-type polycrystalline Si film 10 is used to form B.
Are diffused to form a p-type diffusion layer 5. Further, the exposed metal silicide film 30 on the island region is removed by dry etching, and then wet etching is performed to remove polycrystalline Si.
The film 22 and the SiO ₂ film 32 are also removed (e). Further, after this step, the electrodes of the emitter, the base and the collector are all formed by the usual method to complete the bipolar transistor of FIG. According to this embodiment, the same effect as the fourth embodiment can be obtained.

Next, the bipolar transistor of the sixth embodiment of the present invention will be explained with reference to FIG. 34 is a semi-insulated type G
aAs substrate, 35 is n + type GaAs layer, 36 is n− type G
aAs layer, 37 SiO ₂ film, 38 Be-diffused p-type GaA
s layer, 39 is p-type GaAs epitaxial layer, 40 is n
Type AlGaAs epitaxial layer, 41 is n + type GaA
s epitaxial layer, 42 is a p + type polycrystalline GaAs film,
Reference numeral 43 is a metal film, and other portions are the same as in the case of the fifth embodiment of FIG. In this embodiment, the constituent materials are different from those of the previous embodiments, but the function of each part is basically the same. In the manufacturing method of this embodiment, the constituent material is Si.
There is only a change related to the replacement of the compound semiconductor with the compound semiconductor, and the operation is basically the same as that of the fifth embodiment described with reference to FIG. According to this embodiment, a heterojunction bipolar transistor having a similar structure and a similar effect can be realized not only for Si-based compounds but also for compounds.

[0055]

In the bipolar transistor according to the present invention, the area of the external base region can be reduced to about 1/4 without increasing the base resistance, as compared with the case of the prior art. 1 / capacity
It can be 2. As a result, it is possible to increase the operating speed of the transistor by about 1.5 times that in the conventional technique.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is an enlarged view of a main part.

FIG. 3 is a vertical sectional view of a bipolar transistor according to a second embodiment of the present invention.

FIG. 4 is a vertical sectional view of a bipolar transistor according to a third embodiment of the present invention.

FIG. 5 is a vertical sectional view of a bipolar transistor according to a fourth embodiment of the present invention.

FIG. 6 is a vertical sectional view of a bipolar transistor according to a fifth embodiment of the present invention.

FIG. 7 is a vertical sectional view of a conventional bipolar transistor.

FIG. 8 is a vertical cross-sectional view for explaining problems in the conventional bipolar transistor.

FIG. 9 is a vertical sectional view of each step showing the method for manufacturing the bipolar transistor of the first embodiment of the present invention.

FIG. 10 is a vertical sectional view of each step showing the method of manufacturing the bipolar transistor of the third embodiment of the present invention.

FIG. 11 is a vertical cross-sectional view of each step showing another method for manufacturing the bipolar transistor of the first embodiment of the present invention.

FIG. 12 is a vertical sectional view of each step showing the method for manufacturing the bipolar transistor of the second embodiment of the present invention.

FIG. 13 is a vertical cross-sectional view of the first half process showing the method for manufacturing the bipolar transistor of the fourth embodiment of the present invention.

FIG. 14 is a vertical sectional view of a second half process showing the method of manufacturing the bipolar transistor of the fourth embodiment of the present invention.

FIG. 15 is a vertical sectional view of each step showing the method of manufacturing the bipolar transistor of the fifth embodiment of the present invention.

FIG. 16 is a vertical sectional view of a bipolar transistor according to a sixth embodiment of the present invention.

[Explanation of symbols]

1 ... p-type single crystal Si substrate, 2 ... high-concentration n-type buried layer, 3 ...
Low-concentration n-type Si epitaxial layer, 4, 6, 11, 1
5, 31 ... SiO ₂ film, 5 ... P-type impurity diffusion layer, 7 ... P
-Type SiGe epitaxial layer, 8 ... N-type impurity diffusion layer,
10 ... p-type polycrystalline Si film, 12, 19 ... Si ₃ N ₄ film, 1
4 ... N-type polycrystalline Si film, 16 ... Metal film, 30 ... Metal silicide film.

Front page continuation (72) Inventor Kazuhiro Onishi, 1-280, Higashi Koikekubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Yoichi Tamaki 1-280, Higashi Koikeku, Tokyo Kokubunji City, Central Research Laboratory, Hitachi Ltd. (72) Inventor Miya-saki Hiroshi 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory

Claims (16)

[Claims] 1. An opening is formed on the upper surface of a collector layer which is composed of a first-conductivity-type buried layer and a first-conductivity-type epitaxial layer formed on one main surface of a semiconductor substrate and which are electrically separated from each other by an insulating film. A bipolar transistor having an insulating film having, a base extraction electrode made of a conductive film containing a second conductivity type polycrystalline semiconductor film on the insulating film, and a base made of a second conductivity type epitaxial layer on the region of the opening. In the bipolar transistor, the base extraction electrode is connected to the second conductivity type base epitaxial layer at a sidewall thereof. 2. The bipolar transistor according to claim 1, wherein the sidewall of the second-conductivity-type base epitaxial layer is inclined. 3. The base lead electrode is in contact with the semiconductor substrate around the opening, and the width of the contact is constant around the opening.
Bipolar transistor with a thickness of 00 nm or less. 4. The bipolar transistor according to claim 1, wherein a side wall inside the base extraction electrode is located inside a periphery of the opening. 5. The bipolar transistor according to claim 1, 2, 3, or 4, wherein the insulating film having an opening on the collector layer is gradually thinned at an edge around the opening. 6. The bipolar device according to claim 1, 2, 3 or 4, wherein an upper surface of the insulating film having an opening on the collector layer is level with an upper surface of the collector layer in the opening. Transistor. 7. The bipolar transistor according to claim 1, 2, 3 or 4, wherein the insulating film having the opening on the collector layer is made of a plurality of kinds of insulating films, and an upper film of the insulating films is the opening. A bipolar transistor that recedes outward from the periphery by a certain amount. 8. The base epitaxial layer of the second conductivity type according to claim 1, 2, 3, 4, 5, 6 or 7.
A bipolar transistor made of a mixed crystal of Ge and Ge. 9. A bipolar transistor according to claim 1, 2, 3, 4, 5 or 7, wherein the semiconductor substrate, the epitaxial base layer and the emitter layer are made of a III-V group compound semiconductor. 10. Claims 1, 2, 3, 4, 5, 6, 7, 8
Or 9, the base extraction electrode includes a metal silicide film or a metal film, and edges of the films in the periphery of the opening are provided with the second conductivity type base epitaxial film via the second conductivity type polycrystalline semiconductor film. A bipolar transistor at a distance from the sidewalls of a layer. 11. The metal silicide film or the metal film of the base lead electrode is overlapped with the second conductivity type base epitaxial layer via the second conductivity type polycrystalline semiconductor film. Bipolar transistor. 12. A Si oxide layer is formed on a collector region, which is composed of a first-conductivity-type buried layer and a first-conductivity-type epitaxial layer formed on one main surface of a semiconductor substrate and electrically isolated from each other by an insulating film. Forming an island region made of a multilayer film including a film and a Si nitride film, forming a thin film including the Si nitride film on a sidewall of the island region, and forming the island region in the collector region. A step of selectively forming a Si oxide film on a portion not covered by the sidewall film; a step of removing the sidewall film of the island-shaped region and a step of forming a second conductivity type polycrystalline semiconductor film; Selectively removing the polycrystalline semiconductor film on the island-shaped region, forming an insulating film on the surface of the remaining polycrystalline semiconductor film, and removing the multilayer film forming the island-shaped region, A second conductor is formed on the semiconductor substrate with the crystal surface exposed. Forming a type epitaxial layer on the exposed side wall of the polycrystalline semiconductor film at the same time selectively forming the second conductivity type polycrystalline semiconductor film, and forming an insulating film on the side wall of the polycrystalline semiconductor film. A method of manufacturing a bipolar transistor, comprising: 13. A collector region, which comprises a buried layer of the first conductivity type and an epitaxial layer of the first conductivity type formed on one main surface of a semiconductor substrate and is electrically isolated from each other by an insulating film, is provided with a first layer and a second layer. Forming a first insulating film, a second insulating film, a conductive film including a second conductivity type polycrystalline semiconductor film, and a third insulating film, and forming an opening reaching the upper surface of the collector layer in the collector region And a step of side-etching the sandwiched second insulating film from the side wall by a certain dimension, and a second conductivity type epitaxial layer on the semiconductor substrate where the single crystal surface is exposed, and the exposed portion of the polycrystalline semiconductor film. And a step of selectively forming the second conductivity type polycrystalline semiconductor film at the same time, and a step of forming an insulating film on a sidewall of the polycrystalline semiconductor film. 14. The polycrystalline semiconductor film according to claim 12, wherein after the opening is formed in the collector region, the second conductivity type epitaxial layer is formed on the semiconductor substrate where the single crystal surface is exposed, and the polycrystalline semiconductor film is formed. Instead of the step of selectively forming the second-conductivity-type polycrystalline semiconductor film on the exposed part of the substrate, the second-conductivity-type epitaxial layer is formed on the semiconductor substrate with the single-crystal surface exposed, and the rest of the substrate. And a step of selectively forming the second-conductivity-type polycrystalline semiconductor film on all the parts of the same, and a step of selectively removing the second-conductivity-type polycrystalline semiconductor film on the insulating film. 15. A collector region comprising a buried layer of a first conductivity type and an epitaxial layer of a first conductivity type formed on one main surface of a semiconductor substrate and electrically isolated from each other by an insulating film, A step of simultaneously forming a second-conductivity-type polycrystalline semiconductor film on the insulating film in the element isolation region, and a multi-layer including a Si-oxide film, a Si-nitride film, and a poly-Si film on the collector region. A step of forming an island region made of a film, a step of forming a thin film including at least a Si nitride film or a silicon oxide film on a sidewall of the island region, and the exposed second conductive film using the island region as a mask. The epitaxial type epitaxial layer and the second-conductivity-type polycrystalline semiconductor film by etching, a step of forming an insulating film on the entire surface, and the insulating film is selectively removed at a constant width around the island region. Process A step of depositing the polycrystalline Si film, and then selectively removing the polycrystalline Si film on the island-shaped region, and selectively exposing a metal silicide film or a metal film on the exposed polycrystalline Si film. A step of forming, an insulating film is formed, a step of selectively removing the insulating film on the island region, and a sidewall of the opening formed after removing the multilayer film forming the island region A method of manufacturing a bipolar transistor, comprising the step of forming an insulating film on the substrate. 16. A collector region comprising a first-conductivity-type buried layer and a first-conductivity-type epitaxial layer formed on one main surface of a semiconductor substrate and electrically isolated from each other by an insulating film. A step of simultaneously forming a second-conductivity-type polycrystalline semiconductor film on the insulating film in the isolation region of the conductive-type epitaxial layer; and an island-like structure composed of a multilayer film including the insulating film and the semiconductor layer and having the semiconductor layer as the lowermost layer. A step of forming a region, a step of forming a thin film including a Si nitride film or a silicon oxide film on a sidewall of the island-shaped region, the second conductivity type epitaxial layer exposed using the island-shaped region as a mask and the first A step of etching away the two-conductivity-type polycrystalline semiconductor film, a step of forming an insulating film on the entire surface, a step of selectively removing the insulating film with a constant width around the island region, and a polycrystalline semiconductor Deposited film After that, a step of selectively removing the polycrystalline semiconductor film on the island region, a step of selectively forming a metal silicide film or a metal film on the exposed polycrystalline semiconductor film, and an insulating film are formed. After that, a step of selectively removing the insulating film on the island-shaped region, and a step of removing all the portions other than the lowermost semiconductor layer of the island-shaped multilayer film are included. Production method.