JPH0634729A - Output interface circuit of squid flux meter - Google Patents

Abstract

PURPOSE:To process a measurement signal output from SQUID by synchronizing it with a clock of the same frequency as an alternating current bias electric current for SQUID. CONSTITUTION:A negative pulse of a measurement signal VO is converted to a positive pulse by a negative inversion circuit 3, and it is outputted as a negative inversion pulse VM. As the measurement signal is delayed rather than the negative inversion pulse by a half-cycle delay circuit 4 by half a cycle of an alternating current bias electric current IB for SQUID and it is outputted as a delay pulse VD, it becomes possible for a process circuit 2 to process the negative inversion pulse VM and the delay pulse VD by way of synchronizing with a clock of the same frequency as the alternating current bias electric current IB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output interface circuit of a SQUID magnetometer.

[0002]

2. Description of the Related Art The SQUID magnetometer has the highest sensitivity among all magnetometers, and is particularly used for measuring the magnetic field emitted from a living body. From the viewpoint of clinical application, a SQUID magnetometer with higher characteristics is desired.

FIG. 8 is a circuit diagram of a conventional SQUID magnetometer (JP-A-63-290979 and JP-A-64).
-21378), the SQUID magnetometer is SQUID.
It is composed of a D chip S and an external circuit.

The primary differential type pickup coil 10 for canceling the earth magnetism is magnetically coupled to the SQUID element 12. The SQUID element 12 is configured by interposing a Josephson junction J1 and a Josephson junction J2 in a superconducting loop. The SQUID element 12 includes, for example, an AC bias current source 14 having a frequency of 10 MHz from FIG.
An alternating bias current as shown in (A) is supplied.

On the other hand, the write gate 16 has a SQUID
A magnetic coupling wire 20 is provided near the element 18. One end of the magnetic coupling wire 20 is connected to the SQUID element 18,
The other end is connected to the output end of the AC bias current source 14. The SQUID element 18 is annularly connected together with the superconducting storage loop 22 and the feedback loop 24.
The feedback loop 24 is magnetically coupled to the SQUID element 12.

When the SQUID element 12 receives an input magnetic flux via the pickup coil 10, a write pulse as shown in FIG.
In the superconducting storage loop 22 via the QUID element 18, FIG.
The magnetic flux ψ as shown in (C) is accumulated. A magnetic flux proportional to the stored magnetic flux ψ is fed back to the SQUID element 12 via the feedback loop 24, canceling the input magnetic flux from the pickup coil 10 and maintaining the operating point so that the total magnetic flux in the SQUID element 12 becomes zero. .

In the write pulse shown in FIG. 9B, the positive pulse is SQU from the pickup coil 10.
This occurs when the total magnetic flux obtained by superposing the input magnetic flux supplied to the ID element 12 and the magnetic flux supplied from the feedback loop 24 to the SQUID element 12 is increased by the magnetic flux quantum, and a negative pulse is generated by this total magnetic flux. Occurs only when the magnetic flux is decreased (the magnetic flux in the opposite direction is increased).

[0008] The write pulse from the input terminal of the write gate 16 is taken as a measurement signal V _O, and the measurement signal V _O, a signal obtained by inverting the measuring signal V _O at the inverting element 26, synchronized with the clock CLK frequency 2fHz Then, the signals are alternately selected by the switch element 28 and a signal in which the positive pulse of the measurement signal V _O is left unchanged and the negative pulse is a positive pulse is generated. The signal from the switch element 28 is supplied to the up / down counter 30, and its count value CN is the measurement signal V.
_O is incremented by a positive pulse of, is decremented by a positive pulse corresponding to the negative pulses of the measurement signal V _O. The count value CN is proportional to the stored magnetic flux ψ and the input magnetic flux, and the count value CN represents the measured value of the magnetic flux.

Such a SQUID magnetometer has an advantage that a large number of magnetometers can be arranged in parallel in one chip to measure the magnetic field distribution. By this one-chip,
There are advantages that the number of cables connecting the room temperature circuit and the low temperature side SQUID chip is reduced, the heat inflow from the room temperature side to the low temperature side is reduced, and the crosstalk between channels is reduced.

[0010]

However, since the up / down counter 30 must be operated with the clock CLK whose frequency is twice that of the AC bias current source 14, the configuration of the up / down counter 30 becomes complicated. Similar problems occur even if the up / down counter 30 is another processing circuit.

In view of the above problems, an object of the present invention is to provide a measurement signal output from the SQUID to the SQUID.
Another object of the present invention is to provide an output interface circuit of a SQUID magnetometer that can perform processing in synchronization with a clock having the same frequency as an AC bias current for use.

[0012]

FIG. 1 shows the principle structure of an output interface circuit of an SQUID magnetometer according to the present invention.

According to the present invention, an alternating current I _B having a frequency of fHz is used.
In is connected between the signal line L measured signal V _O having a positive pulse and negative pulse in synchronization with the alternating current phi _f from the SQUID 1 is biased is taken out, a processing circuit 2 for processing the measurement signal V _O In the output interface circuit of the SQUID magnetometer, the negative inverting circuit 3 that converts the negative pulse of the measurement signal V _O into a positive pulse and outputs this as a negative inversion pulse V _M , and the measurement signal V _O from the negative inversion pulse V _M Also includes a half-cycle delay circuit 4 that delays the AC current I _{B by} a half cycle and outputs it as a delay pulse V _D.

For example, AC bias current I_BAnd measurement signal
Issue V_OAre shown in Fig. 2 (A) and (B) respectively.
Delay pulse V_DIs V in FIG. 2 (C)_D1Or V of (D)
_D2And the negative inversion pulse V_MIn Fig. 2 (E)
V_M1, V of (F)_M2Or V of (G)_M3Will be processed
Circuit 2 has an inversion pulse at the fHz timing shown by the dotted line.
V _MAnd delayed pulse V_DCan be processed.
That is, according to the present invention, the frequency of half the frequency of the conventional one is used.
The negative inversion pulse V_MAnd delayed pulse V_D
Can be processed and therefore the processing circuit 2
The configuration can be simplified.

In the first aspect of the present invention, the negative inverting circuit 3 has:
For example, as shown in FIG. 3 and FIG.
Loose current φ_2fIs supplied to the power input terminal to operate, and the measurement signal
Issue V _OOutput the positive pulse of
_OMagnetic coupling type that converts negative pulse of positive to positive pulse and outputs
The logic gate 34.

In this case, since the negative inverting circuit 3 can be composed of one logic gate, the structure becomes simple.

In the second aspect of the present invention, the negative inverting circuit 3 is
For example, as shown in FIGS. 3 and 5, an alternating current φ _f having a frequency fHz is supplied to the power supply input terminal to operate, and the measurement signal V _o
Positive pulse is converted into a negative pulse output, the measurement signal V _O of
Is a magnetic field coupling type logic gate 34 for converting the negative pulse of the above into a positive pulse and outputting it.

Also in this case, since the negative inverting circuit 3 can be formed by one logic gate, the structure is simplified.

In the third aspect of the present invention, the half-cycle delay circuit 4
Is a delay line 32 as shown in FIG.

In this case, the structure is particularly simple.

In the fourth aspect of the present invention, the half-cycle delay circuit 4
6 and 7, for example, a plurality of current injection type Josephson gates 38 to 42 are connected in cascade, and each current injection type Josephson gate has a positive pulse current of frequency f with a phase difference from each other. By operating in φ1 to φ3, the positive pulse of the measurement signal V _O is delayed.

With this configuration, the delay time can be easily and accurately determined.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 3 shows the SQ of the first embodiment.
3 shows a UID magnetometer. The SQUID chip S and the AC bias current source 14 have, for example, the same configuration as in FIG. SQ
The input end of the write gate of the UID chip S is SQUI
It is connected to one end of the delay line 32 outside the D chip S and the input end of the magnetic field coupling type logic gate 34.

The delay line 32, a measurement signal V _O from the write gate 16 of the SQUID chip S, is intended to delay by the half-period of the AC bias current I _B of the frequency fHz, for example AC bias current I _B is 10MHZ In this case, it is delayed by 0.05 μs. AC bias current I _B
And when the measurement signal V _O is as shown in FIGS. 4A and 4B, the delay pulse V _D1 from the delay line 32 is as shown in FIG. 4C.

The magnetic field coupling type logic gate 34 has a known structure and is provided with an SQUID element 341, a magnetic field coupling line 342 and resistance elements R1 to R3, and the SQUID element 341 has Josephson junctions J6 to J8 in its loop. Has been done. The magnetic field coupling type logic gate 34 operates by being supplied with a positive pulse current φ _2f having a frequency of 2 fHz from the current source 36 to the power supply input terminal, and outputs a negative inversion pulse V _M1 with respect to the input measurement signal V _O. That is, as shown in FIG. 4, the magnetic field coupling type logic gate 34 synchronizes with the positive pulse current φ _2f and outputs the measurement signal V.
One positive pulse is output for each positive or negative pulse of _O.

In FIG. 3, the delay pulse V _D1 from the delay line 32 and the negative inversion pulse V _M1 from the magnetic field coupling type logic gate 34 are the up clock input terminal CKU and the down clock input terminal CK of the up / down counter 30A, respectively.
Supplied to D. The up / down counter 30A is shown in FIG.
The count value CN is incremented when the up clock input terminal CKU is "1" and decremented when the down clock input terminal CKD is "1" in synchronization with the clock CLK having the frequency fHz as shown in (F). When both the clock input terminal CKU and the down clock input terminal CKD are "1", they are ignored. As a result, the count value CN changes as shown in FIG.

In the first embodiment, since the delay line 32 and the magnetic field coupling type logic gate 34 are provided, the up / down counter 30A has the clock CLK having the same frequency as the AC bias current I _B , that is, half the conventional frequency. The configuration of the up / down counter 30A can be simplified.

[Second Embodiment] The SQUID magnetometer of the second embodiment is the same as that of FIG. 3 _except that the positive pulse current φ _2f of FIG. 3 is an alternating current φ _f as shown in FIG. 5D. It is composed.

[0030] When negative inversion pulse V _M2 the output of the magnetic-coupled logic gate 34 in this case, negative inversion pulse V _M2 is as shown in FIG. 5, the measurement signal V _O becomes positive pulse when a negative pulse, the measurement signal When V _O is a positive pulse, it becomes a negative pulse. The other points are the same as in the first embodiment.

Also in the second embodiment, the up / down counter 30A operates at the same frequency as the AC bias current I _B, and the structure of the up / down counter 30A can be simplified.

[Third Embodiment] FIG. 6 shows the SQ of the third embodiment.
3 shows a UID magnetometer. This SQUID magnetometer uses cascaded current injection type Josephson gates 38, 40 and 42 in place of the delay line 32 of FIG. 3, and instead of the magnetic field coupling type logic gate 34 of FIG. Type Josephson gate 44 and magnetic field coupling type logic gate 46 are connected in cascade.

Current injection type Josephson gates 38-44
Have the same configuration as each other and are, for example, MVTL gates (variable threshold type logic gates). The current injection type Josephson gate 38 includes, for example, a SQUID element 381, a magnetic field coupling line 382, and resistance elements R4 to R6, and SQUID.
The D element 381 has Josephson junctions J9 and J in its loop.
10 is interposed, and the Josephson junction J11 is interposed in the connection line between the SQUID element 381 and the resistance element R5. On the other hand, the magnetic field coupling type logic gate 46 has the same configuration as the magnetic field coupling type logic gate 34 of FIG.

Current injection type Josephson gates 38, 40
7 and (C) at the power input terminals of 42 and 42, respectively.
Three-phase positive pulse currents φ1, φ2, and φ3 having phases different from each other by 120 ° as shown in (D) and (E) are supplied. A negative pulse current * φ1 is supplied to the power supply input terminal of the current injection type Josephson gate 44. The negative pulse current * φ1 is the positive pulse current φ1 as shown in FIG.
Is 0 when is positive, and is negative when the positive pulse current φ1 is 0.

Current injection type Josephson gates 38-44
When the power supply current is positive, the input positive pulse is held and output while the power supply current is positive, and when the power supply current is negative,
The input negative pulse is held and output while the power supply current is negative.

The hatched portion in FIG. 7 is the positive pulse current φ1.
Two of [phi] 3 are positive, and signals are transmitted in this part. Therefore, when the AC bias current I _B and the measurement signal V _O are as shown in FIGS. 7A and 7B, only the positive pulse of the measurement signal V _O is delayed by the current injection type Josephson gates 38, 40 and 42. The delayed pulse V _D2 that moves while being moved and is output from the current injection type Josephson gate 42 becomes as shown in FIG. 7 (G).

On the other hand, current injection type Josephson gate 44
Holds and outputs only the negative pulse of the measurement signal V _O when the negative pulse current * φ1 is negative, and this negative pulse is converted into a positive pulse by the magnetic field coupling type logic gate 46 in synchronization with the positive pulse current φ3. To be done. Therefore, the magnetic field coupling type logic gate 4
The negative inversion pulse V _M3 output from 6 is as shown in FIG.

The up / down counter 30A is shown in FIG.
In synchronization with a clock CLK having a frequency fHz as shown in (I), counting is performed in the same manner as in the first embodiment, and the count value C is obtained.
N changes as shown in FIG.

Also in the third embodiment, the up / down counter 30A operates at the same frequency as the AC bias current I _B, and the structure of the up / down counter 30A can be simplified.

[0040]

As described above, the SQU according to the present invention
In the output interface circuit of the ID magnetometer, the negative inversion circuit converts the negative pulse of the measurement signal into a positive pulse and outputs it as a negative inversion pulse, and the half-cycle delay circuit outputs the measurement signal to the SQUID AC instead of the negative inversion pulse. Since the bias current is delayed by a half cycle and output as a delay pulse, the processing circuit can process the negative inversion pulse and the delayed pulse in synchronization with a clock having the same frequency as the AC bias current. This has the effect of contributing to the simplification of the configuration of the measurement signal processing circuit.

In both the first aspect and the second aspect of the present invention, the negative inverting circuit can be configured by one logic gate, so that the configuration is simplified.

In the third aspect of the present invention, the half-cycle delay circuit is composed of the delay line, so that the structure is particularly simple.

In the fourth aspect of the present invention, the half-cycle delay circuit is constructed by connecting a plurality of current injection type Josephson gates in cascade, and each current injection type Josephson gate has the same frequency as the AC bias current. Since the positive pulse of the measurement signal is delayed by operating the positive pulse currents whose phases are shifted from each other, the delay time can be easily and accurately determined.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle configuration of an output interface circuit of an SQUID magnetometer according to the present invention.

FIG. 2 is a waveform diagram showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of the SQUID magnetometer of the first embodiment of the present invention.

FIG. 4 is a waveform diagram showing the operation of the circuit of FIG.

FIG. 5 is a waveform diagram showing the circuit operation of the SQUID magnetometer of the second embodiment of the present invention.

FIG. 6 is a circuit diagram of an SQUID magnetometer according to a third embodiment of the present invention.

7 is a waveform chart showing the operation of the circuit of FIG.

FIG. 8 is a circuit diagram of a conventional SQUID magnetometer.

9 is a waveform chart showing the operation of the circuit of FIG.

[Explanation of symbols]

 10 Pickup Coil 12, 18, 341, 381 SQUID Element 14 AC Bias Current Source 16 Write Gate 20 Magnetic Coupling Line 22 Superconducting Storage Loop 24 Feedback Loop 30, 30A Up / Down Counter 32 Delay Line 34 Magnetic Field Coupling Logic Gate 36 Current Source S SQUID chip

Claims (5)

[Claims] 1. A signal line frequency fHz of the alternating current (I _B) in the measurement signal having a positive pulse and negative pulse synchronized from biased SQUID element (1) in the AC current (V _O) is taken out (L ) and, at the output interface circuit of the SQUID fluxmeter connected between the processing circuit (2) treating the measurement signal, a negative pulse positive pulse convert to this negative inversion pulse (V _M of the measurement signal ), And a half-cycle delay circuit (4) that delays the measurement signal by a half cycle of the alternating current than the negative inversion pulse and outputs this as a delay pulse (V _D ). ) And, the processing circuit processes the negative inversion pulse and the delayed pulse based on a clock of frequency fHz, and an output interface circuit of the SQUID magnetometer. 2. The negative inverting circuit (3) has a frequency of 2fH.
A positive pulse current (φ _2f ) of z is supplied to the power supply input terminal to operate, the positive pulse of the measurement signal (V _O ) is output as a positive pulse, and the negative pulse of the measurement signal is converted into a positive pulse. The output interface circuit of the SQUID magnetometer according to claim 1, which is a magnetic field coupling type logic gate (34) for outputting. 3. The negative inverting circuit (3) has a frequency fHz.
AC current (φ _f ) is supplied to the power input terminal to operate,
It is a magnetic field coupling type logic gate (34) which converts a positive pulse of the measurement signal (V _O ) into a negative pulse and outputs the negative pulse, and converts a negative pulse of the measurement signal into a positive pulse and outputs the positive pulse. An output interface circuit of the SQUID magnetometer according to claim 1. 4. The output interface circuit of the SQUID magnetometer according to claim 1, wherein the half-cycle delay circuit (4) is a delay line (32). 5. The half-cycle delay circuit (4) is formed by cascade-connecting a plurality of current injection type Josephson gates (38 to 42), and the current injection type Josephson gates are out of phase with each other. Positive pulse current of frequency f (φ1 to φ
The output interface circuit of the SQUID magnetometer according to claim 1, wherein the positive pulse of the measurement signal (V _O ) is delayed by operating in 3).