JPH06342300A - Solid state sound recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain the solid state sound recording and reproducing device which extends a sound recording time by decreasing the bit rate of speech data after recording instantaneously and securing a free area in a semiconductor memory, and also reproduces the data without any feeling of physical disorder by making the sound quantity not vary halfway in the reproduction. CONSTITUTION:This solid state sound recording and reproducing device is equipped with a hierarchic encoding means 30 which encodes a speech input signal hierarchically, semiconductor memories 50-53 having plural memory spaces which can be erased at a time, and controllers 40 and 60 which record the speech data hierarchically encoded by the hierarchical encoding means 30 in the batch-erasable memory spaces of the semiconductor memories 50-53 by layers and erases the recorded speech data by the layers at a time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state recording / reproducing apparatus which encodes and records an audio signal in a semiconductor memory, and more particularly to a solid-state recording / reproducing apparatus capable of varying the encoding bit rate.

[0002]

2. Description of the Related Art In recent years, a solid-state recording / reproducing apparatus using a semiconductor memory as a recording medium is expected as a next-generation recording / reproducing apparatus. However, at present, the semiconductor memory has a very high byte unit price as compared with other recording media such as a magnetic tape, a magnetic disk, and an optical disk, which hinders the practical application of the solid-state recording / reproducing apparatus. The signal compression technique is an effective means for effectively utilizing the semiconductor memory and putting the solid-state recording / reproducing device into practical use, but it has a problem that the recording quality is deteriorated while the compression ratio is increased. .

Therefore, various solutions have heretofore been proposed. For example, as a conventional example closest to the present invention,
There are the following.

The encoding bit rate is made variable, and when the memory capacity is sufficient, the audio signal is encoded at a high bit rate and recorded in the semiconductor memory. Next, when the remaining capacity of the semiconductor memory becomes low, the audio data recorded at a high bit rate is read from the semiconductor memory, the bit rate is reduced, and the data is re-encoded and recorded in the semiconductor memory. Reserve an empty area. By repeating this series of processes, the contradictory problems of the recording quality and the lengthening of the recording time are dealt with (see, for example, JP-A-2-305053).

[0005]

However, in such a conventional example, in order to secure an empty area in the semiconductor memory, the audio data recorded at a high bit rate is read out from the semiconductor memory, the bit rate is lowered, and the bit rate is reduced again. It was necessary to re-encode and re-record new audio data in the semiconductor memory. That is, re-encoding old audio data already recorded in the semiconductor memory,
There is a problem in that the load on the hardware is large because the encoding of the audio signal currently being recorded has to proceed at the same time.

Further, when the recording is interrupted and the power is turned off, there is a problem of what to do with the old audio data having a different bit rate for which the re-encoding remains unprocessed.

In view of the above problems, the present invention extends the recording time by instantly reducing the bit rate of audio data and securing an empty area in the semiconductor memory without the load of re-encoding on hardware. At the same time, the present invention provides a solid-state recording / reproducing apparatus that allows the user to listen to the sound without any discomfort while the sound quality does not change during the reproduction.

[0008]

To achieve this object, a solid-state recording / reproducing apparatus of the present invention comprises a hierarchical coding means for hierarchically coding a voice input signal and a plurality of batch erasable memory spaces. A semiconductor memory having the same, and a memory management means for recording the audio data hierarchically encoded by the hierarchical encoding means in a hierarchically erasable memory space of the semiconductor memory and for erasing the recorded audio data collectively in a hierarchical manner. It is equipped with.

[0009]

With the above-described structure, the present invention can extend the recording time by instantly reducing the bit rate of audio data and securing a free area in the semiconductor memory without the load of re-encoding on hardware. It will be. In addition, during playback, the sound quality does not change in the middle and you can listen to it without any discomfort.

[0010]

Embodiments of the solid-state recording / reproducing apparatus of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of a solid-state recording / reproducing apparatus according to an embodiment of the present invention.

In FIG. 1, 10 is an AD for converting an analog voice input signal into, for example, a 16-bit digital signal.
Similarly, 20 is a DA converter for converting a 16-bit digital signal into an analog signal. Reference numeral 30 receives the 16-bit digital signal output from the AD converter 10 and hierarchically encodes it into voice data, and vice versa.
A hierarchical encoder / decoder for receiving hierarchically encoded voice data, converting it into a 16-bit digital signal, and sending it to the DA converter 20, 31 is included in the hierarchical encoder / decoder 30, and an AD converter Receives the output of 10 and changes the frequency band from 0 to 2
kHz, 2-4 kHz, 4-6 kHz and 6-8 kHz
While dividing into 4 bands of z and outputting, and vice versa,
A band divider / combiner which receives signals divided into four bands and performs band combination, 32 is included in the hierarchical encoder / decoder 30, and receives a signal of 0 to 2 kHz band from the band divider / combiner 31 and outputs 2 bits. Is compressed and encoded to output, and vice versa.
A first encoder / decoder that receives and decodes a 2-bit compressed signal in the band of 2 kHz and sends it to the band divider / combiner 31;
Similarly, 33, 34 and 35 are 2 to 4 kHz,
Second, third, and fourth encoders / decoders 40 for the bands of 4 to 6 kHz and 6 to 8 kHz, and 40 for the first, second, third, and fourth encoders / decoders 32, 33, 34, and 35. 2 bit signal is received and 8 samples of data are combined for each band to form a 16 bit structure, and conversely, 16 bit structure data for each band is received and decomposed into 2-bit time series data. Memory controller, 5
0, 51, 52, and 53 are respectively connected to the memory controller 40, and can be collectively erased in chip units.
Second, third and fourth semiconductor memories, 60 is a system controller for controlling the entire system, and 70 is a control key for giving an operation instruction to the system controller 60.

The operation of the solid-state recording / reproducing apparatus having the above structure will be described below.

First, when recording is instructed by the control key 70 when the semiconductor memory is unrecorded, the following is performed.

The system controller 60 gives the memory controller 40 an instruction to check the memories of the first, second, third and fourth semiconductor memories 50, 51, 52 and 53, and the memory controller 40 is unrecorded. After confirming that there is, start recording. The analog voice input signal is converted into a 16-bit digital signal by the AD converter 10. The digital signal is 0 to 2 kHz, 2 to 4 kHz by the band divider / combiner 31.
z, 4 to 6 kHz and 6 to 8 kHz.

Next, the 0-2 kHz band signal is compressed into a 2-bit signal by the first encoder / decoder 32. Similarly, band signals of 2 to 4 kHz, 4 to 6 kHz and 6 to 8 kHz are compressed into 2-bit signals by the second, third and fourth encoders / decoders, respectively.

2 transmitted from the first encoder / decoder 32
The bit signal is reconfigured by the memory controller 40 into time series data of 8 samples into 16 bits,
Is recorded in the semiconductor memory 50 of FIG. Similarly, the second,
The 2-bit signals sent from the third and fourth encoders / decoders are reconfigured by the memory controller 40 into time-series data for 8 samples into 16 bits, and the second, third, and fourth semiconductors are reconfigured. It is recorded in the memories 51, 52 and 53. Here, the same sampling data is recorded at the same address in the first, second, third, and fourth semiconductor memories 50, 51, 52, and 53.

When recording is further continued and the remaining amount of empty space in the first, second, third and fourth semiconductor memories 50, 51, 52 and 53 becomes small, the memory controller 40
Stops writing to the third and fourth semiconductor memories 52 and 53, and the third and fourth semiconductor memories 52 and 53,
The old data of 53 is collectively erased to secure an empty area. Further recording is continued, and the first and second semiconductor memories 50, 5
When the recording to 1 is full, the memory controller 40 controls the data of the first and second encoders / decoders 32 and 33 to be written in the third and fourth semiconductor memories 52 and 53, respectively. .

Further, when recording is continued and the remaining amount of empty space in the third and fourth semiconductor memories 52 and 53 becomes small, the memory controller 40 causes the fourth semiconductor memory 5 to operate.
Writing to 3 is stopped, and the old data in the second and fourth semiconductor memories 51 and 53 are collectively erased to secure an empty area.

Recording is further continued, and the third semiconductor memory 5
When the recording in 2 is full, the memory controller 40 records the data of the first encoder / decoder 32 in the second semiconductor memory 51. Recording is further continued, and when the recording of the second semiconductor memory 51 is full, the memory controller 40 records the data of the first encoder / decoder 32 in the fourth semiconductor memory 53. When the writing of the fourth semiconductor memory 53 is full, the recording is stopped. Here, the layered information is recorded in the head address of each semiconductor memory, and when recording is started from the middle, the information of the head address is confirmed and then the recording is started according to the above sequence.

Next, the reproducing operation is as follows. If you use the control key to instruct playback, the memory controller 4
0 reads the hierarchical information recorded at the top address of each semiconductor memory, and the system controller 60 connects each semiconductor memory to each code / complexer according to the information and the phrase information designated by the control key. The 16-bit audio data of the designated semiconductor memory is returned to 2-bit 8-sample time series data by the memory controller 40, is composited by the code / combiner, and is band-combined by the band-divider / combiner. The converter 20 converts the analog audio output signal.

As described above, according to this embodiment, the hierarchical coding means for hierarchically coding the voice input signal, the semiconductor memory having a plurality of collectively erasable memory spaces, and the hierarchical coding means are used. Re-encoding to hardware by providing hierarchically encoded voice data for each layer in a batch erasable memory space of the semiconductor memory and memory management means for collectively erasing the recorded voice data for each layer It is possible to extend the recording time by instantly lowering the bit rate of the audio data and securing an empty area in the semiconductor memory without the load.
In addition, during playback, the sound quality does not change in the middle and you can listen to it without any discomfort.

Although the hierarchical coding means is band division coding here, it goes without saying that it may be embedded coding or the like. In other words, the most significant bit to represent the original audio information may be set to the most significant bit, and each bit may be sequentially weighted to be hierarchical. Although each semiconductor memory is composed of one chip (element), it may be an assembly of chips. Furthermore, it goes without saying that each semiconductor memory can be erased not only in chip units but also in byte units or block units.

Further, it is more preferable to use a flash memory as the semiconductor memory because the capacity can be increased at low cost. In particular, since the memories have a parallel configuration, there is an advantage that the disadvantage that the writing speed of the flash memory is slow is solved.

[0025]

As described above, according to the present invention, the hierarchical coding means for hierarchically coding the voice input signal, the semiconductor memory having a plurality of collectively erasable memory spaces, and the hierarchical coding means are used. Recoding the hardware by recording coded audio data in a hierarchically erasable memory space of the semiconductor memory and providing memory management means for collectively erasing the recorded audio data in a hierarchy. It is possible to provide a solid-state recording / playback device that can extend the recording time by instantly reducing the bit rate of audio data and securing an empty area in the semiconductor memory without the load of There is something. In addition, there is also an effect that the sound quality can be heard without any feeling of discomfort during reproduction without changing in the middle.

If a flash memory is used as the semiconductor memory, the capacity can be increased at low cost. In particular, since the memories have a parallel configuration, the disadvantage that the writing speed of the flash memory is slow is solved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a solid-state recording / reproducing apparatus in an embodiment of the present invention.

[Explanation of symbols]

30 Hierarchical Coder / Decoder 40 Memory Controller 50, 51, 52, 53 First, Second, Third, Fourth Semiconductor Memory

Claims (2)

[Claims] 1. Hierarchical coding means for hierarchically coding a voice input signal, a semiconductor memory having a plurality of collectively erasable memory spaces, and voice data hierarchically coded by said hierarchical coding means. A solid-state recording / reproducing apparatus, comprising: a memory management unit for recording in a erasable memory space of the semiconductor memory for each layer and for collectively erasing recorded voice data for each layer. 2. The solid-state recording / reproducing apparatus according to claim 1, wherein the semiconductor memory is a flash memory.