JPH06339088A - Voice signal demodulation circuit - Google Patents

Abstract

PURPOSE:To suppress the generation of unpleasant noise generated at the time of stopping voice data, etc., when a special reproduction is performed by using the reproduction signals of a MUSE-VTR and a MUSE disk player, etc., and to obtain continuous voice outputs even when C/N is degraded. CONSTITUTION:The number of blocks to be detected as correction impossible blocks is counted in an error correction/detection circuit 10, the number of corrected blocks to be generated within a frame is determined, and as for the frame for a period till when the number of correction impossible blocks shows a second threshold or more after it shows below a first threshold, base band voice data are demodulated by a first interpolation signal. The frame for a period till when the number shows below the first threshold after it shows the second threshold or more is demodulated by a second interpolation signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to Multiple Sub-Nyquist Sampling Encoding.
The present invention relates to an audio signal demodulation circuit of a high-definition television receiver that receives a high-definition television signal (hereinafter, simply referred to as "MUSE signal") band-compressed by a coding system (hereinafter, simply referred to as "MUSE method").

[0002]

2. Description of the Related Art As a technique for band-compressing a high-definition video signal, the MUSE system has been developed by NHK (Japan Broadcasting Corporation) and is regularly broadcast using a broadcasting satellite. This MU
In the SE method, the audio signal is multiplexed in the differential PCM format within the vertical blanking period of the video signal.

FIG. 10 is a block diagram showing a schematic structure of a conventional audio signal demodulation circuit multiplexed with a MUSE signal.

In FIG. 10, the MUSE signal input from the input terminal 1 is converted into a digital signal by the A / D conversion circuit 2 and then sent to the frequency conversion circuit 3. The frequency conversion circuit 3 converts the sample rate from 16.2 MHz to 12.15 MHz, and then the ternary-binary conversion circuit 4 converts the ternary signal into the binary signal according to the correspondence table of FIG. . The signal converted into the binary value is the difference PC in the MUSE signal by the time expansion circuit 5.
The M audio signal (hereinafter simply referred to as “DPCM signal”) is separated and extracted, and the extracted binary DPCM signal is
Converted to 1.35Mb / sec. Continuous signal.

The audio signal converted into a continuous signal by the time expansion circuit 5 has 1350 bits as one unit (hereinafter,
Interleave processing is performed for 25 frames (simply called “frame”). Therefore, the inter-frame deinterleave circuit 6 returns the data to the regular frame unit.

The frame structure of a voice signal is such that a frame synchronization pattern consisting of a 16-bit specific pattern and a 22-bit control code are added to the beginning of each frame, followed by 1312-bit voice data and independent data. Is. The control code includes control information such as a voice mode, the number of voice channels, and voice suppression, and the control code detection circuit 8 determines the control code.

Further, the frame synchronization detection circuit 7 generates a synchronization signal for each frame, that is, for every 1 msec by detecting the frame synchronization pattern, and based on this, it is necessary in the audio signal demodulation circuit. Generates various timing signals. The frame synchronization detection circuit 7 has a frame synchronization compensation function that operates as if the frame synchronization pattern was detected at a predetermined position by the built-in counter for several tens of msec even when the frame synchronization pattern is disturbed by an error in the transmission system. Have With this frame synchronization compensation function, it becomes possible to continuously demodulate voice even when C / N (carrier to noise ratio) is deteriorated.

The bit deinterleave circuit 9 performs bit deinterleaving on the inter-frame deinterleaved DPCM signal to restore the signals aligned in the row direction (sample word direction) of each one frame,
It is sent to the error correction / detection circuit 10.

The frame structure of an audio signal is such that a 16-bit frame synchronization pattern, a 22-bit control code, and subsequent 1312-bit audio data and independent data follow. This 1312-bit audio data and independent data Is divided into 16 blocks and 82 bits.
A CH error correction code is added, and it has error correction and detection capabilities. There are two correction modes, normal and enhanced, for this error correction and detection.

First, in the normal mode, according to the generator polynomial of X ⁸ + X ⁷ + X ⁴ + X ³ + X + 1, a 1-bit error in the block is corrected, and a 2-bit error is detected as an uncorrectable error.

The enhancement mode corrects errors up to 2 bits according to a generator polynomial of X ¹⁵ + X ¹⁴ + X ¹⁰ + X ⁸ + X ⁷ + X ⁴ + X ³ +1.
A 3-bit error is detected as an uncorrectable error.

The error correction processing and the detection processing are performed in the error correction / detection circuit 10, and a block having no error is a normal block, a block having a correction is a correction block, and a block having an uncorrectable error is an uncorrectable block. And

Since the error-corrected DPCM signal is interleaved in the row direction and in the sample word direction, the word deinterleave circuit 11 cancels the interleaving and restores the signal for one normal frame. The range detection circuit 12 detects a range bit from the error-corrected DPCM signal and corrects the error. The expansion circuit 13 expands the level of the output of the word deinterleave circuit 11 according to the range bit output from the range detection circuit 12. In the interpolation circuit 14, the level-expanded DPCM signal is output from the error correction / detection circuit 10 in accordance with the ED signal indicating the presence of an uncorrectable block, and the difference data before and after the difference data included in the block is continued. After being subjected to interpolation processing such as average value interpolation or “0” value interpolation using data, the integrating circuit 15 reproduces the signal as a baseband audio signal. The reproduced digital audio signal is output from the output terminal 16.

On the other hand, in the broadcasting by the MUSE system, immediately before the end of the broadcasting, the transmitting side instructs the suppression of the reproduced voice by using the 16th bit of the 22-bit control code, and then the transmission of the MUSE signal is stopped. ing.

Therefore, in the above-mentioned voice demodulation circuit for demodulating the voice signal multiplexed with the MUSE signal, the reproduced baseband voice signal is suppressed according to the 16th bit of the control code. The suppression of the reproduced baseband audio signal is maintained while the synchronization state is maintained by the frame synchronization compensation function. When the synchronization compensation period ends, the synchronization is lost, and the voice suppression due to the loss of synchronization continues the voice suppression by the control code. In this way, MUS
In the case of broadcasting by the E system, it is possible to operate so that noise does not occur when the MUSE signal is stopped.

[0016]

When a reproduction signal of a MUSE-VTR or a MUSE disc player is used as an input MUSE signal, when a sound signal is stopped during special reproduction, when a connected input signal is removed, or the like. When the MUSE signal is stopped, the input of audio data to the audio signal demodulation circuit is stopped without the audio being suppressed by the control code. Therefore, by the frame synchronization compensation function, even if there is uncertain voice data due to the stop of the input voice signal, the voice suppression is not executed immediately, and there is no control code for instructing the voice suppression. Therefore, unpleasant noise due to the stop of the audio signal is output.

As a countermeasure against this, it is conceivable to shorten the frame synchronization protection period by the frame synchronization compensation function so that the voice suppression functions early. However, when the C / N is deteriorated, the voice suppression frequently occurs. This is not desirable.

Therefore, the present invention relates to MUSE-VTR, M
It is possible to suppress the generation of unpleasant noise that occurs when the audio data is stopped during the special reproduction using the reproduction signal of the USE disc player or the like, and to output a continuous audio even when the C / N is deteriorated. It is an object to provide an audio signal demodulation circuit that can be obtained.

[0019]

A second output indicating the occurrence of an uncorrectable error and a third indicating the occurrence of a corrected error in the error correction / detection circuit of the audio signal demodulation circuit according to claim 1.
Of the second output signal and the third output signal from the error correction / detection circuit to generate a first interpolation signal. The first interpolating means, and one or more of the second output signal and the third output signal from the error correction / detection circuit
Second interpolation means for generating a second interpolation signal for instructing interpolation at a frequency higher than that of the second interpolation signal, and an uncorrectable error generated within a certain period from the second output signal from the error correction / detection circuit. Counting means for counting the number of occurrences, comparing means for selecting one of a first threshold value and a second threshold value larger than the first threshold value, and comparing with the counting result; The first interpolation signal is output for the period from when the number of uncorrectable errors is less than the first threshold to when it is more than the second threshold, and the number of uncorrectable error occurrences is the second threshold. The second interpolation signal is selected and output for the period after the value is equal to or more than the value and the value is less than the first threshold value.

A second indication that an uncorrectable error has occurred in the error correction / detection circuit of the audio signal demodulation circuit according to the second aspect.
And the third output signal indicating the occurrence of the corrected error, the interpolating signal generating circuit for generating the interpolating signal is provided with the second output signal and the third output signal from the error correcting / detecting circuit. A first interpolation means for generating a first interpolation signal from one or more of the above, and one or more of the second output signal and the third output signal from the error correction / detection circuit, which is higher than the first interpolation signal. A second interpolating signal for instructing interpolation by frequency;
Interpolation means, counting means for counting the number of uncorrectable error occurrences within a fixed period from the second output signal from the error correction / detection circuit, and the uncorrectable error occurrence count and a predetermined threshold. A holding means for holding a plurality of comparison results with the value, and either one of the first interpolation signal and the second interpolation signal is selected and output from the plurality of held comparison results.

According to a third aspect of the present invention, there is provided a voice signal demodulation circuit according to the first or second aspect of the present invention, further comprising a noise amount detection circuit for obtaining a noise component of an input signal and detecting the noise amount. , And a threshold value setting circuit for setting a threshold value according to the detected noise amount.

A voice signal demodulating circuit according to a fourth aspect is the voice signal demodulating circuit according to the first or second aspect, in which the ternary signal of the input MUSE signal is converted into a binary signal in the time axis direction. Inputs a discontinuous ternary audio signal that is compressed into 3 and converts it from binary to binary -3
Time for inputting binary data which is the first output signal of the value conversion circuit and the three-value conversion circuit to return an audio signal to a continuous data string and outputting the output to the inter-frame deinterleave circuit. A decompression circuit, a lost data counter for determining the frequency of occurrence of lost data indicating the presence of ternary and binary uncorresponding data which is the second output signal of the ternary to binary conversion circuit, and generation of the lost data. A threshold value setting circuit for setting a threshold value based on the frequency is added.

[0023]

According to the present invention, the number of blocks detected as uncorrectable blocks in the error correction / detection circuit is counted, and the number of corrected blocks generated in one frame is obtained. Baseband audio data is demodulated by the first interpolation signal for a frame in a period until the number of uncorrectable blocks in the frame is less than the first threshold value and is more than the second threshold value. . In addition to a conventional uncorrectable block, a frame of a period after the second threshold value or more is displayed and then a period until the first threshold value is displayed is a correction block,
A second interpolation signal is generated for a block that cannot be corrected or a block following the correction block. In the interpolation circuit, for the data of the block instructed to be interpolated by the interpolation signal,
Baseband audio is demodulated by performing interpolation processing such as average value interpolation or “0” value interpolation using continuous difference data before and after.

According to a second aspect of the present invention, a function of holding a plurality of comparison results with the number of correction blocks generated in one frame or a predetermined threshold value is provided, and a plurality of held comparison results are used as a first interpolation signal. Either one of the second interpolation signals is selected and output, and interpolation processing such as average value interpolation or “0” value interpolation is performed by using the difference data before and after continuous, and the baseband audio is demodulated.

In claim 3, the input MUSE
Extract the noise component of the signal and pay attention to the fact that a stable baseband audio signal can be reproduced when the noise component is small, and set the threshold value to suppress the noise generated when the input audio signal stops. . On the other hand, when there are many noise components, remarkably generated noise occurs in the reproduced baseband audio signal, making it difficult to distinguish the noise generated when the input audio signal is stopped from the noise generated by the reproduction. Since it is preferable to continuously demodulate the baseband audio signal even if the C / N is deteriorated, C / N
The threshold value is set so that continuous reproduction can be performed even when N is deteriorated.

In the fourth aspect, in place of the noise in the third aspect, in the three-value to two-value conversion, the data having no correspondence from the three-value format to the two-value format, that is, the occurrence frequency of the lost data is three.
The detection is performed according to the correspondence table of the value-binary conversion, and the threshold value is controlled based on the frequency of occurrence of lost data.

[0027]

Embodiments of the audio signal demodulation circuit of the present invention will be described below. In the figure, the same reference numerals and symbols as those of the conventional example indicate the same or corresponding components as those of the conventional example, and therefore, duplicated description is omitted here.

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of an audio signal demodulation circuit of the present invention. 2 is a block diagram showing a first example of the interpolation signal generating circuit in FIG. 1, FIG. 3 is an explanatory diagram showing the interpolation signal selecting operation in FIG. 2, and FIG. 4 is a diagram of the first embodiment shown in FIG. It is a timing diagram which shows an interpolation signal generation operation.

In the first embodiment shown in FIG. 1, an interpolation signal generation circuit 17 is added to the circuit configuration of the conventional audio signal demodulation circuit shown in FIG. Interpolation signal generation circuit 17
Is two signals from the error correction / detection circuit 10 indicating the correction / detection state, that is, E indicating the existence of an uncorrectable block.
The D signal and the EC signal indicating the presence of the correction block are input, and operate according to the frame cycle timing signal FP from the frame synchronization detection circuit 7 and the error correction / detection processing block cycle timing signal LP in the error correction / detection circuit 10. Then, the interpolation signal EF is output.

A concrete example of the interpolation signal generating circuit 17 is shown in FIG.

In FIG. 2, one frame delay circuit 21,
22 is an ED signal indicating the presence of the uncorrectable block,
The EC signal indicating the presence of the correction block is delayed for one frame period, and the ED1 signal and the EC1 signal are output in the order corresponding to the output signal from the word deinterleave circuit 11. The first logic gate 23 receives the ED1 signal and generates a first interpolation signal EF1. Second logic gate 24
Inputs the ED1 signal and the EC1 signal and outputs the first interpolation signal E
The second interpolation signal EF that instructs the interpolation at a higher frequency than F1
2 is generated.

In addition, the counter 26 receives the first threshold value B1 or the second threshold value selected by the switch 28 from the terminal PD.
The threshold value B2 is loaded according to the timing signal FP. Next, the timing signal L input from the terminal CK
When the ED signal input from the terminal ET indicates the occurrence of an uncorrectable block with P as a clock, the timing signal LP
To count down. Then, when the count value becomes "0", the counter 26 sends out a carry from the terminal TC, and the carry passes through the inversion gate 27,
The terminal EP of the counter 26 is entered to instruct to stop the counter 26. As a result, when the number of uncorrectable blocks generated in one frame is less than the value loaded from the terminal PD, the counter 26 outputs no carry from the terminal TC (low level). In this state (high level), the next timing signal FP is input.
Then, the flip-flop 29 outputs the timing signal FP.
According to the output of the terminal TC of the counter 26,
6 holds just before loading, and outputs as the status signal FI0 of the frame. The switch 28 selects the first threshold value B1 when the FI0 signal of the flip-flop 29 is at the high level and selects the second threshold value B2 when the signal is at the low level, and causes the counter 26 to be loaded. At this time, the first
Threshold value B1 <second threshold value B2 (B1 <B2).

As a result, a carry is output when the number of uncorrectable blocks generated in one frame is equal to or greater than the value loaded from the terminal PD, and the FI0 signal of the flip-flop 29 is the number of uncorrectable blocks generated in each frame. Accordingly, it changes as shown in FIG. In FIG. 3, the number of uncorrectable blocks generated for each frame and the first
The threshold B1 and the second threshold B2 are shown in the upper row, and the FI0 signal is shown in the lower row. Assuming that the FI0 signal is low level in the initial state, the switch 28 selects the second threshold value B2. When the number of uncorrectable blocks generated exceeds the second threshold value B2, the FI0 signal changes to high level. As a result, the switch 28 selects the first threshold value B1. Then, next, the FI0 signal changes to the low level when the number of uncorrectable blocks generated becomes less than the first threshold value B1. By controlling the FI0 signal in this manner, it is possible to prevent the FI0 signal from changing frequently due to the deterioration of C / N of the input signal.

The switch 25 outputs the first interpolation signal EF1 as the interpolation signal EF when the FI0 signal is at the low level and outputs the second interpolation signal EF2 as the interpolation signal EF when the signal is at the high level. For example, the interpolation signal EF is generated as shown in FIG. Note that, in FIG. 4, the generation of the interpolation signal is conceptually described so that it can be easily described, and the operation of the counter 26 is omitted.

In FIG. 4, the first interpolation signal EF1 is
The ED signal indicating the existence of the uncorrectable block is delayed by one frame period, and the ED1 signal corresponding to the output signal from the word deinterleave circuit 11 is left unchanged, while the second interpolation signal EF2 is the EC signal indicating the existence of the correction block. The word deinterleave circuit 11 is delayed by one frame period.
The logical sum of the EC1 signal corresponding to the output signal from
When the FI0 signal is high level, the output E of the switch 25
When the EF1 signal is low level as the F signal, the EF2 signal is output, and the logic of the EF signal is switched depending on the state of the FI0 signal.

As described above, in the audio signal demodulation circuit of the present embodiment, the bit deinterleave circuit 9 for removing the bit interleave of the audio input signal processed on the transmitting side and the output signal of the bit deinterleave circuit 9 are used. Error correction / detection circuit 1 for performing error correction / error detection
0, a word deinterleave circuit 11 for canceling the word interleave processed on the transmission side for the corrected data which is the first output signal of the error correction / detection circuit 10, and the error correction / detection circuit 10. A range detection circuit 12 that detects a range bit from the first output signal and corrects the error, and the word deinterleave circuit 1 according to the range bit that is the output signal of the range detection circuit 12.
A decompression circuit 13 for decompressing the output of No. 1, a second output indicating the occurrence of an uncorrectable error and a third output signal indicating the occurrence of a corrected error in the error correction / detection circuit 10 are input, and an interpolation signal is input. An interpolating signal generating circuit 17 for generating the interpolating signal, an interpolating circuit 14 for interpolating the output of the decompressing circuit 13 based on the interpolating signal from the interpolating signal generating circuit 17, and an output of the interpolating circuit 14 are integrated to demodulate into an audio signal. Integrating circuit 1
5, the interpolation signal generation circuit 17 generates a first interpolation signal from one or more of the second output signal and the third output signal from the error correction / detection circuit 10 and the one-frame delay circuit 21. And a first interpolating means consisting of a logic gate 23, and one or more of the second output signal and the third output signal from the error correction / detection circuit 10 to instruct interpolation at a higher frequency than the first interpolation signal. Generate a second interpolated signal 1
Second frame delay circuit 22 and logic gate 24
And the second error correction circuit 10 from the error correction / detection circuit 10.
Counting means including a counter 26 that counts the number of uncorrectable errors that occur within a certain period of time from the output signal of the second output signal, a first threshold value B1 and a second threshold value that is larger than the first threshold value B1. Comparing means using the load and carry function of the counter 26 for selecting one of B2 and comparing it with the counting result; and after the number of uncorrectable errors is less than the first threshold value B1, the second Of the first interpolated signal for a period until the threshold value B2 or more of
Second for the period until it is less than the first threshold B1
Is selected and output. This structure corresponds to the embodiment of claim 1.

Therefore, EF1 having a low interpolation instruction frequency for frames from when the number of uncorrectable blocks generated in one frame is less than the first threshold value B1 to when it is more than the second threshold value B2. Signal to a second threshold B2
An EF2 signal having a high interpolation instruction frequency is output as an interpolation signal EF with respect to the frames from the above to the point below the first threshold value B1.

That is, the interpolation circuit 14 outputs the interpolation signal EF.
EF1 whose interpolation instruction frequency is low for the data instructed by
Interpolation processing is performed using a signal or an EF2 signal with a high interpolation instruction frequency.

FIG. 5 is a block diagram showing a second example of the interpolation signal generation circuit in FIG. 1, which is another configuration example of the interpolation signal generation circuit 17 in FIG. Specifically, this is an example in which the generation portion of the FI0 signal for switching the switch 25 in the block diagram of FIG. 2 is changed.

In FIG. 5, the counter 31 is reset according to the timing signal FP input from the terminal RE. Next, the timing signal L input from the terminal CK
When the ED signal indicating the existence of the uncorrectable block input from the terminal ET by using P as a clock indicates the occurrence of the uncorrectable block, it is counted up. The flip-flop 32 holds the count result output from the terminal Q of the counter 31 immediately before the counter 31 is reset by the timing signal FP according to the frame cycle timing signal FP from the frame synchronization detection circuit 7. The held output of the flip-flop 32 indicates the number of times the uncorrectable block is generated in the frame. The comparison circuit 33 compares the number of occurrences of the uncorrectable block with one of the first threshold value B1 and the second threshold value B2 selected by the switch 28, and determines the FI0 signal in the state of the frame. The state in which the number of occurrences of the uncorrectable block is larger is output as a high level, and the state in which the number is smaller is output as a low level. Further, the flip-flop 34 holds the FI1 signal in the state one frame before the frame. If the FI1 signal in the state one frame before is high level, the first threshold value B1 is set to low level. If there is, the second threshold value B2 is selected by the switch 28 and input to the comparator 33. At this time, B1 <B2.

That is, the FI0 signal in the frame state operates the switch 25, and if the FI0 signal is at a low level, the EF1 signal having a low interpolation instruction frequency with respect to the data instructed by the interpolation signal EF is at a high level. If there is, an EF2 signal with a high interpolation instruction frequency is selected and output as the interpolation signal EF.

As described above, when the interpolation signal generating circuit 17 is configured as shown in FIG. 5, the number of uncorrectable blocks generated in one frame is the first, as in the case of the circuit shown in FIG.
Of less than the threshold value B1 of the frame to the second threshold value B2 or more of the frame having a low interpolation instruction frequency E.
EF2 is output as EF, which has a high interpolation instruction frequency for frames from when F1 is greater than or equal to the second threshold value B2 to when it is less than the first threshold value B1.

By the way, although the configuration examples of the interpolation signal generating circuit 17 are shown in FIGS. 2 and 5, when the present invention is carried out,
The configuration of the interpolation signal generating circuit 17 is not limited,
An interpolation signal that is less frequently instructed to be interpolated for a period from when the number of occurrences of uncorrectable errors is less than the first threshold value B1 to when it is greater than or equal to the second threshold value B2 is It suffices as long as it is configured to output an interpolation signal having a high frequency of instructing interpolation for a period from when the threshold value B2 is equal to or more than B2 to when the threshold value is less than the first threshold value B1.

Further, the logic gate 23 of the interpolation signal generating circuit 17 generates the first interpolation signal EF1 having a low interpolation instruction frequency for the uncorrectable block, and the logic gate 22 performs the second interpolation signal having a high interpolation instruction frequency. Although it has been described that the signal EF2 is generated for the uncorrectable block and the corrected block, when the present invention is implemented, the logic gates 22,
The interpolation signal generating means in 23 is not limited, and any generation logic may be used as long as different thresholds having high and low interpolation instruction frequencies can be set (EF1 <EF2).

FIG. 6 is a block diagram showing a first example of the interpolation signal generating circuit in the second embodiment of the audio signal demodulating circuit of the present invention, and FIG. 7 is an explanatory diagram showing the interpolation signal selecting operation in FIG. .

In particular, in this embodiment, the generation portion of the signal FI0 for switching the switch 25 is changed in the block diagram of the embodiment shown in FIG.

In FIG. 6, the counter 26 loads the threshold value B from the terminal PD in accordance with the timing signal FP. Next, the timing signal L input from the terminal CK
When the ED signal indicating the existence of the uncorrectable block input from the terminal ET by using P as a clock indicates the occurrence of the uncorrectable block, it counts down. When the count value becomes "0", the counter 26 sends out a carry from the terminal TC, and the carry instructs the terminal EP of the counter 26 to stop the counter 26 via the inversion gate 27. Therefore, if the number of uncorrectable blocks generated in one frame is equal to or less than the threshold value B loaded from the terminal PD, the counter 26 generates no carrier (low level) from the terminal TC and occurs in one frame. If the number of uncorrectable blocks exceeds the threshold value B loaded from the terminal PD,
When the carry is output (high level), the next timing signal FP is input.

The flip-flops 35, 36 and 37 operate according to the timing signal FP, and the terminal T of the counter 26.
A delay circuit for holding the output of C for 3 frames is configured. The output of the gate 38 is output to the three flip-flops 35, 3 with respect to the terminal DS of the SR-flip-flop 40.
When the outputs of 6, 37 are all at the high level, the output FI0 of the SR-flip-flop 40 is instructed to be at the high level. The output of the gate 39 is output to the three flip-flops 35, 3 with respect to the terminal DR of the SR-flip-flop 40.
When the outputs of 6, 37 are all at the low level, the output FI0 of the SR-flip-flop 40 is instructed to be at the low level.

As a result, the output FI0 of the SR-flip-flop 40 changes as shown in FIG. 7 according to the number of uncorrectable blocks generated in each frame. The number of uncorrectable blocks generated and the threshold value B for each frame are shown in the upper stage, and the output FI0 of the SR-flip-flop 40 is shown in the lower stage. In the initial state, the output FI of the SR-flip-flop 40
0 is a low level. When the number of uncorrectable blocks generated in one frame exceeds the threshold value B three times in succession according to the timing signal FP of the flip-flops 35, 36 and 37, the FI0 output changes to high level. Even if the threshold B is sporadically exceeded, the FI0 signal does not change to the high level. Next, the output FI0 of the SR-flip-flop 40 changes to the low level is
This is when the number of uncorrectable blocks generated falls below the threshold value B three times in a row, and the FI0 signal does not change to the low level even if the number of occurrences of the uncorrectable block falls below the threshold value B one by one. By controlling the FI0 signal in this way, it is possible to prevent the output FI0 of the SR-flip-flop 40 from changing frequently due to the deterioration of the C / N of the input signal.

The switch 25 is the SR-flip-flop 4
If the output FI0 of 0 is low level, the EF1 signal having a low interpolation instruction frequency with respect to the data is selected, or if the output FI0 is high level, the EF2 signal having a high interpolation instruction frequency is selected, and the interpolation signal E is selected.
Output as F.

As described above, in the audio signal demodulation circuit of the present embodiment, the bit deinterleave circuit 9 for removing the bit interleave of the audio input signal processed on the transmission side and the output signal of the bit deinterleave circuit 9 are used. Error correction / detection circuit 1 for performing error correction / error detection
0, a word deinterleave circuit 11 for canceling the word interleave processed on the transmission side for the corrected data which is the first output signal of the error correction / detection circuit 10, and the error correction / detection circuit 10. A range detection circuit 12 that detects a range bit from the first output signal and corrects the error, and the word deinterleave circuit 1 according to the range bit that is the output signal of the range detection circuit 12.
A decompression circuit 13 for decompressing the output of No. 1, a second output indicating the occurrence of an uncorrectable error and a third output signal indicating the occurrence of a corrected error in the error correction / detection circuit 10 are input, and an interpolation signal is input. An interpolating signal generating circuit 17 for generating the interpolating signal, an interpolating circuit 14 for interpolating the output of the decompressing circuit 13 based on the interpolating signal from the interpolating signal generating circuit 17, and an output of the interpolating circuit 14 are integrated to demodulate into an audio signal. Integrating circuit 1
5, the interpolation signal generation circuit 17 generates a first interpolation signal from one or more of the second output signal and the third output signal from the error correction / detection circuit 10 and the one-frame delay circuit 21. And a first interpolating means consisting of a logic gate 23, and one or more of the second output signal and the third output signal from the error correction / detection circuit 10 to instruct interpolation at a higher frequency than the first interpolation signal. Generate a second interpolated signal 1
Second frame delay circuit 22 and logic gate 24
And the second error correction circuit 10 from the error correction / detection circuit 10.
A plurality of comparison results of the counting means composed of a counter 26 for counting the number of uncorrectable error occurrences occurring within a certain period from the output signal of No. 1 and the number of uncorrectable error occurrences and a predetermined threshold value B are held. Flip-flops 35, 36,
The holding means composed of 37 and one of the first interpolation signal and the second interpolation signal is selected and output from the plurality of held comparison results. This configuration corresponds to the embodiment of claim 2.

By the way, an example in which the result of comparison between the number of uncorrectable blocks generated in one frame and the threshold value B is held for three frames by using the flip-flops 35, 36 and 37 is shown. Does not limit the number of times the comparison result is held. Also, switch 2
Although an example using the gates 38 and 39 and the SR-flip-flop 40 as means for changing the FI0 signal for switching 5 is shown, in the case of implementing the present invention, a plurality of comparisons holding the state FI0 signal of the frame are performed. Any configuration may be used as long as it is determined from the result.

FIG. 8 is a block diagram of the audio signal demodulating circuit according to the third embodiment of the present invention.

The basic difference between this embodiment and the embodiment shown in FIG. 1 is that the noise amount detection circuit 19 and the threshold value setting circuit 1 are
8 is added.

In FIG. 8, the noise amount detection circuit 19 detects the noise amount by extracting high frequency components from the output of the A / D conversion circuit 2. The threshold value setting circuit 18 sets a high threshold value so that continuous reproduction can be performed when the noise amount is large according to the noise amount output from the noise amount detection circuit 19, that is, when the C / N is deteriorated. When the amount of noise is small, that is, when C / N is high, the threshold value is set low so that noise generated when the input audio signal is stopped can be suppressed. The interpolation signal generation circuit 17 outputs the interpolation signal EF according to the threshold value input from the threshold value setting circuit 18.

As described above, in this embodiment, the noise amount detection circuit 19 for obtaining the noise component of the input signal and detecting the noise amount in the circuit of the first or second embodiment described above is detected.
And a threshold value setting circuit 18 for setting a threshold value according to the detected noise amount are added, and this configuration corresponds to the embodiment of claim 3.

Since the operation of the audio signal demodulation circuit of this embodiment is basically the same as that of the embodiment of FIG. 1, its explanation is omitted.

Although the high-frequency component is extracted as the noise amount detection circuit 19 and is controlled by the noise amount here, when the present invention is implemented, the noise amount detection circuit 19 uses C / It may measure N. Further, the threshold value set by the threshold value setting circuit 18 has two threshold values, but in the case of implementing the present invention, either or both of the two threshold values are set. Can be a threshold of.

FIG. 9 is a block diagram of a voice signal demodulating circuit according to a fourth embodiment of the present invention.

The basic difference between this embodiment and the embodiment shown in FIG. 1 is the configuration in which a lost data counter 20 and a threshold value setting circuit 18 are added.

In FIG. 9, the ternary / binary conversion circuit 4 generates an erasure signal when it confirms the occurrence of erasure data according to the ternary / binary conversion correspondence table shown in FIG. The erasure data counter 20 receives the erasure signal and calculates the number of erasure data generations per unit time. Threshold setting circuit 1
In No. 8, in accordance with the number of lost data generated per unit time output from the lost data counter 20, the threshold value is set high so that a continuous audio signal can be reproduced when the number of generated data is large, and when the number of generated data is small, , Set the threshold low so that the noise generated when the input audio signal stops is suppressed. In the interpolation signal generation circuit 17,
The interpolation signal EF is output according to the threshold value input from the threshold value setting circuit 18.

As described above, in the present embodiment, the circuit of the first or second embodiment described above is compressed in the time axis direction in which the input ternary signal of the MUSE signal is converted into a binary signal. A ternary-binary conversion circuit 4 for inputting a discontinuous ternary audio signal and converting the ternary form into a binary form, and a first output signal of the ternary-binary conversion circuit 4. A second output signal of the time-decompression circuit 5 for returning the audio signal to a continuous data string with binary data as an input and outputting the output to the inter-frame deinterleave circuit 6, and the ternary-binary conversion circuit 4. And a threshold value setting circuit 18 for setting a threshold value on the basis of the frequency of occurrence of the lost data. It is added. This structure corresponds to the embodiment of claim 4.

Since the operation of the audio signal demodulation circuit of this embodiment is basically the same as that of the embodiment of FIG. 1, its explanation is omitted.

The threshold value set by the threshold value setting circuit 18 has two threshold values, but when the present invention is carried out, one of the two threshold values is set. One or both thresholds can be set. The first interpolation signal EF1 at that time and the second interpolation signal EF2 for instructing interpolation at a frequency higher than that of the first interpolation signal EF1 are generated. However, a plurality of interpolation signals may be prepared.

[0065]

As described above, in the audio signal demodulating circuit of the invention of claim 1, the number of correction blocks generated in the frame detected as the uncorrectable block in the error correction / detection circuit is calculated, and The audio data is demodulated by the first interpolation signal during the period from the number of uncorrectable blocks being less than the first threshold value to the second threshold value or more, and from the second threshold value or more to the second threshold value or more. A second interpolation signal is generated for a correction block, a block that cannot be corrected or a block following the correction block, in addition to a conventional uncorrectable block, for a period of time until it becomes less than a threshold value of 1.
In response to this, the interpolation circuit performs interpolation processing such as average value interpolation or “0” value interpolation on the difference data before and after continuous processing on the data of the block instructed by the interpolation signal, Demodulate banded audio. Therefore, it is possible to suppress the generation of unpleasant noise that occurs when the voice data is stopped, obtain a continuous voice output even when the C / N is deteriorated, and generate when the input voice data is interrupted. It is possible to minimize the unpleasant noise that occurs and to continuously demodulate the sound when the C / N is deteriorated, and sound during special reproduction using a reproduction signal of a MUSE-VTR, MUSE disc player, or the like. It is possible to suppress the generation of unpleasant noise that occurs when data is stopped.

In the audio signal demodulating circuit according to the second aspect of the present invention, a function for holding a plurality of correction blocks generated in one frame or a comparison result with a predetermined threshold value is provided.
One of the first interpolation signal and the second interpolation signal is selected from the plurality of held comparison results and output, and interpolation processing such as average value interpolation or “0” value interpolation using consecutive difference data before and after To demodulate the baseband audio. Therefore, it is possible to suppress the generation of unpleasant noise that occurs when the voice data is stopped, obtain a continuous voice output even when the C / N is deteriorated, and generate when the input voice data is interrupted. Minimizes unpleasant noise,
Furthermore, it becomes possible to continuously demodulate voice when C / N is deteriorated, and MUSE-VTR, MUSE
It is possible to suppress the generation of unpleasant noise that occurs when audio data is stopped during special reproduction using a reproduction signal from a disc player or the like.

In the audio signal demodulating circuit according to the third aspect of the invention, paying attention to the fact that a stable baseband audio signal can be reproduced when the noise component of the input MUSE signal is extracted and the noise component is small. Set the threshold value to suppress the noise generated when the input audio signal stops. On the other hand, when there are many noise components, remarkably noise is generated in the reproduced baseband audio signal, and it is difficult to distinguish the noise generated when the input audio signal is stopped or the generated noise from the reproduced noise. Since it is preferable to continuously demodulate the baseband audio signal even when the C / N is deteriorated, the threshold value is set so that continuous reproduction can be performed even when the C / N is deteriorated. Therefore,
The same effects as those of claims 1 and 2 are obtained, and the reliability thereof is better than that of the inventions of claims 1 and 2.

In the audio signal demodulation circuit of the invention of claim 4, in place of the noise of claim 3, the data which does not correspond to the ternary format from the ternary format in the ternary-binary conversion, that is,
The occurrence frequency of the lost data is detected according to the correspondence table of three-value conversion, and the threshold value is controlled based on the occurrence frequency of the lost data. Therefore, the same effects as those of the first and second aspects are achieved, and the reliability thereof is better than that of the inventions of the first and second aspects.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of an audio signal demodulation circuit of the present invention.

FIG. 2 is a block diagram showing a first example of the interpolation signal generation circuit in FIG.

FIG. 3 is an explanatory diagram showing an interpolation signal selection operation in FIG.

FIG. 4 is a timing diagram showing an interpolation signal generating operation of the first embodiment shown in FIG.

5 is a block diagram showing a second example of the interpolation signal generation circuit in FIG.

FIG. 6 is a block diagram showing a first example of an interpolation signal generation circuit in a second embodiment of the audio signal demodulation circuit of the present invention.

FIG. 7 is an explanatory diagram showing an interpolation signal selection operation in FIG. 6;

FIG. 8 is a block diagram showing a schematic configuration of a third embodiment of the audio signal demodulation circuit of the present invention.

FIG. 9 is a block diagram showing a schematic configuration of a voice signal demodulation circuit according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a schematic configuration of a conventional audio signal demodulation circuit multiplexed with a MUSE signal.

FIG. 11 is a correspondence table showing ternary / binary conversion.

[Explanation of symbols]

 9-bit deinterleave circuit 10 Error correction / detection circuit 11 Word deinterleave circuit 12 Range detection circuit 13 Expansion circuit 14 Interpolation circuit 15 Integration circuit 17 Interpolation signal generation circuit 18 Threshold setting circuit 19 Noise amount detection circuit 20 Loss data counter 21 , 22 1 frame delay circuit 23, 24 logic gate 26 counter

Claims (4)

[Claims] 1. A bit deinterleave circuit for decompressing bit interleave of a voice input signal processed on a transmitting side, and an error correction / detection circuit for performing error correction / error detection on an output signal of the bit deinterleave circuit. ,
From the word deinterleave circuit for solving the word interleave processed on the transmitting side for the corrected data which is the first output signal of the error correction / detection circuit, and the first output signal of the error correction / detection circuit. A range detection circuit that detects a range bit and performs error correction; a decompression circuit that decompresses the output of the word deinterleave circuit according to the range bit that is the output signal of the range detection circuit;
An interpolation signal generating circuit for generating an interpolation signal by inputting a second output indicating the occurrence of an uncorrectable error and a third output signal indicating the occurrence of a corrected error in the error correction / detection circuit; An interpolation circuit that interpolates the output of the expansion circuit based on an interpolation signal from the generation circuit, and an integration circuit that integrates the output of the interpolation circuit and demodulates into an audio signal, wherein the interpolation signal generation circuit is the error correction circuit. / A first interpolating means for generating a first interpolating signal from one or more of the second output signal and the third output signal from the / detecting circuit; a second output signal from the error correcting / detecting circuit; Second interpolating means for generating a second interpolating signal instructing interpolation from one or more of the three output signals at a higher frequency than the first interpolating signal; and a second output signal from the error correction / detection circuit. Correction error that occurs within a certain period from Counting means for counting the number of error occurrences, and comparing means for selecting one of a first threshold value and a second threshold value larger than the first threshold value and comparing with the counting result. The first period is the period from when the number of uncorrectable errors is less than the first threshold value to when it is more than the second threshold value.
The interpolating signal is output by selecting the second interpolating signal for the period after the number of uncorrectable error occurrences is equal to or greater than the second threshold value and is less than the first threshold value. An audio signal demodulation circuit characterized by the above. 2. A bit deinterleave circuit for removing bit interleave of a voice input signal processed on the transmitting side, and an error correction / detection circuit for performing error correction / error detection on an output signal of the bit deinterleave circuit. ,
From the word deinterleave circuit for solving the word interleave processed on the transmitting side for the corrected data which is the first output signal of the error correction / detection circuit, and the first output signal of the error correction / detection circuit. A range detection circuit that detects a range bit and performs error correction; a decompression circuit that decompresses the output of the word deinterleave circuit according to the range bit that is the output signal of the range detection circuit;
An interpolation signal generating circuit for generating an interpolation signal by inputting a second output indicating the occurrence of an uncorrectable error and a third output signal indicating the occurrence of a corrected error in the error correction / detection circuit; An interpolation circuit that interpolates the output of the expansion circuit based on an interpolation signal from the generation circuit, and an integration circuit that integrates the output of the interpolation circuit and demodulates into an audio signal, wherein the interpolation signal generation circuit is the error correction circuit. / A first interpolating means for generating a first interpolating signal from one or more of the second output signal and the third output signal from the / detecting circuit; a second output signal from the error correcting / detecting circuit; Second interpolating means for generating a second interpolating signal instructing interpolation from one or more of the three output signals at a higher frequency than the first interpolating signal; and a second output signal from the error correction / detection circuit. Correction error that occurs within a certain period from Counting means for counting the number of error occurrences; holding means for holding a plurality of comparison results between the uncorrectable error occurrence counts and a predetermined threshold; and a first interpolation signal based on the plurality of held comparison results. An audio signal demodulation circuit which selects and outputs one of the second interpolation signals. 3. A noise amount detection circuit for obtaining a noise component of an input signal and detecting the noise amount, and a threshold value setting circuit for setting a threshold value according to the detected noise amount. The audio signal demodulation circuit according to claim 1 or 2. 4. A ternary format audio signal that is compressed in the time axis direction and is converted into a binary signal from a ternary signal of an input MUSE signal is input, and the ternary format is converted to a binary format. A three-value-two-value conversion circuit to be converted and two-value data which is the first output signal of the three-value-two-value conversion circuit are input, and an audio signal is returned to a continuous data string, and the output thereof is set to the interframe deinterlacing. A time expansion circuit for outputting to the interleave circuit,
Based on the occurrence frequency of the disappearance data, a disappearance data counter for obtaining the occurrence frequency of the disappearance data indicating the existence of the ternary and binary uncorresponding data which is the second output signal of the ternary-to-binary conversion circuit. The audio signal demodulating circuit according to claim 1 or 2, further comprising a threshold value setting circuit for setting a threshold value.