JPH06338913A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To more quickly decode data by remarkably reducing the arithmetic quantity of a branch metric calculation circuit of a viterbi estimating part. CONSTITUTION:This viterbi decoder is provided with a synchronizing signal data detection means 3 detecting a synchronizing signal data part from a reception signal data group, a transmission line characteristic estimating means 4 deciding the transmission model of impulse response between a transmitter and a receiver through the use of synchronizing signal data detected by the synchronizing signal data detection means 3 and RAM 5 into which a symbol value sent from a transmission line equivalent model is calculated and written by each frame. The branch metric calculation circuit 21 reads out the symbol value from this RAM 5 and uses it to decode a transmission data group by using viterbi algorithm based on the transmission model.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder suitable for use in, for example, automobile telephones.

[0002]

2. Description of the Related Art In the United States, Europe and Japan, car telephone system digitalization is in progress. In mobile communication such as this car telephone, due to the influence of so-called multipath due to the presence of a high-rise building between the mobile station and the base station at high speed like a car, the transmission characteristics between the base station and the mobile station However, data transmission with few errors was difficult. Moreover, this equivalent transmission characteristic changes from moment to moment.

In such a mobile communication system, an equalization technique for correcting such transmission characteristics is indispensable in order to realize reception with few errors.

As a conventional equalization technique, a Viterbi decoder has been proposed which decodes transmission data based on maximum likelihood sequence estimation by using transmission characteristics between a base station and a mobile station.

The basic configuration of this Viterbi decoder is as shown in FIG. 3. Here, the Viterbi equalizer shown in FIG. 3 is a GSM (Group Special Moval) system adopted in European car telephones. An example applied to is described below.

In FIG. 3, the received signal supplied to the input terminal 1 is supplied to the branch metric calculation circuit 21 constituting the Viterbi estimation unit 2 and the received signal is supplied to the synchronization signal data detection unit 3 for synchronization. The synchronization signal data from the signal data detector 3 is supplied to the transmission line characteristic estimator 4.

The speech channel from the GSM system base station adopted in Europe to the mobile station (automobile) has a frame structure as shown in FIGS. 4A and 4B. As shown in FIG. 4B, a sync signal pattern (SYNC pattern) having a known pattern is added to the central portion of each time slot, and the time slot is used by the transmission path characteristic estimator 4. Then, the impulse response (hereinafter referred to as the channel response) of the transmission system interposed between the transmitter and the receiver is estimated.

In the case of this GSM system, a modulation system called GMSK (Gaussian minimum shift keying) is adopted, but since the high frequency transmission system is converted into a baseband signal by passing through a demodulator, it will be explained below. In order to simplify, we will proceed with signal processing in the baseband.

In this GSM system, eight types of data series are designated in advance as the synchronization signal pattern,
One of them is shown in FIG. A conventional general procedure for modeling a channel response using this synchronization signal pattern will be described.

Now, the case where the channel response is as shown in FIG. 6 is taken as an example (in reality, this channel response is unknown). In FIG. 6, the unit in the time axis direction is equal to the symbol transmission interval. The sync signal pattern of FIG. 6 is the sync signal pattern of FIG. The synchronization signal data received when passing through the transmission system having such a channel response is expressed by the following equation.

[0011]

[Equation 1] Here, y _i is a received signal, x _i is a synchronization signal pattern, h _i
Represents the channel response. The values are sampled at the symbol time intervals T, respectively.

When the received signal corresponding to the sync signal pattern portion is calculated according to equation 1, an output signal as shown in FIG. 6 is obtained. On the receiver side, the known information is the sync signal pattern x _i and the received signal y _i .

In the conventional modeling procedure of the transmission path characteristic estimating section 4, first, the synchronization signal data section is detected by taking the correlation between the received signal and the synchronization signal pattern.

Next, the cross-correlation function r _j between the sync signal data portion and the sync signal pattern is calculated.

[0015]

[Equation 2]

Next, normalization is performed using the maximum value of this cross-correlation function r _j . The cross-correlation function calculated in this way is shown in FIG. The branch metric calculation circuit 21 estimates the channel response by this cross-correlation function.
Supply to.

After estimating this channel response, the transmission data sequence is decoded using the Viterbi algorithm. FIG. 7 shows a generalized transmission line equivalent model. Here, the example of FIG. 8 in which the generalized transmission path equivalent model of FIG. 7 is modeled by specifically limiting its channel response length will be described.

When modeled as shown in FIG. 8, it can be regarded as a convolutional encoder with constraint length = 4 and coding rate r = 1/1. However, the difference from the normal convolutional encoder is that the adder 71 performs a linear operation and the shift registers T ₀ , T ₁ , T ₂ and T ₃
The symbol input to is a binary value of <+1> and <-1>, and each output of the shift register is weighted corresponding to the channel responses h _-1 , h ₀ , h ₊₁ and h _+2. These are two points that are added by the adder 71 after the addition.

The symbol G transmitted in the case of modeling in this way is expressed by the following equation.

[0020]

[Equation 3] Here, <T _j > represents the contents stored in the register T _j .

FIG. 9 shows a trellis diagram showing the transition of the internal states of the transmission line in the transmission line equivalent model shown in FIG. The three-letter alphabet corresponding to each state node S _i in FIG. 9 represents the internal state of the shift register in each time slot. Here, since the shift register takes the values of <+1> and <-1>, they are represented as H and L for convenience of expression. In addition, in FIG. 9, a grid structure diagram that is normally used is modified so that a solid line is used when the information input symbol <-1> is input, and a broken line is used when the information input symbol <+1> is input. It indicates that the transition as shown occurs.

On the other hand, the received signal data Y _k is input to the branch metric calculation circuit 21 to calculate the likelihood of its transition. Although some metrics have been proposed for measuring the likelihood, the Hamming distance, which is the most general evaluation measure in Viterbi decoder, is applied in a broad sense.

The branch metric at the time slot t (k) is calculated by the following equation.

[0024]

Equation 4] _{b (k, S i → S} n) = | Y k -G k | , where, Y _k is the received signal data and a symbol G _k is transmitted from the equivalent transmission path model , Takes the value calculated by Equation 3.

The branch metric obtained by the branch metric calculation circuit 21 is referred to as ACS (Add Compare Sele).
ct) Supply to the circuit 22. The ACS circuit 22 is composed of an adder, a comparator, and a selector. In each state, the branch metric and the path metric of one time slot before stored in the path metric storage circuit 23 are added to obtain the value. The smaller one is selected as the likely survival path. Here, the path metric is a value obtained by adding the branch metrics in the surviving paths.

The output signal of the ACS circuit 22 is supplied to the path metric storage circuit 23 via the normalization circuit 24, and the output signal of the ACS circuit 22 is supplied to the maximum likelihood path detection circuit 25.

The maximum likelihood path detection circuit 25 detects a path having the minimum path metric value and outputs the contents of the path memory 26 corresponding to the path as decoded data. The path memory 26 is a memory for estimating and storing an information bit string.

FIG. 10 shows a logical unit constituting this Viterbi decoder. In FIG. 10, each metric represents the following contents.

P (k-1, S _i ): Time slot t
Path metric P (k-1, _Sj ) of the surviving path reaching the state node S _i at (k-1): Path of the surviving path reaching the state node S _j at the time slot t (k-1) Metric b (k, S _i → S _n ): Branch metric b (k, S _j → S _n ): time slot t corresponding to the transition from the state node S _i to the state node S _n in the time slot t (k). The branch metric corresponding to the transition from the state node S _j to the state node S _n in (k)

M (k-1, S _i ): Time slot t
Path memory M (k-1, _Sj ) of the surviving path reaching the state node S _i at (k-1): Path of the surviving path reaching the state node S _j at the time slot t (k-1) memory <-1>, <+1>: time slot t (k) information symbols are estimated to have been delivered in P (k, S _n): survivor path reaching the state node S _n in time slot t (k) Path metric possessed M (k, S _n ): Path memory possessed by the surviving path reaching the state node S _n at time slot t (k)

Here, assuming that the constraint length is k, the number of states is 2
Since there are only ^k−1, the number of logical units shown in FIG. 10 basically requires the number of states 2 ^k−1 . Further, as in the block configuration of the Viterbi decoder shown in FIG.
In general, 4 is provided to reduce the scale of the path metric storage circuit 23 and prevent overflow during the calculation of the path metric.

As a concrete process of this normalization, first, the minimum value of the path metric is detected, and then the value is subtracted from each path metric amount. The number of surviving paths selected in this way is 2 ^{k−1, which} is the same as the number of states.

In each time slot, the operation of selecting the surviving path and the operation of updating the path metric and the path memory 26 corresponding to that path are repeated. It is known that, if this operation is performed for a sufficiently long time, it is merged into the same path before a certain time, and this state is shown in FIG. The length of the path from the latest processing time point to the time when the paths are merged is called the truncated path length.

The method of updating the path memory shown in FIG. 10 is determined according to each state. For example, the logical unit of "LLL" is determined as <-1>, the logical unit of "HLL" is determined as <+1>, and so on.

In the maximum likelihood judgment, the path having the minimum path metric value is detected, and the contents of the path memory corresponding to the path are cut off and traced back by the path length (usually set to 3 to 4 times the constraint length). It is output as an information symbol at that time.

The flow of signal processing of this conventional Viterbi decoder will be described with reference to the flowchart of FIG. First, a sync signal pattern is detected when the received signal data _Yk is supplied to the input terminal 1 (step S1), and the cross-correlation between the sync signal pattern of the received signal data _Yk and the previously stored sync signal pattern is detected. The function is calculated in the transmission path characteristic estimation unit 4 (step S2) and the channel response is estimated (step S3). Next, the branch metric calculation circuit 21 calculates a branch metric (step S4), and then starts calculation for the Nth state (step S5).

Next, the state-1 address one time slot before is set (step S6), the path metric stored in the path metric storage circuit 23 of this set address is read (step S7), and this path is set. The metric is added to the branch metric calculated in step S4 by the ACS circuit 22, and the addition output is added to the register P.
1 (step S8).

Next, in step S9, the address of the state-2 one time slot before is set, the path metric stored in the path metric storage circuit 23 of this set address is read (step S10), and this path metric is read. Is added to the branch metric calculated in step S4 by the ACS circuit 22, and the added output is stored in the register P2 (step S11).

Next, the ACS circuit 22 compares and stores the values stored in the registers P1 and P2 (steps S12 and S13) and outputs the selected value (step S14). The metric storage circuit 23 is updated (step S15) and the path memory 26 is updated (step S16).

Steps S5 to S16 described above
The processes up to are repeated by the number of states 2 ^k-1 (step S
17). After the above processing is completed, the maximum likelihood path detection circuit 2
The path having the minimum path metric value is detected by 5 (step S18), and the normalization processing is performed by subtracting the minimum value of the path metric from each path metric amount (step S19).

Then, the maximum likelihood path detection circuit 25 sets the address of the maximum likelihood path (step S20) and outputs the contents of the path memory 26 as decoded data (step S).
21).

[0042]

In the Viterbi estimation unit 2 of such a conventional Viterbi decoder, each data of the received signal (for the received signal as shown in FIG. 4B, the data in one time slot is 116). It is necessary to calculate the symbol value G transmitted from the equivalent transmission path equivalent model based on the equation 3, and the total amount of this calculation becomes very large, and this calculation takes time, and the transmission characteristics can be estimated at high speed. There was an inconvenience that I could not do it.

In view of the above point, the present invention has an object to significantly reduce the operation amount of the branch metric calculation circuit of the Viterbi estimation unit and enable faster decoding.

[0044]

A Viterbi decoder according to the present invention includes a sync signal data detecting means 3 for detecting a sync signal data portion in a received signal data sequence as shown in FIGS. 1 and 2, and this sync signal data. Using the synchronization signal data detected by the detection means 3, the transmission path characteristic estimation means 4 for determining the transmission model of the impulse response between the transmitter and the receiver, and the symbol value sent from the transmission path equivalent model are calculated. 1
It has a RAM 5 that is calculated and written for each frame,
The branch metric calculation circuit 21 reads the symbol value from the RAM 5 and uses it to decode the transmission data sequence using the Viterbi algorithm based on this transmission model.

[0045]

According to the present invention, after the estimation of the impulse response, which is performed once in one frame, is completed, the symbol value G is calculated for all the internal states of the shift register in the transmission line equivalent model and written in the RAM 5, and the transmission model is calculated. In order to decode the transmission data sequence using the Viterbi algorithm based on
Since the symbol value G is read out and used more, there is no need to calculate the symbol value G sent from the transmission path equivalent model for each data of the received signal, and the calculation amount can be reduced accordingly, and the speed can be increased. Can be decrypted.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the Viterbi decoder of the present invention will be described below with reference to FIGS. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the example of FIG. 1 as well, the received signal supplied to the input terminal 1 is supplied to the branch metric calculation circuit 21 that constitutes the Viterbi estimation unit 2 and this received signal is supplied to the synchronization signal data detection unit 3 and this synchronization signal data is supplied. The synchronization signal data from the detection unit 3 is supplied to the transmission path characteristic estimation unit 4.

In estimating the channel response in the transmission path characteristic estimating section 4, the channel response is modeled as shown in FIG. The signal y _i expected to be received if modeled in this way
Is expressed by the above-mentioned equation 1.

On the other hand, when the signal actually received is represented by Y _i , the error regarding the i-th symbol is represented by the following equation.

[0049]

(5) e _i = y _i −Y _i

The sum of squares of this error is obtained by the following equation.

[Equation 6]

In the transmission line characteristic estimation unit 4, this error
Impulse train h to minimize _nTo decide
However, in this example, LMS (maximum
Small mean square) algorithm is used.

In this LMS algorithm, the impulse response sequence h _j is updated according to the procedure shown in the following equation.

[Equation 7]

Here, j represents the j-th tap of the FIR (finite length impulse response) filter, n represents the nth update when updating, and α is the step gain (0 <α
≦ 1), K is the number of times of averaging in the process of averaging the estimation error, y is the sample value of the received signal input to the equivalent filter, and e is the equalization error.

This equalization error e is e = e _out -r, where e _out is the equalization filter output signal,
r is a reference numeral.

When this LMS method is used, it is necessary to set some initial value as the impulse response sequence. FIG. 13 shows the number of updates and the convergence result when the value shown in FIG. 13 is given as the initial value. At this time, the step gain α = 0.500.

After identifying this channel response, the Viterbi algorithm is used to decode the transmission data sequence. However, in order to simplify the explanation, the channel response length of the general model shown in FIG. Let us continue with the example of FIG.

When modeled as shown in FIG. 8, it can be regarded as a convolutional encoder having a constraint length k = 4 and a coding rate r = 1/1 as described above. The difference from the normal convolutional encoder is that the adder 71 performs a linear operation and the symbols input to the shift registers T ₀ , T ₁ , T ₂ and T ₃ are <+1> and <-1>. Is a value,
The _two outputs of the shift registers T ₀ , T ₁ , T ₂ , and T ₃ are added by the adder 71 after weighting corresponding to the channel response.

The symbol value G transmitted in the case of modeling in this way can be calculated by the equation 3. A trellis diagram showing the transition of the internal state of the transmission line in the transmission line model shown in FIG. 8 is as shown in FIG.

In FIG. 9, the three-letter alphabet corresponding to each state node S _i represents the internal state of the shift registers T ₁ , T ₂ , T ₃ in each data.
Here, the shift register takes the values of <+1> and <-1>, and therefore is represented as H and L for convenience of expression. This Figure 9
Then, by modifying the grid structure diagram that is normally used, the transitions shown by the solid line when the information input symbol <-1> is input, and by the broken line when the information input symbol <+1> is input. Is generated.

In this example, the transmission path characteristic estimating unit 4 uses one channel.
Estimation of the channel response once
After finishing, for example, in the transmission line equivalent model shown in FIG.
Shift register T in₀, T₁, T₂, T₃Internal state of
For all 16 states, the symbol value G is set to
Calculate and write to RAM5 which is the symbol memory to send
I will do it. In this case, the address of RAM5 is shift
Dista T₀, T₁, T ₂, T₃The internal state of
The contents (symbol value G) are as shown in Table 1 below.

[0061]

[Table 1]

Here, the estimation result by the LMS method shown in FIG. 13 is used as the channel response coefficient sequence. In this example, RA, which is this sending symbol memory
The contents (G) of M5 are rewritten every frame.

Further, in this example, the symbol value G written in the RAM 5 is appropriately read out to the branch metric calculation circuit 21 and used for calculation. That is, since the received signal Y _k is input to the branch metric calculation circuit 21 and the likelihood regarding the transition thereof is calculated, the Hamming distance, which is the most general evaluation measure in the Viterbi decoder, is used to measure this likelihood in a broad sense. Applied.

Now, the branch metric in the time slot t (k) is calculated by Equation 4, and in this Equation 4, Y _k is the received data, G _k is the symbol value sent from the transmission path equivalent model, and is read from the RAM 5. Be done.

Others are similar to those of the conventional Viterbi decoder described with reference to FIG. This detailed description is omitted.

The flow of signal processing of the Viterbi decoder of this example will be described with reference to the flowchart of FIG. First, when the received signal data Y _k is supplied to the input terminal 1, the sync signal pattern portion is detected (step S1). The detection of the sync signal pattern portion is performed by correlating the received signal data Y _k with the sync signal pattern stored in advance.

Next, in the transmission path characteristic estimating section 4, the impulse response between the transmitter and the receiver is modeled by using the least mean square method with the detected synchronizing signal pattern section as a reference signal (step). The channel response is estimated together with S2) (step S3).

Next, the shift register in the transmission line equivalent model
Star T₀, T₁, T₂, T₃For all internal states of
The shift value G is calculated (step S4).
T ₀, T₁, T₂, T₃Address of the internal state of
The data is written in the RAM 5 (step S5). Frame period
It is judged whether or not the process is completed (step S6), and the frame
If it is within the period, the symbols written in this RAM5
The value G is read (step S7), and the branch
Calculation is performed (step S8). The frame period ends
If so, steps S1, S2, S3. S4, S5
repeat.

After the branch metric calculation circuit 21 calculates the branch metric (step S8), the calculation for the Nth state is subsequently started (step S9).

Next, the address of the state-1 one time slot before is set (step S10), the path metric stored in the path metric storage circuit 23 of this set address is read (step S11), and this path is set. The metric and the branch metric calculated in step S8 are added by the ACS circuit 22, and the added output is stored in the register P1 (step S12).

Next, in step S13, the address of the state-2 one time slot before is set, the path metric stored in the path metric of this set address is read (step S14), and this path metric is read in step S8. Calculated branch metric and ACS
The circuit 22 performs addition, and the addition output is stored in the register P2 (step S15).

Next, the ACS circuit 22 compares and selects the values stored in the registers P1 and P2 (steps S16 and S17), outputs the selected value (step S18), and passes the value. The metric storage circuit 23 is updated (step S19) and the path memory 26 is updated (step S20).

Steps S9 to S20 described above
The processes up to are repeated by the number of states 2 ^k-1 (step S
21). After the above processing is completed, the maximum likelihood path detection circuit 2
The path having the minimum path metric value is detected by 5 (step S22), and the normalization process is performed by subtracting the minimum value of the path metric from each path metric amount (step S23).

Subsequently, the maximum likelihood path detection circuit 25 sets the address of the maximum likelihood path (step S24) and outputs the contents of the path memory 26 as decoded data (step S).
25).

According to this example, after the estimation of the channel response, which is performed once in one frame, is completed, the shift registers T ₀ , T ₁ , T ₂ , T in the transmission path equivalent model are calculated.
For all ₃ internal states, calculate the symbol value G and R
Since the branch metric calculation circuit 21 reads the symbol value G from the RAM 5 and uses it for writing in the AM5 and decoding the transmission data sequence using the Viterbi algorithm based on the transmission model, each data of the reception signal is used. It is not necessary to calculate the symbol value G transmitted from the transmission path equivalent model for each time, and the calculation amount can be reduced accordingly.
It has the benefit of faster decryption.

In the above embodiment, all the internal states of the shift register in the transmission line equivalent model are written in the RAM 5, but when the channel response length is lengthened, the capacity of the RAM 5 becomes large. The capacity of the RAM 5 can be reduced by writing not all the internal states of the shift register but writing one part and using the other parts together with the sequential calculation by the equation 3.

Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0078]

According to the present invention, the shift registers T ₀ , T ₁ , T ₂ , T ₃ in the transmission line equivalent model are calculated after the impulse response estimation, which is performed once in one frame, is completed.
The symbol value G for all internal states of
To write to M5 and decode the transmission data sequence using the Viterbi algorithm based on the transmission model, the branch metric calculation circuit 21 uses the symbol value G from RAM5.
Is read and used, the symbol value G sent from the transmission path equivalent model for each data of the received signal
Need not be calculated, the amount of calculation can be reduced accordingly, and there is an advantage that decoding can be performed faster.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoder of the present invention.

FIG. 2 is a flowchart for explaining an embodiment of a Viterbi decoder of the present invention.

FIG. 3 is a configuration diagram showing a Viterbi decoder.

FIG. 4 is a diagram for explaining the present invention.

FIG. 5 is a diagram for explaining the present invention.

FIG. 6 is a diagram used for explaining the present invention.

FIG. 7 is a diagram showing a generalized transmission line equivalent model.

FIG. 8 is a diagram showing an embodied transmission line equivalent model.

FIG. 9 is a diagram showing a trellis representation.

FIG. 10 is a diagram showing a logical unit of a Viterbi decoder.

FIG. 11 is a diagram showing metric calculation and survivor paths.

FIG. 12 is a flowchart for explaining a conventional Viterbi decoder.

FIG. 13 is a diagram for explaining the present invention.

[Explanation of symbols]

 1 Input Terminal 2 Viterbi Estimator 3 Synchronous Signal Data Detector 4 Transmission Line Characteristic Estimator 5 RAM 21 Branch Metric Calculation Circuit

Claims (2)

[Claims] 1. A synchronizing signal data detecting means for detecting a synchronizing signal data part in a received signal data sequence, and a synchronizing signal data detected by the synchronizing signal data detecting means for use in a transmitter and a receiver. A transmission path characteristic estimating means for determining a transmission model of an impulse response between the two, and a RAM for calculating and writing a symbol value sent from the equivalent transmission path model for each frame, and based on the transmission model A Viterbi decoder, wherein a branch metric calculation circuit is adapted to read a symbol value from the RAM for use in decoding a transmission data sequence using a Viterbi algorithm. 2. The Viterbi decoder according to claim 1, wherein
A Viterbi decoder characterized in that an internal state value of a shift register used in the transmission path equivalent model is used as an access address of the RAM.