JP3329002B2 - Diversity receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver suitable for use in a digital mobile communication system such as a mobile phone.

[0002]

2. Description of the Related Art Generally, a high-rise building or the like is interposed between a base station and a mobile station that moves at a high speed such as an automobile telephone, so that the transmission between the base station and the mobile station is affected. Since the characteristics are greatly deteriorated, it has been difficult to transmit data with few errors. In addition, the equivalent transmission characteristics change every moment.

In such a mobile communication system, in order to realize reception with less errors, a reception system capable of coping with such fluctuations in transmission characteristics is required. As one of them, a diversity reception system has been conventionally known.

FIG. 15 shows a conventional diversity receiver called the most practical selective combining method. In FIG. 15, reference numerals 1a and 1b denote reception branches, respectively, and the respective reception branches 1a and 1b are reception antennas 2a, 2b.
b, high-frequency circuits 3a and 3b, mixing circuits 4a and 4b, intermediate frequency circuits 6a and 6b, and detection circuits 7a and 7b, and have a local oscillation circuit 5 in common.

The output signals of the detection circuits 7a and 7b of the reception branches 1a and 1b are supplied to a selector circuit 8 and the output signals of the intermediate frequency circuits 6a and 6b are supplied to a signal intensity comparison circuit 9. The signal strength comparing circuit 9 compares the signal strengths of the receiving branches 1a and 1b,
The selector circuit 8 selects the output signal of the receiving branch having the higher signal strength, and supplies it to the output terminal 10. Therefore, in the example of FIG. 15, the reception data can be obtained at the output terminal 10 from the detection circuit of the reception branch where the reception signal strength is maximum.

[0006]

However, in the digital data transmission system, the magnitude of the signal level does not always correspond to the quality of the error rate on a one-to-one basis.
The conventional diversity receiver as shown in (1), when used in a car telephone or the like for transmitting the above-mentioned digital data, has a disadvantage that optimum received data is not always obtained.

[0007] In view of the above, it is an object of the present invention to provide a diversity receiver capable of obtaining optimum received data even when used in a digital mobile communication system such as a car telephone.

[0008]

As shown in FIGS. 1 and 2, a diversity receiver according to the present invention has a plurality of, for example, two reception branches 1a and 1b for receiving digital data. A synchronization data detecting means 23 for detecting a synchronization signal data portion from a reception signal data sequence in each of the reception branches 1a and 1b, a synchronization pattern table 25 having a synchronization signal pattern specified in advance, the synchronization signal data portion and An impulse response estimating means 24 for calculating a cross-correlation function with a synchronization signal pattern; an initial value determining means 28 for calculating an initial value of a tap coefficient of the transversal filter 21 based on the normalized cross-correlation function; The output signal of the transversal filter 21 and the synchronization signal data portion and the synchronization signal pattern An automatic estimating unit including an error estimating unit for detecting an error of the tap coefficient, and a filter coefficient setting unit 27 for setting and updating the tap coefficient in accordance with an output from the error estimating unit 26; An equalization error determining means for comparing the absolute value levels of the equalization errors of the automatic equalizing means of the plurality of receiving branches, and the equalization error determining means determines that the equalization error is minimum. The received data demodulated by the received reception branches 1a and 1b are used.

A diversity receiver according to the present invention is, for example, as shown in FIGS. 6 and 7, a diversity receiver having a plurality of, for example, two reception branches 1a and 1b for receiving digital data.
Are provided with a synchronous data detecting means 33 for detecting a synchronous signal data portion from the received signal data sequence, and a signal between the transmitter and the receiver is provided by using the synchronous signal data portion detected by the synchronous data detecting means 33. A transmission path characteristic estimating means for modeling an impulse response; estimating a transmission data sequence by using a Viterbi algorithm based on a transmission model in the plurality of receiving branches; , 1b, the likelihood of the path metric having the surviving path is compared, and the reception branch 1a, 1b determined as the most likely path is determined.
The content of the path metric b is used as demodulated data.

[0010]

According to the present invention, a plurality of receiving branches 1a,
1b, the equalization errors of the automatic equalizers 11a and 11b are compared,
Since the reception data demodulated in the reception branch having the minimum equalization error is used, the best reception data can be obtained.

According to the present invention, a plurality of receiving branches 1
By comparing the likelihood of the path metric having the surviving path in a and 1b and using the content of the path metric of the receiving branch determined as the most likely path as demodulated data, the best received data can be obtained. .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the diversity receiver according to the present invention will be described below with reference to FIGS. In FIG. 1, portions corresponding to those in FIG. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, reference numerals 1a and 1b denote reception branches. These reception branches 1a and 1b are respectively provided with reception antennas 2a and 2b and a high-frequency circuit 3 as in the example of FIG.
a, 3b, mixing circuits 4a, 4b, intermediate frequency circuits 6a, 6
b, detection circuits 7a and 7b, and a common local oscillation circuit 5
have.

In this example, the detection circuits 7a and 7a
The respective output signals of b are supplied to automatic equalizers 11a and 11b, and the demodulated signals obtained at the outputs of the automatic equalizers 11a and 11b are supplied to the selector circuit 8, respectively.

In this embodiment, GSM (Group Special Mobal) which is a kind of TDMA (Time Division Multiplexing) which is a digital car telephone system in Europe.
An example applied to the method will be described.

In this GSM system, a communication channel from a base station to a mobile station (vehicle) has a frame configuration as shown in FIG. 5A. That is, a 1250-bit unit frame is constituted by eight time slots each composed of 156.25 bits, which is 4.615 msec.
It has become.

As shown in FIG. 5B, the contents of one time slot include a 26-bit periodic signal data portion provided substantially at the center and a 58-bit digital data portion provided before and after the synchronization signal data portion. Consists of

In the GSM system, eight types of data sequences are specified in advance as a synchronization signal pattern of the synchronization signal data portion, and one of them is shown in FIG. 5C.

The automatic equalizers 11a and 11b are configured as shown in FIG.

That is, in FIG. 2, reference numeral 20 denotes a detection circuit 7a,
7b shows a reception signal input terminal to which a reception signal obtained through a time-division multiplexing demodulator as shown in FIGS. 5A, 5B and 5C is supplied, and a reception signal supplied to this reception signal input terminal 20. In the case of the GSM system, the signal employs a modulation system called GMSK (Gaussian minimum shift keying), and the high-frequency transmission system is converted into a baseband signal by passing through a demodulator. To do so, we will proceed with the signal in baseband.

The received signal supplied to the received signal input terminal 20 is supplied to an output terminal 22 via an equalizer 21 composed of a transversal filter. This transversal filter 21 includes n delay circuits D ₁ , D
_{2 {} D _n and n + 1 tap coefficients C ₀ , C ₁ , C ₂ }
It is the same as a generally known one composed of a multiplier for multiplying ‥ C _v and an adder 21a.

Further, the received signal obtained at the input terminal 20 is supplied to a synchronous data detecting circuit 23 for detecting the synchronous data portion in FIG. 5B of the received signal, and is also supplied to an impulse response estimating circuit 24.

The synchronization data detection circuit 23 compares the synchronization signal pattern specified in advance with a synchronization signal pattern stored in the synchronization pattern table 25 and detects the correlation. In this case, the synchronization pattern table 25 is shared by the automatic equalizers 11a and 11b of the reception branches 1a and 1b.

The synchronous signal data portion of the received signal obtained on the output side of the synchronous data detecting circuit 23 is
And to the impulse response estimation circuit 24.

The error estimating circuit 26 is supplied with a synchronization signal pattern specified in advance from the synchronization pattern table 25, and is supplied with an output signal of the equalizer 21 so that the LM
S (least mean square) algorithm or RLS
(Recursive least squares) algorithm (Kalman algorithm) using a filter coefficient setting circuit 27
Transversal filter 21 constituting the equalizer
Tap coefficients C ₀ , C ₁ , C ₂ ‥‥ C _n are updated successively. For example, when the LMS algorithm is used, updating is performed according to the procedure shown in the following equation.

[0026]

(Equation 1) Here, j represents the j-th tap of the transversal filter 21, n represents the n-th update at the time of updating,
α is the step gain (0 <α ≦ 1), K is the number of times of averaging in the process of averaging the estimation error, y is the sample value of the received signal input to the equalizer 21, and e is the equalization error. , E = e _out -a e _out is an output signal of the equalizer, and a is a reference signal.

The synchronization signal pattern from the synchronization pattern table 25 is supplied to the impulse response estimation circuit 24. In the impulse response estimation circuit 24, the synchronization signal data portion of the reception signal and the synchronization signal pattern (SYN
C pattern).

[0028]

(Equation 2)

Here, x (iT) is a synchronization signal pattern, h
(IT) is an impulse response, and T is one symbol time length. On the receiver side, the known information is the synchronization signal pattern x (iT) and the received signal y (iT).

In this case, the impulse response of the transmission system interposed between the transmitter and the receiver is as shown in FIG. 4, and one of eight synchronization signal patterns in the GSM system.
When one of the streams has the synchronization signal pattern (SYNC pattern) of FIG. 4 (corresponding to FIG. 5C), the synchronization signal data portion of the received signal is represented by the following equation.

[0031]

(Equation 3)

Here, normalization is performed using the maximum value of the cross-correlation function value according to the equation (2). The cross-correlation function calculated in this way is as shown in FIG. 4. As can be seen by comparing the impulse response of FIG. 4 with the cross-correlation function, the impulse response can be estimated from this cross-correlation function. I can do it.

The cross-correlation function from the impulse response estimating circuit 24 is supplied to an initial value determining circuit 28. The initial value determining circuit 28 Fourier-transforms the cross-correlation function to obtain R (f). From this R (f), the transfer characteristic of the inverse filter is obtained. E (f) = 1 / R (f)

The transfer characteristic of the inverse filter is subjected to Fourier inverse transform, and the output value is used as the initial value of the tap coefficients C ₀ , C ₁ , C ₂ ‥‥ C _n of the transversal filter 21 constituting the equalizer. Are supplied to the multipliers of the transversal filter 21 via the filter coefficient setting circuit 27, respectively.

In this case, the initial value may be set only at the beginning of use of the receiver, or may be set every frame or every several frames.

The operation of the example of FIG. 2 will be described with reference to the flowchart of FIG. The receiving branch 1a using this example,
When reception is started in 1b, first, the synchronization data detection circuit 23 searches the synchronization signal data portion of the received signal (steps S1 and S2). If the synchronization signal data portion is not detected, the search is continued. When the data portion is detected, the impulse response estimation circuit 2
In step 4, a cross-correlation function between the synchronization signal data portion of the received signal and a synchronization signal pattern from a synchronization pattern table 25 specified in advance is calculated (step S3), and normalized (step S4).

Next, the Fourier transform is performed on the cross-correlation function normalized by the initial value determination circuit 28 (step S).
5) The transfer characteristic of the inverse filter is obtained from the obtained value R (f) (step S6).

The transfer characteristic of this inverse filter is subjected to Fourier inverse transform (step S7), and this is set as the initial value of the tap coefficient, and the tap coefficient of the transversal filter 21 constituting the equalizer is set via the filter coefficient setting circuit 27. Initialize (step S8).

Next, the operation of the transversal filter 21 as an equalizer is started (step S9). After the operation of the transversal filter 21, the error estimating circuit 26
In step S10, an error in the tap coefficient of the transversal filter 21 is detected from the output signal of the transversal filter 21, the synchronization signal data portion and the synchronization signal pattern (step S10).
, The tap coefficients C ₀ , C ₁ , and C ₂ ‥‥ C _n of the transversal filter 21 are updated (step S
11, S12). When the error is smaller than the predetermined value, the above operation is terminated.

In this example, the receiving branch 1
The respective equalization errors e obtained by the automatic equalizers 11a and 11b of a and 1b are supplied to the equalization error determination circuit 12, and the equalization error determination circuit 12 determines that the equalization error e is small. The demodulated signal obtained at the output terminal 24 of the automatic equalizer of the receiving branch is obtained at the output terminal 10 as received data.

In the example of FIG. 1, the reception branch 1
The equalization errors e of the automatic equalizers 11a and 11b of a and 1b are compared, and the reception data demodulated in the reception branch having the minimum equalization error e is used, so that the best reception data can be obtained. There is a benefit.

FIGS. 6 to 13 show another embodiment of the present invention. 6 to 13. In FIG. 6, parts corresponding to those in FIGS. 1 and 15 are denoted by the same reference numerals. In the example of FIG. 6 as well, a plurality of, for example, two reception branches 1a and 1b are provided.

The receiving branches 1a and 1b correspond to FIG.
Receiving antennas 2a, 2b high-frequency circuit 3 respectively as in the example
a, 3b mixing circuits 4a, 4b, intermediate frequency circuits 6a, 6
b, detection circuits 7a and 7b, and a common local oscillation circuit 5
have.

In this example, the detection circuits 7a and 7a
The respective output signals b are supplied to Viterbi equalizers 13a and 13b, and the demodulated signals obtained at the outputs of the Viterbi equalizers 13a and 13b are supplied to the selector circuit 8, respectively.

The Viterbi equalizers 13a and 13b are configured as shown in FIG. In FIG. 7, the received signal supplied to the input terminal 30 is supplied to the branch metric calculation circuit 32 constituting the Viterbi estimating unit 31, and the received signal is supplied to the synchronous data detecting unit 33. The synchronization signal data is supplied to the transmission path characteristic estimating unit 34.

The communication channel from a GSM base station to a mobile station (vehicle) adopted in Europe has a frame structure as shown in FIGS. 5A and 5B. As shown in FIG. 5B, each time slot is transmitted with a synchronization signal pattern (SYNC pattern) having a known pattern added at the center thereof.
Then, an impulse response (hereinafter, referred to as a channel response) of a transmission system interposed between a transmitter and a receiver is estimated using the synchronization signal pattern.

In the case of the GSM system, a modulation system called GMSK (Gaussian minimum shift keying) is adopted. However, since the high-frequency transmission system is converted into a baseband signal by passing through a demodulator, it will be described below. Let us proceed as signal processing in baseband to simplify.

In this GSM system, eight types of data sequences are specified in advance as synchronization signal patterns.
One of them is shown in FIG. 5C. A conventional general procedure for modeling a channel response using this synchronization signal pattern will be described.

Now, a case where the channel response is as shown in FIG. 4 will be taken as an example (actually, this channel response is unknown). In FIG. 4, the unit in the time axis direction is equal to the symbol transmission interval. The synchronization signal pattern in FIG. 4 is the synchronization signal pattern in FIG. 5C. The synchronization signal data received when passing through a transmission system having such a channel response is expressed by the following equation.

[0050]

(Equation 4) Where y _i is the received signal, x _i is the synchronization signal pattern, h _i
Represents a channel response. The values are sampled at symbol time intervals T.

When the received signal corresponding to the synchronization signal data part is calculated according to the equation 4, an output signal as shown in FIG. 4 is obtained. In this receiver, a known information is a synchronous signal pattern x _i and the received signal y _i.

In the conventional modeling procedure of the transmission path characteristic estimating unit 34, first, a synchronization signal data part is detected by correlating a received signal with a synchronization signal pattern.

Next, a cross-correlation function r _j between the synchronization signal data portion and the synchronization signal pattern is calculated.

[0054]

(Equation 5)

Next, normalization is performed using the maximum value of the cross-correlation function r _j . FIG. 4 shows the cross-correlation function calculated in this manner. The channel response is estimated by the cross-correlation function, and the branch metric calculation circuit 32
To supply.

After estimating the channel response, the transmission data sequence is decoded using the Viterbi algorithm. FIG. 9 shows a generalized transmission line equivalent model. Here, the example of FIG. 10 in which the generalized transmission path equivalent model of FIG. 9 is modeled by specifically limiting its channel response length will be described.

When modeling as shown in FIG. 10, it can be regarded as a convolutional encoder with constraint length = 4 and coding rate r = 1/1. However, the difference from the normal convolutional encoder is that the adder 71 performs a linear operation and that the shift registers T ₀ , T ₁ , T ₂ and T ₃
Symbols input is weighted corresponding to <+1> and a 2 value between <-1>, and each output of the shift register channel response h _-1, h _0, h ₊₁ and h ₊₂ to After that, two points are added by the adder 71.

The symbol G transmitted in the case of modeling as described above is expressed by the following equation.

[0059]

(Equation 6) Here, <T _j > represents the contents stored in the register T _j .

FIG. 11 is a trellis diagram showing the transition of the internal state of the transmission line in the transmission line equivalent model shown in FIG. The three-letter alphabet corresponding to each state node S _i in FIG. 11 represents the internal state of the shift register in each time slot. Here, since the shift register takes values of <+1> and <-1>, it is represented as H and L for convenience of expression. In FIG. 11, a modification is made to the grid structure diagram that is usually used, and the information input symbol <-1> is input with a solid line, and the information input symbol <+1> is input with a broken line. This indicates that a transition as shown occurs.

On the other hand, the received signal data Y _k is input to the branch metric calculation circuit 32, and the likelihood regarding the transition is calculated. Although some metrics have been proposed as metrics for measuring the likelihood, the Hamming distance, which is the most common evaluation measure in a Viterbi decoder, is broadly applied.

The branch metric at the time slot t (k) is calculated by the following equation.

[0063]

B (k, S _i → S _n ) = | Y _k −G _k | where Y _k is received signal data, and G _k is a symbol transmitted from the equivalent transmission path model. , Take the value calculated by equation (6).

The branch metric obtained by the branch metric calculation circuit 32 is converted into an ACS (Add Compare Sele
ct) to the circuit 35. The ACS circuit 35 includes an adder, a comparator, and a selector. In each state, the branch metric and the path metric one time slot before stored in the path metric storage circuit 36 are added and the result is added. Is selected as a likely survival path. Here, the path metric is a value obtained by adding the branch metrics in the surviving path.

The output signal of the ACS circuit 35 is supplied to the path metric storage circuit 36 via the normalization circuit 37, and the output signal of the ACS circuit 35 is supplied to the maximum likelihood path detection circuit 38.

The maximum likelihood path detection circuit 38 detects a path having the minimum path metric value and outputs the contents of the path memory 39 corresponding to the path as decoded data. The path memory 39 is a memory for estimating and storing an information bit sequence.

FIG. 12 shows a logical unit constituting the Viterbi equalizer. In FIG. 12, each weighing represents the following contents.

P (k−1, S _i ): Path metric of the surviving path that has reached state node S _i in time slot t (k−1) P (k−1, S _j ): time slot t (k) -1) path metric b having the state node S _j surviving path which has reached the in (k, S _i → S _n): corresponding to the transition of the in time slot t (k) from the state node S _i to the state node S _n branch metric _{b (k, S j → S} n): a branch metric corresponding to a transition in time slot t (k) from the state node S _j to state nodes S _n

M (k−1, S _i ): Path memory of the surviving path that has reached state node S _i in time slot t (k−1) M (k−1, S _j ): time slot t (k) Path memory <-1>, <+1> of the surviving path that reached state node _Sj in -1) <-1>, <+1>: information symbol estimated to be transmitted in time slot t (k) P (k, _Sn ): time slot t (k) path surviving path which reaches the state node S _n has the metric M (k, S _n): a path memory with the survival path which reaches the state node S _n in time slot t (k)

Here, if the constraint length is k, the number of states is 2
Since only ^k-1 exist, the number of logical units shown in FIG. 12 is basically required by 2 ^k-1 states. Further, as shown in the block configuration of the Viterbi equalizer shown in FIG.
7 is generally used to reduce the size of the path metric storage circuit 36 and to prevent overflow during path metric calculation.

As a specific process of the normalization, a process of first detecting the minimum value of the path metric and then subtracting that value from each path metric amount is performed. The number of surviving paths selected in this way exists by 2 ^{k -1} like the number of states.

In each time slot, an operation of selecting a surviving path and an operation of updating the path metric and the path memory 39 corresponding to the path are repeated. If this operation is performed for a sufficiently long period of time, it is known that before a certain period of time, merging into the same path is performed, and this state is shown in FIG. The length of a path from the latest processing time until the path is merged is called a truncated path length.

The method of updating the path memory in FIG. 12 is determined according to each state. For example, the logical unit of "LLL" is determined as <-1>, the logical unit of "HLL" is determined as <+1>, and so on.

In the maximum likelihood judgment, the path having the smallest path metric value is detected, and the contents of the path memory corresponding to the path are cut off and the path length is cut back by the path length (usually set to about three to four times the constraint length). It is output as the information symbol at the point of time.

FIG. 8 shows the flow of signal processing in the Viterbi equalizer.
This will be described with reference to the flowchart of FIG. First, when the reception signal data _Yk is supplied to the input terminal 30, a synchronization signal pattern is detected (step S1).
A cross-correlation function between the _k synchronization signal pattern and a previously stored synchronization signal pattern is calculated in the transmission path characteristic estimating unit 34 (step S2), and a channel response is estimated (step S3). Next, the branch metric calculation circuit 32 calculates a branch metric (step S).
4) Then, calculation is started for the Nth state (step S5).

Next, the address of state-1 one time slot before is set (step S6), and the path metric stored in the path metric storage circuit 36 of the set address is read (step S7). The metric is added to the branch metric calculated in step S4 by the ACS circuit 35, and the added output is stored in the register P
1 (step S8).

Next, in step S9, the address of state-2 one time slot before is set, and the path metric stored in the path metric storage circuit 36 of the set address is read (step S10). Is added to the branch metric calculated in step S4 by the ACS circuit 35, and the added output is stored in the register P2 (step S11).

Next, the ACS circuit 35 compares and stores the values stored in the registers P1 and P2 (steps S12 and S13), and outputs the selected value (step S14). The metric storage circuit 36 is updated (step S15), and the path memory 39 is updated (step S16).

The above steps S5 to S16
The processing up to repeat only the state number 2 ^k-1 (step S
17). After the above processing is completed, the maximum likelihood path detection circuit 3
8, the path having the minimum path metric value is detected (step S18), and the normalization process is performed by subtracting the minimum value of the path metric from each path metric amount (step S19).

Subsequently, the address of the maximum likelihood path is set by the maximum likelihood path detection circuit 38 (step S20), and the contents of the path memory 39 are output as decoded data (step S20).
21).

In this example, the receiving branch 1
The likelihood of a path metric having a surviving path obtained by the Viterbi equalizers 13a and 13b of a and 1b is supplied to a likelihood comparison circuit 14, and the likelihood comparison circuit 14 determines that the path is the most likely path. The output signal of the Viterbi equalizer of the received branch is selected by the selector circuit 8 and is obtained at the output terminal 10.

According to the example of FIG. 6, the content of the path metric of the reception branch determined to be the maximum likelihood path by comparing the likelihood of the path metric having the surviving path in the plurality of reception branches 1a and 1b. Is used as demodulated data, so that there is an advantage that the best received data can be obtained.

FIG. 14 shows another embodiment of the present invention.
To describe the example of FIG. 14, in FIG.
1 and 15 are denoted by the same reference numerals. Also in FIG. 14, a plurality of, for example, two reception branches 1a
And 1b.

The receiving branches 1a and 1b are, as in the example of FIG. 15, respectively receiving antennas 2a and 2b, high-frequency circuits 3a and 3b, mixing circuits 4a and 4b, and intermediate-frequency circuits 6a and 6b.
6b, detection circuits 7a and 7b, and a local oscillation circuit 5 in common. The output signals of the detection circuits 7a and 7b are supplied to the selector circuit 8, respectively.

In this example, the detection circuits 7a and 7a
b are output to error detection circuits 15a and 15a, respectively.
5b respectively, and the error detection circuits 15a and 15b
At b, the error rate of each detection data is detected. Various known error detection circuits can be used as the error detection circuits 15a and 15b. Since error detection and error correction are generally indispensable in a digital data transmission system, these may be used in common.

The error rates obtained by the error detection circuits 15a and 15b are supplied to an error rate comparison circuit 16, and the output of the error rate comparison circuit 16 selects the receiving branch with the minimum error rate by the selector circuit 8. , Receiving data demodulated by the receiving branch is obtained at the output terminal 10.

In the example of FIG. 14, the receiving branch having the minimum error rate is selected and the received data is used, so that there is an advantage that the best received data can be obtained.

Although the above embodiment has been described with respect to an example in which two receiving branches are provided, it is needless to say that three or more receiving branches may be provided in the same manner as described above, if necessary. In addition, the present invention is not limited to the above-described embodiments, and may adopt various other configurations without departing from the gist of the present invention.

[0089]

According to the present invention, there is an advantage that it is possible to obtain a diversity receiver capable of obtaining optimum reception data even when used in a digital mobile communication system such as a car telephone.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a diversity receiver according to the present invention.

FIG. 2 is a configuration diagram illustrating an example of an automatic equalizer.

FIG. 3 is a flowchart for explaining FIG. 2;

FIG. 4 is a diagram for explaining FIG. 2;

FIG. 5 is a diagram for explaining FIG. 2;

FIG. 6 is a configuration diagram showing another embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating an example of a Viterbi equalizer.

FIG. 8 is a flowchart for explaining FIG. 7;

FIG. 9 is a diagram showing a generalized transmission path equalization model.

FIG. 10 is a diagram showing a embodied transmission equalization model.

FIG. 11 is a diagram showing a trellis expression.

FIG. 12 is a diagram showing a logical unit of a Viterbi equalizer.

FIG. 13 is a diagram illustrating metric calculation and surviving paths.

FIG. 14 is a configuration diagram showing another embodiment of the present invention.

FIG. 15 is a configuration diagram illustrating an example of a conventional diversity receiver.

[Description of Signs] 1a, 1b Receiving branches 7a, 7b Detection circuit 8 Selector circuit 10 Output terminal 11a, 11b Automatic equalizer 12 Equalization error determination circuit 13a, 13b Viterbi equalizer 14 Likelihood comparison circuit

Claims (2)

(57) [Claims] 1. A diversity receiver having a plurality of reception branches for receiving digital data, wherein: a synchronization data detection means for detecting a synchronization signal data portion from a reception signal data sequence in each of the plurality of reception branches; A synchronization pattern table having a synchronized synchronization signal pattern, an impulse response estimating means for calculating a cross-correlation function between the synchronization signal data portion and the synchronization signal pattern, and a transversal filter based on the normalized cross-correlation function Initial value determining means for calculating an initial value of the tap coefficient, error estimating means for detecting an error of the tap coefficient based on the output signal of the transversal filter, the synchronization signal data portion and the synchronization signal pattern, and the error estimation Filter section for setting and updating the tap coefficient according to the output from the means Automatic equalizing means having setting means, and equalizing error determining means for comparing absolute value levels of equalizing errors of the automatic equalizing means of the plurality of receiving branches, and the equalizing error determining means Wherein the reception data demodulated in the reception branch for which the equalization error is determined to be the minimum is used. 2. A diversity receiver having a plurality of receiving branches for receiving digital data, wherein each of the plurality of receiving branches is provided with synchronous data detecting means for detecting a synchronous signal data portion from a received signal data sequence. Transmission path characteristic estimating means for modeling an impulse response between a transmitter and a receiver by using a synchronization signal data portion detected by the synchronization data detection means, and based on a transmission model in the plurality of reception branches. And estimating the transmission data sequence using a Viterbi algorithm and comparing the likelihoods of path metrics having surviving paths in the plurality of reception branches, and determining the path metric of the reception branch determined to be the most likely path. A diversity receiver characterized by using the contents of (1) as demodulated data.