JPH06338524A - Charge transfer device - Google Patents

Abstract

PURPOSE:To provide a highly sensitive charge transfer device, which is operated at low voltage, of simple structure. CONSTITUTION:The title charge transfer device has a high resistant P-type well layer 102 formed on the surface of an N-type semiconductor substrate 101. On the surface of the well layer 102, an N-type charge transfer channel layer 103a, an N-type charge accumulation channel layer 103b, an N-type charge exhaust channel layer 115 and an N-type charge exhaust drain layer 108 are formed continuously. On the surface of the charge accumulation channel layer 103b, the p-type charge sensitive channel layer 111 of a charge detection transistor is formed. The sensitive channel layer 111 is arranged in such a manner that it does not come in contact with either of the transfer channel 103a and the exhaust channel layer 115. The potential of the charge accumulation channel layer 103b in a chargeless state is set higher than the potential of the exhaust drain layer 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge coupled device (hereinafter referred to as C
Abbreviated as CD), and a charge transfer device using the principle of
In particular, it relates to a charge transfer device having an improved charge detection unit.

[0002]

2. Description of the Related Art In recent years, a solid-state image pickup system using a charge transfer device using a CCD has been used as an image pickup system for a video camera, an electronic still camera and the like. This solid-state imaging system includes a photoelectric conversion unit that converts light into an electric signal (signal charge), a charge transfer unit that transfers the signal charge, and a charge detection unit that detects the transferred signal charge and converts the signal charge into a voltage signal for extraction. Consists of. A charge transfer device is provided with the charge transfer section and the charge detection section.

One of the charge detectors provided in the charge transfer device
One of them is a floating diffusion amplifier (hereinafter referred to as FDA) arranged adjacent to the final stage of the charge transfer section.
Is abbreviated). The FDA has a floating diffusion layer (hereinafter abbreviated as FD layer) provided between the output end of the charge transfer unit and the charge discharging drain (reset drain). When the signal charge is transferred from the charge transfer unit to the FD layer, the signal charge is temporarily stored in the FD layer, and the potential of the FD layer changes accordingly. The potential change of the FD layer is transmitted to the gate electrode of the driver transistor of the source follower circuit by the wiring, and the gate potential of the transistor is changed. The source follower circuit amplifies a change in gate potential and outputs a voltage signal, thereby detecting a signal charge. After the charge detection / signal output is completed, the signal charge in the FD layer is discharged from the charge discharging drain by opening the reset gate.

FIG. 14 shows a conventional FDA type charge detector,
In particular, it is a schematic diagram showing an example of a source follower circuit. An FD layer 211 and a reset drain 212 are formed on the surface of the semiconductor substrate 210. The transfer electrode 213, the output gate electrode 214, and the reset gate electrode 215 of the CCD are arranged on the semiconductor substrate 210 via the SiO ₂ film 230. The FD layer 211 is electrically connected to the gate electrode of the transistor 221. The source of the transistor 221 is connected to the drain of the load transistor 222 to form a first-stage source follower circuit. The source of the transistor 221 is connected to the gate electrode of the transistor 223. The source of the transistor 223 is connected to the drain of the load transistor 224 to form a source follower circuit in the output stage. Load MOS transistor 2
Gate electrodes 22 and 224 are both grounded.

In the FDA type charge detection part having such a structure, the parasitic capacitance due to the wiring from the FD layer to the gate electrode of the driver transistor of the source follower circuit becomes large. Therefore, a large change in potential per accumulated charge cannot be obtained, and it is difficult to detect charges with high sensitivity. Moreover, it is difficult to reduce the kTC noise of the reset gate due to the discharge of the signal charge.

FIG. 15 shows the waveform of the voltage V _RS of the reset gate electrode 215 and the waveform of the output voltage V _out . As shown, the waveform of the output voltage V _out always contains noise. As a property of this noise, thermal noise generated from the reset gate electrode 215 is dominant during the period T21 in which the reset gate electrode 215 is in the on state, and the reset gate electrode 215 is off and the signal charge is FD.
In the period T22 in which the layer 211 is injected, the transistor 22
The thermal noise of 1 becomes dominant. Note that the period T2b corresponds to the case where there is no signal charge and the period T2w corresponds to the case where there is signal charge.

As a means for reducing the noise of the FDA, it can be considered to reduce the constant current of the depletion type MOS transistors 222 and 224 for the load of the source follower circuit. However, if the constant current of the source follower is reduced, the mutual conductance of the source follower becomes low, and the FDA cannot respond at high speed. Therefore, it is extremely difficult to reduce the noise of the FDA because it is necessary to secure a fast response. In addition, the load MOS transistor 22
Since the constant current of 2 and 224 cannot be reduced,
There is also an inconvenience that the power consumption of FDA cannot be reduced.

In order to solve the above problems of the FDA type charge detection unit, a charge transfer device having a charge detection unit as disclosed in Japanese Patent Laid-Open No. 64-17469 has been developed. The charge transfer device disclosed in this publication utilizes a buried channel layer of a charge detection MOS transistor arranged adjacent to the final stage of the charge transfer section.

In this structure, since there is no contact region or wiring for connecting the floating diffusion layer and the driver transistor of the source follower circuit, the parasitic capacitance of the charge detecting portion can be reduced. Therefore, the potential change per accumulated charge can be made large, and the charge can be detected with high sensitivity. In addition, since the signal charge accumulated by the floating gate and the control gate can be completely discharged, the kT generated by the reset gate can be completely discharged.
C noise can be eliminated.

On the other hand, in this structure, Matsunaga et al.
"A Highly Sensitive On-Chip Charge Detector for CC
D Area Image Sensor ", IEEE JOURNAL OF SOLID-STATE
CIRCUITS, Vol.26, No.4, April 1991), a power supply voltage (eg, −80) higher than the power supply voltage (eg, 15V) of a commonly used CCD.
V) is required to operate the control gate. Also,
Since the two-layer gate of the floating gate and the control gate is used, the structure of the output detector and its manufacturing process are complicated.

[0011]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a charge transfer device which can obtain a highly sensitive output of signal charges, can be used at a low voltage, and has a simple structure. Another object of the present invention is to provide a charge transfer device including an FDA that improves the S / N (signal / noise) ratio and saves power consumption.

[0012]

A charge transfer device according to a first aspect of the present invention is a semiconductor substrate of a first conductivity type having a surface, and a high resistance second conductivity type formed on the surface of the substrate. A well layer, a first conductivity type charge transfer channel layer formed on the surface of the well layer, and a first conductivity type charge storage channel layer formed on the surface of the substrate so as to be connected to the transfer channel layer. A first conductivity type charge discharging channel layer formed on the surface of the substrate so as to connect to the storage channel layer, and a first conductivity formed on the surface of the substrate so as to connect to the discharging channel layer. -Type charge discharging drain layer, an output gate electrode provided on the connection between the transfer channel layer and the storage channel layer via an insulating film, and a coating insulating film formed on the storage channel layer, The discharge channel A reset gate electrode disposed on the layer via an insulating film, and a second conductivity type charge sensing channel layer of a charge detection transistor formed in the substrate so as to be stacked with the storage channel layer, A second conductivity type source layer and a drain layer of the charge detection transistor, which are formed on the surface of the substrate so as to face each other with the sensing channel layer interposed therebetween, and the storage channel layer is the transfer channel layer. A first surface portion adjacent to the first insulating layer and in contact with the coating insulating film, and a second surface portion adjacent to the discharge channel layer and in contact with the coating insulating film.

A charge transfer device according to a second aspect of the present invention is a semiconductor substrate of a first conductivity type having a surface, a well layer of a second resistance type having a high resistance formed on the surface of the substrate.
A first conductivity type charge transfer channel layer formed on the surface of the well layer, a first conductivity type charge storage channel layer formed on the surface of the substrate so as to be connected to the transfer channel layer, and the storage channel A first conductivity type charge drain channel layer formed on the surface of the substrate to connect to the layer, and a first conductivity type charge drain drain formed on the surface of the substrate to connect to the drain channel layer. Layers and
On the connection between the transfer channel layer and the storage channel layer,
An output gate electrode disposed via an insulating film, a covering insulating film formed on the storage channel layer, a reset gate electrode disposed on the discharge channel layer via an insulating film, and the storage A second conductive type charge sensing channel layer of a charge detection transistor formed in the substrate so as to be stacked with the channel layer, and formed on the surface of the substrate so as to face the second conductivity type charge sensing channel layer of the charge detecting transistor. , A second conductivity type source layer and a drain layer of the charge detection transistor, and the potential of the storage channel layer in the state of no charge is set higher than the potential of the discharge drain layer.

A charge transfer device according to a third aspect of the present invention is a charge-coupled device having a plurality of transfer electrodes arranged on a semiconductor substrate via a gate insulating film, and is adjacent to an output end of the charge-coupled device. A floating diffusion layer for temporarily storing the signal charges transferred by the element, and an amplifying means for amplifying and outputting a voltage signal generated in the floating diffusion layer, the driving transistor and the Amplifying means including a load transistor for controlling the current of the drive transistor, and including a period during which the signal charges transferred from the charge coupled device to the amplifying means flow into the floating diffusion layer. Different voltages are applied to the gates of the load transistors during the period and other periods to control the transconductance of the associated drive transistors.

[0015]

In the charge transfer device according to the first aspect of the present invention, the storage channel layer has a surface adjacent to the transfer channel layer and the discharge channel layer and in contact with the covering insulating film. Accordingly, the coupling capacitance between the sensing channel layer and the output gate electrode and between the sensing channel layer and the reset gate electrode can be reduced. Therefore, it is possible to obtain a large potential change per signal charge, and it is possible to provide a high-sensitivity charge detection unit having a large current-voltage conversion gain due to the signal charge.

In the charge transfer device according to the second aspect of the present invention, the potential of the storage channel layer in the absence of charges is
It is set higher than the potential of the drain layer. That is,
By making it possible to detect the signal charges in the so-called incomplete discharge mode, it is possible to avoid a detection error due to the unevenness of the potential and the pocket of the potential in the storage channel layer. This eliminates the need to provide a control gate and a floating gate on the storage channel layer for assisting the discharge of signal charges. Therefore, the structure and manufacturing process of the device are simplified, and a high voltage power source for the control gate is not needed.

In the charge transfer device according to the third aspect of the present invention, the gate of the load transistor of the source follower circuit is connected to the gate of the load follower circuit during the period including the period in which the signal charges flow into the floating diffusion layer and changes. Apply different voltage,
Controls the transconductance of the drive transistor. That is, the FDA at the moment when the information of the input signal changes.
It is possible to increase the bias current of the source follower circuit only during the period when fast response is required, and reduce the bias current of the source follower circuit during the period when FDA is not required to reduce noise and power consumption. Becomes
This allows FDA without compromising the required high-speed response.
It is possible to reduce the noise and power consumption of the charge transfer device, and to reduce the noise and power consumption of the charge transfer device.

Preferably, the voltage applied to the gate of the load transistor during at least the period from the time when the voltage signal starts changing from the feedthrough level toward the signal level to the time when the voltage signal reaches the signal level sufficiently. To ensure quick response, and to keep the current consumption low by lowering the voltage applied to the gate during periods when importance is not placed on other quick responses.

[0019]

1 (a) is a plan view of a charge transfer device according to an embodiment of the present invention, and FIGS. 1 (b) and 1 (c) are respectively FIG.
It is the IB-IB and IC-IC sectional view taken on the line of (a). Figure 2
FIG. 1A is an enlarged sectional view showing a charge detection unit of the charge transfer device of FIG. 1B.

This charge transfer device is formed on an n-type semiconductor substrate, that is, an n-type substrate 101. The substrate 101 has
Low impurity concentration, that is, high resistance p- type well layer 102
(Impurity concentration 1 × 10 ¹² to 1 × 10 ¹⁷ cm ⁻³ ) is formed. In this embodiment, the substrate 101 is connected to the ground potential.
Is applied with a bias voltage of + 10V, and the well layer 102 is applied with a bias voltage of 0V.

A charge transfer n-type channel layer 103a (impurity concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁹⁾ in which a plurality of p-type layers 123 are formed at intervals on the surface of the high resistance well layer 102.
cm ⁻³ ) is formed along the IB-IB line direction. The charge transfer n-type channel layer 1 is also formed on the surface of the well layer 102.
03a, followed by charge storage n + type channel layer 103b
(Impurity concentration 1 × 10 ¹⁷ to 1 × 10 ²¹ cm ⁻³ ), charge discharging n-type channel layer 115 (impurity concentration 1 × 10 ¹⁴ to 1 ×)
10 ¹⁹ cm ⁻³ ), and the charge discharging n + type drain layer 108 (impurity concentration 1 × 10 ¹⁷ to 1 × 10 ²¹ cm ⁻³ ) is IB-IB.
It is formed in order along the line direction.

A plurality of pairs of first and second charge transfer electrodes 104 and 105 are provided on the charge transfer n-type channel layer 103a and the p-type layer 123 with an insulating film 121 interposed therebetween. An output gate electrode 106 is provided on the charge transfer n-type channel layer 103a adjacent to the charge storage n + -type channel layer 103b with an insulating film 121 interposed therebetween. The reset gate electrode 107 is formed on the charge discharging n-type channel layer 115 with the insulating film 121 interposed therebetween. A discharge wiring 109 is connected to the charge discharging n + drain layer 108.

A p-type channel layer 111 of a charge detection PMOS transistor is formed on the surface of the charge storage n + type channel layer 103b. IC is formed on the surface of the well layer 102.
Source / drain layers 117 and 118 of the charge detection PMOS transistor are formed on both sides of the p-type channel layer 111 along the −IC line direction. The power supply VDD wiring 112 is connected to the source / drain layer 117, and the output Vo wiring 113 is connected to the source / drain layer 118.

As shown in FIG. 2A, the p-type channel layer 1 is formed.
Reference numeral 11 denotes an n-type channel layer 103 for charge transfer and discharge.
It is formed in the charge storage n + type channel layer 103b so as not to come into contact with a and 115. That is, the n + type channel layer 103b has an exposed surface between the p type channel layer 111 and the n type channel layer 103a and between the p type channel layer 111 and the n type channel layer 115, and the insulating film 121
It has a structure that contacts with.

The operation of the charge transfer device having the above structure will be described below. First, by the first and second transfer electrodes 104 and 105 driven in two phases by the control signals φ1 and φ2, the signal charges exceed the potential of the output gate electrode 106 and are transferred to the charge storage n + type channel layer 103b. Accumulated temporarily. This transfer is performed by the reset gate electrode 1
The driving voltage V _RG at the “L” level is applied to the output terminal 07, and the predetermined constant voltage V _OG is applied to the output gate electrode 106.

The signal charge transferred to the channel layer 103b modulates the potential of the channel 111 of the charge detection PMOS transistor shown in FIG. 1 (c). Therefore, the voltage Vo output to the wiring 113 changes according to the amount of signal charges, and the amount of signal charges is detected by measuring this change. After measuring the output voltage change, reset gate electrode 1
The drive voltage V _RG of “H” level is applied to 07, and the signal charges are discharged by the charge discharging drain 10 leaving a constant residual charge described later.
It is discharged to 8.

Next, with reference to FIGS. 2 (b) to 2 (d) showing potential distributions corresponding to respective portions of the sectional view of FIG. 2 (a), the detection of the signal charge in this embodiment will be described. To do. FIG. 2B shows the potential distribution in the state where there is no charge in the charge storage n + type channel layer 103b. In this state, the potential P1o of the charge storage channel layer 103b is set to be higher than the potential Pdr of the charge discharging drain layer 108.
The level relationship of the potential can be set by adjusting the potential of the drain layer 108, adjusting the impurity concentration of the channel layer 103b, or adjusting both. In this embodiment, the charge storage channel layer 103b
The potential is increased by increasing the impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ²¹ cm ⁻³ .

In the state shown in FIG. 2B, the potential distribution inside the channel layer 103b is not constant. In particular,
The potential pocket DP formed on the charge transfer n-type channel layer 103a side may adversely affect the discharge of signal charges.

FIG. 2C shows a potential distribution after the signal charge or other intentionally added charge is once stored in the charge storage n + type channel layer 103b and then discharged. The channel layer 10 is included in the charge storage channel layer 103b.
The potential P1r of 3b is the potential P of the charge discharging drain layer 108.
The same amount as dr, that is, the total charge amount of the number of electrons corresponding to the shaded portion in the figure remains. That is,
The unevenness of the potential in the channel layer 103b in the state where there is no charge is flattened so that the potential pocket DP is filled with the residual charge. Further, according to the present embodiment, since the exposed surface of the channel layer 103b is in contact with the insulating film 121 on both sides of the channel layer 111, the potential P1r of the channel layer 103b is flattened and the potential distribution is within this region. Is uniformly determined by.

FIG. 2D shows the potential distribution at the time of signal charge detection when the signal charges are accumulated in the charge accumulation n + type channel layer 103b after the state shown in FIG. 2C. When the signal charge is transferred to and accumulated in the channel layer 103b when the potential distribution of the charge accumulation channel layer 103b becomes the state of FIG. 2C, the channel layer 103b is formed as shown in FIG. 2D. Has a potential Plt. At this time,
Potential change due to inflow of signal charge ΔP1 = P1r−P1
t is the total amount of inflow signal charges, that is, the total amount of electrons of the number of electrons corresponding to the hatched portion in the figure.

In other words, all the new signal charges flowing into the channel layer 103b appear as a change in the potential of the channel layer 103b, and modulate the potential of the channel 111 of the charge detection PMOS transistor. Therefore, the wiring 113
The voltage Vo output changes to Vo according to the amount of the total inflow signal charge, and the amount of signal charge is detected by measuring this change.

After the signal charge is detected, the reset gate is opened and the signal charge is discharged.
The potential of 3b returns to the state of FIG. In this specification,
In this way, the mode in which the signal charge is discharged at the time of resetting while a constant amount of charge is always left in the channel layer 103b is referred to as an incomplete discharge mode.

According to this embodiment, Japanese Patent Laid-Open No. 64-1746.
Compared with the charge transfer device disclosed in No. 9, the following advantages are obtained. First, since the p-type channel layer 111 is formed so as not to contact the n-type channel layers 103a and 115, the channel layer 111 and the output gate electrode 106, and the channel layer 111 and the reset gate electrode 107 are formed.
The coupling capacity between and can be reduced.
Therefore, a large potential change per signal charge can be obtained, and the current-voltage conversion gain due to the signal charge is large.
That is, it is possible to provide a highly sensitive charge detection unit.

Further, by making it possible to detect the signal charge in the incomplete discharge mode, it is possible to avoid a detection error caused by the unevenness of the potential and the pocket DP of the potential in the charge storage n-type channel layer 103b. That is, it is not necessary to provide the control gate and the floating gate for assisting the discharge of the signal charges on the channel layer 103b. Therefore, the structure and manufacturing process of the device are simplified, and a high voltage power source for the control gate is not needed.

FIG. 3A is an enlarged sectional view showing a charge detecting portion of a charge transfer device according to another embodiment of the present invention.
In this embodiment, the charge storage channel layer 1 in the absence of electric charge is used.
1 except that the potential P2o of 03x is set lower than the potential Pdr of the charge discharging drain layer 108.
The configuration is the same as that of the embodiment shown in FIGS. 2 (a), 2 (b), 2 (c) and 2 (a).

This embodiment will be described with reference to FIGS. 3 (b) to 3 (d) showing potential distributions corresponding to respective portions of the sectional view of FIG. 3 (a). FIG. 3B shows the potential distribution in a state where there is no charge in the charge storage n-type channel layer 103x.
In this state, the potential P2o of the charge storage channel layer 103x is set to be lower than the potential Pdr of the charge discharging drain layer 108. Depending on the level of the potential, the potential of the drain layer 108 may be adjusted or the channel layer 103b may be adjusted.
It can be set by adjusting the impurity concentration of, or by adjusting both of them. In the present embodiment, the impurity concentration of the charge storage channel layer 103x is set to 1 × 10 ¹⁵ -1.
The potential of the channel layer 103x is lowered by making it smaller than x10 ¹⁹ cm ^-3 , which is smaller than that of the channel layer 103b of the previous embodiment.

FIG. 3C shows a potential distribution at the time of detecting the signal charge in which the signal charge is stored in the charge storage n + type channel layer 103x. When the signal charges are transferred to and accumulated in the channel layer 103x, the channel layer 103x receives the potential P2t.
And modulates the potential of the channel 111 of the charge detection PMOS transistor. Therefore, wiring 1
The voltage Vo output to 13 changes in accordance with the amount of signal charge, and the amount of signal charge is detected by measuring this change.

FIG. 3D shows the potential distribution after the reset gate is opened and the signal charges are discharged. Basically, all the charges accumulated in the channel layer 103x are discharged to the charge discharging drain layer 108, and the potential of the channel layer 103x returns to the original P2o. However, unstable residual charges may remain in the potential pocket DP of the channel layer 103x. In this specification, the mode of discharging substantially all the signal charges at the time of resetting is referred to as a complete discharging mode.

According to the embodiment shown in FIG. 3A, the coupling capacitance between the channel layer 111 and the output gate electrode 106 and between the channel layer 111 and the reset gate electrode 107 can be reduced. A highly sensitive charge detection unit can be provided. Further, since the control gate and the floating gate for assisting the discharge of the signal charge are omitted, the structure of the device and the manufacturing process are simplified, and a high voltage power source for the control gate is unnecessary.

FIG. 4A is a plan view of a charge transfer device according to still another embodiment of the present invention, and FIGS. 4B and 4C are IXB-IXB and IXC-IXC of FIG. 4A, respectively. It is a line sectional view. FIG. 5A is an enlarged cross-sectional view of the charge detection unit of the charge transfer device of FIG. 4B.

In this embodiment, the potential P3o of the charge storage channel layer 103x in the absence of electric charges is set lower than the potential Pdr of the charge discharging drain layer 108, and the control gate for assisting the discharging of the signal charges. , Except that the floating gate is provided.
The configuration is the same as that of the embodiment shown in FIGS. 2 (a), 2 (b), 2 (c) and 2 (a).

In this embodiment, the floating gate electrode 120a is provided on the charge storage channel layer 103x and the channel layer 111 via the insulating film 121.
In addition, the insulating film 1 is formed on the floating gate electrode 120a.
A control gate electrode 120b is provided via 14. A high negative voltage can be applied to the control gate electrode 120b, and the charge storage channel layer 103 is provided via the floating gate electrode 120a to which no voltage is applied.
It acts on x.

This embodiment will be described with reference to FIGS. 5 (b) to 5 (d) showing potential distributions corresponding to respective portions of the sectional view of FIG. 5 (a). FIG. 5B shows the potential distribution in the state where no voltage is applied to the control gate electrode 120b and there is no charge in the charge storage n-type channel layer 103x. In this state, the charge storage channel layer 103x
Potential P3o of the charge drain drain layer 108 potential Pdr
It is set to be lower. In this embodiment,
The impurity concentration of the charge storage channel layer 103x is set to 1 × 10 ¹⁵
The electric potential is lowered by setting it to ˜1 × 10 ¹⁹ cm ⁻³ .

In the state shown in FIG. 5B, the potential distribution in the channel layer 103x is not constant. In particular,
The potential pocket DP formed on the charge transfer n-type channel layer 103a side may adversely affect the discharge of signal charges.

FIG. 5C shows the control gate electrode 1
20b shows a potential distribution when a negative voltage is applied to 20b.
The potential of the channel layer 103b changes to the potential P3r due to the influence of the applied voltage. At this time, the potential pocket DP disappears, and the potential is continuously connected from the charge transfer n-type channel layer 103a side to the charge storage n-type channel layer 103x. The application of the negative voltage to the control gate electrode 120b is for preventing the unstable residual charge from remaining in the potential pocket DP at the time of discharging the signal charge, that is, at the time of resetting. Therefore, the same voltage may be applied only at the time of reset, but in this embodiment, a negative voltage is always applied to the control gate electrode 120b in order to simplify the operation.

FIG. 5D shows the control gate electrode 1
20B shows a potential distribution at the time of signal charge detection in which a negative voltage is applied to 20b and signal charges are accumulated in the charge accumulation n-type channel layer 103x. When the signal charges are transferred to and accumulated in the channel layer 103x, the channel layer 103x receives the potential P.
As a result, the potential of the channel 111 of the charge detection PMOS transistor is modulated. Therefore, the voltage output to the wiring 113 changes Vo according to the amount of the total inflow signal charge, and the amount of the signal charge is detected by measuring this change.

After the signal charge is detected, the reset gate is opened and the signal charge is discharged.
The potential of 3x returns to the state of FIG. That is, this embodiment operates in full drain mode.

According to the embodiment shown in FIG. 5A, the coupling capacitance between the channel layer 111 and the output gate electrode 106 and between the channel layer 111 and the reset gate electrode 107 can be reduced. A highly sensitive charge detection unit can be provided. Further, the control gate and the floating gate can prevent unstable residual charges from remaining in the channel layer 103x.

FIG. 6A is an enlarged sectional view showing a charge detecting portion of a charge transfer device according to still another embodiment of the present invention. In this embodiment, the p-type channel layer 131 is formed so as to extend completely from the n-type channel layer 103 a to the n-type channel layer 115, as shown in FIG.
The configuration is the same as the embodiment shown in FIGS. 2 (b), 2 (c) and 2 (a).

Detection of signal charges in this embodiment will be described with reference to FIGS. 6B to 6D showing potential distributions corresponding to respective portions of the sectional view of FIG. 6A. Figure 6 (b)
Indicates a potential distribution in a state where there is no charge in the charge storage n + type channel layer 103b. In this state, the potential P4o of the charge storage channel layer 103b changes to the charge drainage layer 108.
Is set to be higher than the potential Pdr. Whether the potential of the drain layer 108 is adjusted,
It can be set by adjusting the impurity concentration of the channel layer 103b or by adjusting both of them. In this embodiment, the potential is increased by increasing the impurity concentration of the charge storage channel layer 103b to 1 × 10 ¹⁷ to 1 × 10 ²¹ cm ⁻³ .

In the state shown in FIG. 6B, the potential distribution inside the channel layer 103b is not constant. In particular,
The potential pocket DP formed on the charge transfer n-type channel layer 103a side may adversely affect the discharge of signal charges.

FIG. 6C shows a potential distribution after the signal charge or other intentionally added charge is once stored in the charge storage n + type channel layer 103b and then discharged. The channel layer 10 is included in the charge storage channel layer 103b.
The potential P4r of 3b is the potential P of the charge drain layer 108.
The same amount as dr, that is, the total charge amount of the number of electrons corresponding to the shaded portion in the figure remains. That is,
The unevenness of the potential in the channel layer 103b in the absence of electric charge is evened so that the electric potential pocket DP is filled with the residual electric charge.

FIG. 6D shows a potential distribution at the time of signal charge detection in which signal charges are accumulated in the charge accumulation n + type channel layer 103b after the state shown in FIG. 6C. When the signal charge is transferred to and accumulated in the channel layer 103b when the potential distribution of the charge accumulation channel layer 103b is in the state of FIG. 6C, the channel layer 103b is formed as shown in FIG. 6D. Has a potential P4t. At this time,
Potential change due to inflow of signal charge ΔP4 = P4r−P4
t is the total amount of inflow signal charges, that is, the total amount of electrons of the number of electrons corresponding to the hatched portion in the figure.

In other words, all new inflow signal charges into the channel layer 103b appear as changes in the potential of the channel layer 103b, and modulate the potential of the channel 131 of the charge detection PMOS transistor. Therefore, the wiring 113
The voltage Vo output changes to Vo according to the amount of the total inflow signal charge, and the amount of signal charge is detected by measuring this change.

After the signal charge is detected, the reset gate is opened and the signal charge is discharged.
The potential of 3b returns to the state of FIG. 6 (c). That is, this embodiment operates in the incomplete ejection mode.

According to the embodiment shown in FIG. 6A, the control gate and the floating gate for assisting the discharge of the signal charge are omitted, and the signal charge can be detected by the incomplete discharge mode. Therefore, the structure and manufacturing process of the device are simplified, and a high voltage power source for the control gate is not needed.

FIG. 7A is an enlarged sectional view showing a charge detecting portion of a charge transfer device according to still another embodiment of the present invention. This embodiment has the same configuration as the embodiment shown in FIG. 6A except that a control gate and a floating gate for assisting the discharge of signal charges are provided.

The control gate and the floating gate are formed in the same arrangement as that shown in FIGS. 4A and 4C. That is, the floating gate electrode 120a is provided on the charge storage channel layer 103b and the channel layer 131 with the insulating film 121 interposed therebetween. Further, the control gate electrode 120b is provided on the floating gate electrode 120a with the insulating film 114 interposed therebetween. A high negative voltage can be applied to the control gate electrode 120b, and no voltage is applied to the floating gate electrode 12b.
It acts on the charge storage channel layer 103b via 0a.

This embodiment will be described with reference to FIGS. 7 (b) to 7 (d) showing potential distributions corresponding to respective portions of the sectional view of FIG. 7 (a). FIG. 7B shows a potential distribution in the state where no voltage is applied to the control gate electrode 120b and no charge is present in the charge storage n-type channel layer 103b. In this state, the potential P5o of the charge storage channel layer 103b is set to be higher than the potential Pdr of the charge discharging drain layer 108. In the present embodiment, the impurity concentration of the charge storage channel layer 103b is set to 1 × 10 ¹⁷ to
The electric potential is raised by increasing it to 1 × 10 ²¹ cm ⁻³ .

FIG. 7C shows the control gate electrode 1
20b shows a potential distribution after a negative voltage is applied to 20b and the signal charge or other intentionally added charge is once stored in the charge storage n + type channel layer 103b and then discharged. In the charge storage channel layer 103b, an amount by which the potential P5r of the channel layer 103b is made equal to the potential Pdr of the charge discharging drain layer 108, that is, the total charge amount of the number of electrons corresponding to the shaded portion in the drawing remains. .

FIG. 7D shows the potential distribution at the time of signal charge detection when the signal charges are accumulated in the charge accumulation n + type channel layer 103b after the state shown in FIG. 7C. When the signal charge is transferred to and accumulated in the channel layer 103b, the channel layer 103b comes to have the potential P5t. The charge detection PM changes due to the change in the potential of the channel layer 103b.
The potential of the channel 131 of the OS transistor is modulated.
Therefore, the voltage output to the wiring 113 changes Vo according to the amount of signal charges, and the amount of signal charges is detected by measuring this change.

After the signal charge is detected, the reset gate is opened and the signal charge is discharged.
The potential of 3b returns to the state of FIG. 7 (c). That is, this embodiment operates in the incomplete ejection mode.

According to the embodiment shown in FIG. 7 (a), since the signal charge can be detected in the incomplete discharge mode, the control gate can be operated at a low voltage, and a high voltage power supply is unnecessary.

FIG. 8 is an enlarged sectional view showing a charge detecting portion of a charge transfer device according to still another embodiment of the present invention. This example is different from FIG. 1 except that the p-type channel layer 141 of the charge detection PMOS transistor is formed at a different position.
The configuration is the same as that of the embodiment shown in FIGS. 2 (a), 2 (b), 2 (c) and 2 (a).

In this embodiment, the charge storage n + type channel layer 103b formed between the charge transfer n type channel layer 103a and the charge discharging n type channel layer 115 is
The entire upper surface contacts the insulating film 121. A high resistance p- type well layer 10 is formed under contact with the n + type channel layer 103b.
2 (impurity concentration 1 × 10 ¹² to 1 × 10 ¹⁷ cm ⁻³ ) within the charge sensing p-type channel layer 141 (impurity concentration 1 × 10 ¹⁴ to
1 × 10 ¹⁸ cm ⁻³ ) is formed. p-type channel layer 14
1 is an n-type channel layer 103a for charge transfer and discharge
It is arranged so as not to contact 115. The p-type channel layer 141 can be formed using a high acceleration ion implantation device.

Charge storage channel layer 10 in the absence of charge
The potential of 3b is set higher than the potential of the charge discharging drain layer 108, as in the embodiment shown in FIG. That is, this embodiment is operated in the incomplete discharge mode, and the mode at that time is substantially the same as the mode shown in FIGS. 2 (b) to 2 (d).

According to the embodiment shown in FIG. 8, the channel layer 1
11 and the output gate electrode 106, and the channel layer 1
The coupling capacitance between the gate electrode 11 and the reset gate electrode 107 can be reduced, and a highly sensitive charge detection unit can be provided. Further, since the control gate and the floating gate for assisting the discharge of the signal charge can be omitted, the structure of the device and the manufacturing process are simplified, and
The high voltage power supply for the control gate is also unnecessary.

FIG. 9 is an enlarged sectional view showing a charge detecting portion of a charge transfer device according to still another embodiment of the present invention. In this embodiment, the p-type well layer is divided, and the p-type channel layer 15 of the PMOS transistor for charge detection is divided.
1 (a), except that the formation position of 1 is different.
The configuration is the same as the embodiment shown in FIGS. 2 (b), 2 (c) and 2 (a).

In this embodiment, the high resistance p--type well layer (impurity concentration 1 × 10 ¹² to 1 × 10 ¹⁷ cm ^-3 ) is disposed under the charge transfer n-type channel layer 103a. 1
It is divided into a portion 102a and a second portion 102b disposed below the charge discharging n + type drain layer. Between the well layer portions 102a and 102b, the charge sensing p-type channel layer 151 (impurity concentration 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ^{− 3} )
Is formed. The p-type channel layer 151 is in contact with the charge transfer n-type channel layer 103a and the charge discharging n-type channel layer 115 on both sides. Charge storage n + type channel layer 103
b is formed on the surface of the charge sensing p-type channel layer 151,
The entire upper surface thereof contacts the insulating film 121.

Charge storage channel layer 10 in the absence of charge
The potential of 3b is set to be higher than the potential of the charge discharging drain layer 108 as in the embodiment shown in FIG. That is, this embodiment is operated in the incomplete discharge mode, and the mode at that time is substantially the same as the mode shown in FIGS. 6 (b) to 6 (d).

The embodiment shown in FIG. 9 has the advantage that the p-type channel layer 151 is easier to form than the p-type channel layer 141 of the embodiment shown in FIG. Further, since the control gate and the floating gate for assisting the discharge of the signal charges can be omitted, the structure of the device and the manufacturing process are simplified, and a high voltage power source for the control gate is not required.

FIG. 10 is a diagram showing a charge detector of a charge transfer device according to still another embodiment of the present invention. This embodiment is different from the embodiments shown in FIGS. 1 to 9 and relates to an improvement of the FDA type charge detection unit.

The FD layer 21 is formed on the surface of the semiconductor substrate 210.
1 and reset drain 212 are formed. The transfer electrode 213, the output gate electrode 214, and the reset gate electrode 215 of the CCD are arranged on the semiconductor substrate 210 via the SiO ₂ film 230. The FD layer 211 is electrically connected to the gate electrode of the transistor 221. The source of the transistor 221 is connected to the drain of the depletion type load MOS transistor 222 to form a first-stage source follower circuit. The source of the transistor 221 is connected to the gate electrode of the output stage driving transistor 223. The source of the transistor 223 is connected to the drain of the depletion type load MOS transistor 224 to form a source follower circuit of the output stage. Gate electrodes 22 of load MOS transistors 222 and 224
5, 226 have independent control signals V _cont and V _G , respectively.
Is configured to be able to give.

Next, the operating point of the source follower circuit of the output stage will be described. Here, it is assumed that the voltage of the control signal V _G is constant (for example, 0 V or 1 to 2 V), and the power supply voltage V _DD is a voltage such as 15 V.

FIG. 11 is a diagram showing operating points of the source follower circuit in the output stage. Here, the curve 231 shows the drain current characteristic with respect to the output voltage of the output stage drive transistor 223 shown in FIG. Also, the curves 234a,
234b shows the drain current characteristics with respect to the output voltage of the output stage load transistor 224 shown in FIG. The curve 234a indicates the gate electrode 2 of the transistor 224.
The voltage of the control signal V _cont applied to 26 is increased (for example,
Curve 234b corresponds to the case where the voltage of the control signal V _cont is low (for example, 2 to 3 V).
As understood from the figure, according to the present embodiment, a low voltage is applied to the gate electrode 226 of the transistor 224 to operate the source follower circuit at the operating point (V ₁ , I ₁ ) 232a, or the transistor 224 is operated. Gate electrode 2
It is possible to apply a high voltage to 26 and operate the source follower circuit at the operating point (V ₂ , I ₂ ) 232b. That is, the gate electrode 22 of the load transistor 224
By controlling the voltage V _cont applied to 6, the bias current of the source follower circuit can be controlled.

At this time, the change amount V _out of the output signal that changes with respect to the input signal V _in of the source follower circuit is: V _out = Adc [1-exp (-Gmt / C)] V _in ... It can be represented by (1). V _out , V _in , Adc, Gm,
C and t are output voltage, input voltage, DC amplification factor,
Indicates transconductance, load capacity, and time. It can be seen from the above equation that the response speed of the source follower circuit increases as Gm increases.

Then, Gm can be expressed by Gm = (2 · W / L · μ · Cox · Id) ^1/2 (2). W, L, μ, Cox, and Id represent channel width, channel length, mobility, capacitance per area, and bias current, respectively.

Therefore, it is understood that the larger the bias current is, the larger Gm becomes, and thus the response speed of the circuit is increased. Therefore, during the period when the information of the input signal changes, the gate electrode 226 of the load MOS transistor 224 is changed.
By increasing the voltage V _cont applied to the circuit and increasing Gm, a large amount of current is flowed to improve the fast response of the FDA, and further, the voltage V _cont is lowered during the period when the information of the input signal does not change. The current consumption can be greatly reduced by passing a small amount of current.

The above advantages will be described in more detail below with reference to the voltage waveforms shown in FIG. In the same figure, the waveform of the voltage V _RS of the reset gate electrode 215, the waveform of the voltage V _cont of the gate electrode 226 of the load transistor, and the waveform of the output voltage V _out are sequentially shown from the top.

Here, T11 is a period during which the reset gate is turned on, T12 is a period after the reset gate is turned off, and shortly before the injection of the signal charge into the FD layer 211 is started. The period during which Gm of the load transistor gate electrode 226 should be increased, that is, the output V _out
Is a period from just before the point where the charge injection starts to change from the feedthrough level L1 toward the signal level L2 to the time when the output V _out reaches the signal level sufficiently, and T14 is the end of T13. To FD layer 21
1 shows the period until the reset of the signal charge existing in 1 starts. The time T1b corresponds to the case where the signal charge is small, and the time T1w corresponds to the case where the signal charge is large. As shown in the figure, in the period of T13, the voltage V _cont is increased to increase the Gm of the load transistor gate electrode 226, so that the FDA responds to a change in the signal at a high speed, and other than T13. In the period of, the voltage V
_Since the Gm of the load transistor gate electrode 226 is reduced by lowering _cont , the operating current is suppressed to a low level, and thus noise is suppressed to a very low level as compared with the conventional case.

As described above, according to this embodiment, it is possible to achieve power saving and noise reduction in the FDA of the charge transfer device without impairing the required high-speed response. This F
If the charge transfer device having the DA is applied to the solid-state image pickup device, it is possible to achieve a great improvement in performance.

Here, in the periods other than T13, F
DA has a low frequency characteristic, and if the output signal is sampled in the period T14, a signal with high aliasing noise of high frequency noise components can be obtained. Further, the signal of the period T12 may be sampled to obtain the difference from the signal of the period T14, or the low frequency noise component can be eliminated by passing the signal of the time T14 through a high pass filter. Furthermore, if the output signal is sampled at the time when a small amount of current is flowing, the mutual conductance of the charge detection MOS transistor is reduced and the band is narrowed, so that high frequency noise can be largely eliminated, so that the FDA S / The N ratio is improved.

Therefore, by controlling the gate voltage of the load transistor of the FDA, the bias current and noise of the FDA can be controlled and the output sensitivity of the FDA can be improved. It is possible to achieve a significant improvement in.

In the above description, the voltage V _G given to the gate electrode 225 of the load transistor 222 of the first stage source follower circuit is kept constant, but this voltage V _G
May also be applied to the gate electrode 225 as a pulse voltage.
Hereinafter, advantages of controlling the voltage V _G applied to the gate electrode 225 will be described. First, the equivalent input noise charge generated from the thermal noise of the transistor 221 is Q = (4k · T / Gm · α) ^1/2 · Ct / [1+ (2 · f · Cgs / Gm) ² ] ^{1 / 2} It can be expressed by (3). Q, k, T, α, Ct, f, Cgs
Are equivalent input noise charge, Boltzmann constant, temperature,
The experimental constants, the capacitance of the FD layer 211, the noise frequency, and the capacitance between the gate and the source of the transistor 221 are shown.

FIG. 13 shows the equivalent input 2 obtained from the above equation.
It is the figure which represented the squared noise charge versus frequency notionally. Here, Gm2> Gm1, and the noise 240a is Gm = Gm1.
And noise 240b represents noise when Gm = Gm2. The noise A when the noise 240a is DC is A = 4α · k · T · Ct ² / Gm1 (4), and the noise B when the noise 240b is DC is B = 4α · k · T · Ct ² / Gm2 (5). Further, fa is a signal band determined by subsequent signal processing.

In this case, since the total noise output is the integral of the noise within the band, the total noise At of the noise 240a is At = (A · fa) ^1/2 (6), and the total noise At of the noise 240b is The total noise Bt is Bt = (B · fa) ^1/2 (7)

Therefore, since At> Bt, the larger the Gm of the charge detection transistor 221, the smaller the noise. That is, the gate electrode 225 of the transistor 222
In addition, the effect of further increasing the noise reduction effect can be obtained by applying a higher voltage. Therefore, for example, when the voltage V _G is increased and Gm of the charge detection transistor 221 is increased only before and after the sampling of the output signal, the noise included in the output signal at the time of sampling is hardly increased with almost no increase in power consumption. There is an advantage that it can be reduced.

In the embodiment shown in FIG. 10, the FDA has a two-stage source follower circuit.
The DA may be configured using a source follower circuit having three or more stages.

16 and 17 are block diagrams showing the configuration of a camera using the charge transfer device according to the embodiment of the present invention described with reference to FIGS. FIG. 16 shows a single plate camera 10 having one solid-state imaging system 12 incorporating a charge transfer device according to an embodiment of the present invention. The solid-state imaging system 12 has a light receiving unit 14 having a large number of pixels. Incident light from the subject 5 is focused on the light receiving unit 14 of the imaging system 12 through the lens 16. The imaging system 12 converts the signal charge generated in response to the collected light into an electrical output signal in the above-described manner. The output signal from the imaging system 12 is transmitted to the monitor 22 via the signal processing circuit 18 and imaged.

FIG. 17 shows a three-plate camera 30 having three solid-state image pickup systems incorporating a charge transfer device according to an embodiment of the present invention. Each of the three solid-state imaging systems includes a red (R), green (G), and blue (B) color filter in the light receiving portion, and forms a color separation optical system 32. Incident light from the subject 5 is condensed through the lens 36 on the light receiving part of each imaging system in the color separation optical system 32. Each imaging system converts the signal charge generated in response to the collected light into an electrical output signal in the manner described above. The output signal from each imaging system is
The signals are transmitted to the monitor 42 through the signal processing circuits 38 a, 38 b, 38 c dedicated to each color and the color coder 40, and are imaged.

In the embodiment shown in FIG. 17, the high-sensitivity solid-state imaging system according to the present invention is used for blue (B) color, which has low sensitivity, and normal solid-state images are used for the remaining two colors (R, G). An imaging system can be used to increase blue sensitivity. As described above, the present invention can be appropriately used according to the application without using the solid-state imaging system according to the present invention for all three colors (R, G, B).

The high sensitivity of the solid-state image pickup system according to the present invention makes it particularly suitable for a surveillance camera which needs to be used at night when the signal amount is small. Further, when the solid-state imaging system according to the present invention is used for a home video camera, it is possible to provide a high-sensitivity camera with little deterioration in resolution.

[0093]

According to the charge transfer device of the first aspect,
It is possible to reduce the coupling capacitance between the sensing channel layer and the output gate electrode and between the sensing channel layer and the reset gate electrode. Therefore, it is possible to obtain a large potential change per signal charge, and it is possible to provide a high-sensitivity charge detection unit having a large current-voltage conversion gain due to the signal charge.

According to the charge transfer device of the second aspect, it is possible to avoid the detection error caused by the unevenness of the potential and the pocket of the potential in the storage channel layer. This eliminates the need to provide a control gate and a floating gate on the storage channel layer for assisting the discharge of signal charges. Therefore, the structure and manufacturing process of the device are simplified, and a high voltage power source for the control gate is not needed.

According to the charge transfer device of the third aspect, the bias current of the source follower circuit is increased only during the period when the FDA is required to respond quickly such as the moment when the information of the input signal changes. In a period in which is not required, it is possible to reduce the bias current of the source follower circuit to reduce noise and power consumption. As a result, it is possible to reduce the noise and power consumption of the FDA without impairing the required high-speed response, and to reduce the noise and power consumption of the charge transfer device.

[Brief description of drawings]

1A is a plan view showing a charge transfer device according to an embodiment of the present invention, and FIGS. 1B and 1C are IBs of FIG. 1A.
-IB line and IC-IC line sectional view.

2A is an enlarged cross-sectional view of the charge detection unit illustrated in FIG. 1B, and FIGS. 2B to 2D are diagrams illustrating potential distributions corresponding to respective portions of the cross-sectional view illustrated in FIG.

FIG. 3A is an enlarged cross-sectional view of a charge detection unit of a charge transfer device according to another embodiment of the present invention, and FIGS.
FIG. 4A is a diagram showing a potential distribution corresponding to each part of the sectional view shown in FIG.

4A is a plan view showing a charge transfer device according to still another embodiment of the present invention, and FIGS. 4B and 4C are cross-sectional views taken along line IXB-IXB and IXC-IXC of FIG. 4A, respectively. .

5A is an enlarged cross-sectional view showing a charge detection unit of a charge transfer device according to still another embodiment of the present invention, and FIG.
(D) is a figure which shows the electric potential distribution corresponding to each part of the sectional view of (a) illustration.

FIG. 6A is an enlarged sectional view showing a charge detection unit of a charge transfer device according to still another embodiment of the present invention;
(D) is a figure which shows the electric potential distribution corresponding to each part of the sectional view of (a) illustration.

FIG. 7A is an enlarged sectional view showing a charge detection unit of a charge transfer device according to still another embodiment of the present invention;
(D) is a figure which shows the electric potential distribution corresponding to each part of the sectional view of (a) illustration.

FIG. 8 is an enlarged cross-sectional view showing a charge detection unit of a charge transfer device according to yet another embodiment of the present invention.

FIG. 9 is an enlarged cross-sectional view showing a charge detection unit of a charge transfer device according to yet another embodiment of the present invention.

FIG. 10 is a diagram showing an FDA type charge detection unit of a charge transfer device according to still another embodiment of the present invention.

11 is a graph showing drain current-output voltage characteristics of the source follower circuit shown in FIG.

12 is a diagram showing output waveforms of the FDA of the embodiment shown in FIG.

13 is a conceptual diagram showing a noise amount obtained by further improving the FDA of the embodiment shown in FIG.

FIG. 14 is a diagram showing an FDA type charge detection unit of a conventional charge transfer device.

15 is a diagram showing an output waveform of the FDA of the apparatus shown in FIG. 14 and the like.

FIG. 16 is a block diagram showing a configuration of a camera using the charge transfer device according to the embodiment of the present invention.

FIG. 17 is a block diagram showing the configuration of another camera using the charge transfer device according to the embodiment of the present invention.

[Explanation of symbols]

101 ... N-type (first conductivity type) semiconductor substrate, 102 ... Low-concentration p-type (second conductivity type) well layer, 103a ... Charge transfer n-type channel layer, 103b, 103x ... Charge storage n-type channel layer, 104 ... first charge transfer electrode, 105 ... second charge transfer electrode, 106 ... output gate electrode, 107 ... reset gate electrode, 108 ... charge discharging drain layer, 109 ... charge discharging wiring, 111,131,141,151 ... Charge sensing p-type channel layer, 112 ... Power supply wiring, 113 ... Output signal wiring, 114 ... Insulating film, 115 ... Charge discharging n-type channel layer, 117, 118 ... Source / drain layer, 120a ... Floating gate electrode, 120b ... Control gate electrode, 121 ... Insulating film, 123 ... P-type layer, 210 ... Semiconductor substrate, 211 ... FD layer (floating diffusion layer), 2 12 ... Reset drain layer, 213 ... Transfer electrode, 214 ... Output gate electrode, 215 ... Reset gate electrode, 221 ... Charge detection MOS transistor, 222 ... First stage load MOS transistor, 223 ... Output stage drive MOS transistor, 224 ... Output stage load MOS transistor, 225 ... Gate electrode, 226 ... Gate electrode, 230 ... SiO ₂ film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Endo 1 Komukai Toshiba Town, Kawasaki City, Kanagawa Prefecture

Claims (3)

[Claims] 1. A first conductive type semiconductor substrate having a surface, a high resistance second conductive type well layer formed on the surface of the substrate, and a first conductive type charge formed on the surface of the well layer. A transfer channel layer, a first conductivity type charge storage channel layer formed on the surface of the substrate so as to be connected to the transfer channel layer, and formed on the surface of the substrate so as to be connected to the storage channel layer. A first conductivity type charge discharging channel layer, a first conductivity type charge discharging drain layer formed on the surface of the substrate so as to be connected to the discharge channel layer, and a connection between the transfer channel layer and the storage channel layer. On the department
An output gate electrode disposed via an insulating film, a covering insulating film formed on the storage channel layer, a reset gate electrode disposed on the discharge channel layer via an insulating film, the storage A second conductivity type charge sensing channel layer of a charge detection transistor formed in the substrate so as to be stacked with the channel layer, and formed on the surface of the substrate so as to face the second conductivity type charge sensing channel layer. A second of the charge detection transistor
A conductive source layer and a drain layer, wherein the storage channel layer is adjacent to the transfer channel layer and is in contact with the coating insulating film, and the coating is adjacent to the discharge channel layer. A second surface portion in contact with the insulating film; 2. A first conductive type semiconductor substrate having a surface, a high resistance second conductive type well layer formed on the surface of the substrate, and a first conductive type charge formed on the surface of the well layer. A transfer channel layer, a first conductivity type charge storage channel layer formed on the surface of the substrate so as to be connected to the transfer channel layer, and formed on the surface of the substrate so as to be connected to the storage channel layer. A first conductivity type charge discharging channel layer, a first conductivity type charge discharging drain layer formed on the surface of the substrate so as to be connected to the discharge channel layer, and a connection between the transfer channel layer and the storage channel layer. On the department
An output gate electrode disposed via an insulating film, a covering insulating film formed on the storage channel layer, a reset gate electrode disposed on the discharge channel layer via an insulating film, the storage A second conductivity type charge sensing channel layer of a charge detection transistor formed in the substrate so as to be stacked with the channel layer, and formed on the surface of the substrate so as to face the second conductivity type charge sensing channel layer. A second of the charge detection transistor
A charge transfer device comprising: a conductive type source layer and a drain layer, wherein a potential of the storage channel layer in a state where there is no charge is set higher than a potential of the discharge drain layer. 3. A charge-coupled device having a plurality of transfer electrodes arranged on a semiconductor substrate with a gate insulating film interposed therebetween, and a signal charge transferred adjacent to the output end of the charge-coupled device by the device. A floating diffusion layer for temporarily accumulating, and an amplifying means for amplifying and outputting a voltage signal generated in the floating diffusion layer, the driving transistor and a load transistor for controlling the current of the driving transistor. The load transistor is provided with a period including a period during which the signal charge transferred from the charge coupled device applied to the amplifying unit flows into the floating diffusion layer and a period other than the period including the period. A charge transfer device that applies different voltages to the gates of the transistors to control the transconductance of the associated drive transistors.