JPH06334990A - Encoding circuit and decoding circuit for digital video signal - Google Patents

Abstract

PURPOSE:To provide digital video signal encoding and decoding circuits of high practicality which use the IC used in a video signal recording and reproducing device like a consumer digital VTR to perform the video signal recording and reproducing processing of high picture quality and reduce the cost of a video apparatus of high picture quality. CONSTITUTION:An analog video signal is converted to a digital signal by an A/D converter 10 and is supplied to an orthogonal transformation circuit 52 and is subjected to orthogonal transformation based on DCT and is zigzag scanned and is outputted. This coefficient data is separated into an even data string and an odd data string by a separating circuit 54. Thus, the information volume is separated into halves approximately. Separated data strings are subjected to nonlinear quantization and two-dimensional Huffman encoding by variable length code encoding circuits 16A and 16B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital VTR, a disk recorder or the like, which compresses a video signal by band compression by an image compression technique by high efficiency coding using orthogonal transformation and records or reproduces it on a medium. The present invention relates to a digital video signal encoding circuit and a decoding circuit that perform decompression and decoding.

[0002]

2. Description of the Related Art A signal processing circuit, such as a digital VTR, for compressing a video signal by high efficiency coding using orthogonal transformation.
Has a configuration as shown in FIG. 5, for example. In the figure, first of all, from the recording side, the analog video signal is supplied to the A / D converter 10 and converted into a digital signal, and then supplied to the high efficiency encoding circuit 12. The high efficiency coding circuit 12 includes an orthogonal transformation circuit 14 and a variable length coding circuit 16. The orthogonal transform circuit 14 performs an orthogonal transform process such as two-dimensional DCT (discrete cosine transform) on the input digital video signal. According to the so-called JPEG standard, 2 horizontal pixels and 8 vertical pixels are used.
Often a dimensional DCT is used.

Next, so-called zigzag scanning is performed on the data thus orthogonally transformed. Figure 6
Shows the situation, and 8 × 8 = 6 after orthogonal transformation.
The four pieces of data are two-dimensionally zigzag scanned in the order indicated by the numbers in FIG. This zigzag scanning is a process of changing the order of data so that the values of the DCT transform coefficient data are "0" as continuous as possible.

The DCT coefficient data after the zigzag scan is supplied to the variable length coding circuit 16. The variable length coding circuit 16 first performs a quantization process for approximating the input data at discrete levels. For example, quantization is performed by dividing the data by a coefficient that differs for each DCT coefficient position and converting the division result to the nearest integer. At this time, so-called rounding processing is often performed. The code amount of the result of the next encoding changes depending on the coefficient used for the division.

The variable-length coding circuit 16 further performs a coding process on the quantized coefficient data to assign a code to each quantization level. As the encoding method, two-dimensional Huffman encoding is often used in which zero-run length and the value of coefficient data after quantization are combined to perform two-dimensional code assignment.

Next, for the encoded signal,
Coding for error correction by the error correction coding circuit 18 (for example, Reed-Solomon coding) and coding for recording by the recording coding circuit 20 (for example, I-NRZI) are performed. Then, the final encoded data is recorded on the video tape 26 by the recording head 24 after being amplified by the amplifier 22.

Next, the reproducing side will be described. The data reproduced from the video tape 26 by the reproducing head 28 is amplified by the amplifier 30 and then supplied to the data detecting circuit 32, where the sync signal and the control signal are excluded. Detection (extraction) of data related to the image is performed. Then, after error detection and correction by the error correction circuit 34 and decoding by the variable-length code decoding circuit 36 are performed in order, the orthogonal inverse transform circuit 38 performs orthogonal inverse transform processing that is the inverse of DCT and performs decoding. Be converted. Further, the decoded digital video signal is converted into an analog video signal by the D / A converter 40. In this way, the data is decoded and the video signal is reproduced.

[0008]

By the way, in general, the number of manufactured digital VTRs for consumer use is much larger than that for commercial use. Therefore, the development cost of the ICs constituting the set and the unit manufacturing cost of the IC are It will be cheaper if you convert it per unit. On the other hand, since the number of manufactured high-quality digital VTRs for business use is usually very small, the IC development cost per set and the IC manufacturing unit price tend to be inevitably high. Therefore, consumer digital VT
If the R and the high image quality VTR can share the signal processing IC, it is expected that the price of the high image quality digital VTR can be kept low.

Next, in the consumer digital VTR, the cassette size (tape length) must be determined in consideration of not only the image quality but also the length of the recording time and the ease of handling. Generally, the code compression rate is 1/4 to 1 / number 1
There is a tendency to select a small cassette size by increasing the size to about zero. On the other hand, in the high image quality digital VTR, since the image quality is emphasized rather, the code compression rate is selected to be a relatively small value of 1/2 to 1/4.

Here, the small code compression rate means that the amount of data recorded / reproduced on the video tape is large. In other words, the high image quality digital VTR is used.
That is, the signal processing circuit of (1) has a large amount of data that must be processed per unit time. Therefore, high speed operation is required.

On the other hand, there is generally a trade-off relationship between the high-speed operation of the IC internal circuit and the circuit size, and the circuit size often becomes large when the structure capable of high-speed operation is used. But,
The signal processing circuit inside the IC must be made as small as possible in terms of manufacturing cost and power consumption reduction. In addition, a consumer digital VTR that operates at low speed
It is not desirable to mount a processing circuit for performing a high-speed operation for high image quality digital VTRs and an operation mode switching circuit inside the IC used for the above because it is wasteful and costly when considering the IC itself.

From the above viewpoint, the internal circuit of the signal processing IC of the consumer digital VTR is left as it is,
It would be very convenient if a signal processing circuit for a high image quality digital VTR could be constructed by using a plurality of these ICs or adding some external circuits. The same applies to digital disc recorders in addition to VTRs.

The present invention focuses on these points,
A high-quality video signal recording / reproducing process can be performed by using an IC used in a video signal recording / reproducing device such as a consumer digital VTR, and the cost of the high-quality video equipment can be reduced. It is an object of the present invention to provide an encoding circuit and a decoding circuit for high digital video signals.

[0014]

In order to achieve the above object, the digital video signal encoding circuit of the present invention comprises an orthogonal transform means for performing two-dimensional orthogonal transform on a digitized video signal, and thereby an orthogonal transform means. Scanning means for scanning the obtained two-dimensional converted data in a predetermined order to obtain a data string, separation means for separating the data string thus obtained into at least two data strings, and separation means Coding means for allocating a code to each data string by a two-dimensional variable-length coding method combining a zero run length and a data value is provided.

Further, the digital video signal decoding circuit of the present invention is provided with a decoding means for reproducing the video signal coded by the digital video signal coding circuit from the recording medium and decoding the video signal. It is characterized in that it comprises a mixing means for mixing the encoded data string by a method reverse to the method of separation by the separating means.

[0016]

According to the present invention, the data string after orthogonal transformation is separated into at least two data strings. Therefore, the amount of information can be equally divided into good parts, and high quality image processing can be realized by arranging, in parallel, those having a low amount of processing information as the subsequent encoding means.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital video signal encoding circuit and a decoding circuit according to the present invention will be described below in detail with reference to the accompanying drawings. The same reference numerals are used for the same components as those of the above-described conventional technique or components corresponding to the conventional technique.

FIG. 1 shows a signal processing circuit of a high image quality digital VTR according to this embodiment. In the figure,
First, the structure of the recording side will be described. A high efficiency encoding circuit 50 is connected to the output side of the A / D converter 10. The high efficiency coding circuit 50 includes an orthogonal transformation circuit 52 and a separation circuit 5.
4, variable length coding circuits 16A and 16B are included, and for example, the configuration is as shown in FIG. On the output side of the variable length coding circuit 16A, the error correction coding circuit 18A,
Recording coding circuit 20A, amplifier 22A, recording head 24
A is connected in order. In addition, the variable length coding circuit 16
An error correction coding circuit 18B, a recording coding circuit 20B, an amplifier 22B, and a recording head 24B are sequentially connected to the output side of B.

Next, the structure of the reproducing side will be described. An amplifier 30A, a data detecting circuit 32A, an error correcting circuit 34A, a variable length code decoding circuit 3 are provided on the output side of the reproducing head 28A.
6A are connected in order. An amplifier 30B, a data detection circuit 32B, an error correction circuit 34B, and a variable length code decoding circuit 36B are sequentially connected to the output side of the reproducing head 28B. The variable length code decoding circuit 36A,
The output side of 36B is connected to the mixing circuit 56, and the output side of this mixing circuit 56 is the orthogonal inverse transform circuit 38, D /
It is connected to the A converter 40 in order.

FIG. 2 shows the detailed structure of the high-efficiency coding circuit 50, in which a DCT circuit 60 is provided on the input side. A zigzag scan circuit 62 is connected to the output side of the DCT circuit 60.
0, orthogonal transformation circuit 5 by zigzag scan circuit 62
2 are configured.

The output side of the zigzag scan circuit 62 is connected to the common input side of the separation switch 64. One switching output side of the separation switch 64 is connected to the switching input side of the data addition switch 66, and the other switching output side is connected to the switching input side of the data addition switch 68. Data of logical value "0" is supplied to the other switching input side of the data addition switches 66 and 68. The switches 64, 66 and 68 form a separation circuit 54.

Next, the output side of the data addition switch 66 is connected to the quantizer 70A and the code amount control circuit 72A, respectively. The output side of the code amount control circuit 72A is connected to the quantizer 70A, and the output side of the quantizer 70A is connected to the two-dimensional Huffman coding circuit 74A.
The quantizer 70A, the code amount control circuit 72A, and the two-dimensional Huffman coding circuit 74A constitute a variable length coding circuit 16A.

The output side of the data addition switch 68 is connected to the quantizer 70B and the code amount control circuit 72B, respectively. The output side of the code amount control circuit 72B is connected to the quantizer 70B, and the output side of the quantizer 70B is connected to the two-dimensional Huffman coding circuit 74B.
The quantizer 70B, the code amount control circuit 72B, and the two-dimensional Huffman coding circuit 74B constitute a variable length coding circuit 16B. Further, a system control circuit 76 for controlling the system operation of the entire high efficiency encoding circuit 50 is provided.

Of the above units, the DCT circuit 60 is for orthogonally transforming video data of, for example, 8 × 8 = 64 pixels by a two-dimensional DCT. The zigzag scan circuit 62 is for zigzag scanning and outputting the 64 pieces of transform coefficient data after DCT conversion in the order shown in FIG. In both cases, the basic operation is the same as the above-mentioned conventional example.

The separation switch 64 has a function of alternately switching the input coefficient data string and outputting it.
As a result, the input data is divided into 32 even-numbered data strings and 32 odd-numbered data strings. The data addition switches 66 and 68 are for adding the data of the coefficient value "0" to the 33rd to 64th positions of each of the 32 separated data strings.

Next, the quantizers 70A and 70B are for quantizing the input data with the roughness set based on the code amount control by the code amount control circuits 72A and 72B. The two-dimensional Huffman encoding circuits 74A and 74B are provided with the number m (run length) of the coefficient value "0" of the input data.
h () and the following non-zero coefficient n are paired with C (m,
It is for performing code assignment considering the appearance frequency for n). The operations of the quantizer and the encoding circuit are the same as those of the conventional example.

That is, in this embodiment, the processing circuits from the variable length coding circuits 16A and 16B to the recording heads 24A and 24B are constituted by ICs for consumer digital VTRs, and perform signal processing in parallel. Basically, it is possible to handle double the code amount.

Next, the overall operation of the embodiment configured as described above will be described. The analog video signal to be processed is input to the A / D converter 10 where it is converted into a digital video signal. Then, after that, it is supplied to the DCT circuit 60 of the orthogonal transformation circuit 52, where DCT
Processing is performed. The coefficient data after conversion is supplied to the zigzag scan circuit 62. Then, scanning is performed in the order shown in FIG. 6 and serially output.

The coefficient data after the zigzag scan is first input to the separation switch 64, where it is separated into even-numbered data strings and odd-numbered data strings. That is, data is distributed by the separation switch 64 such that the even-numbered coefficient data string is on the switch 66 side and the odd-numbered coefficient data string is on the switch 68 side.
FIG. 3 shows numbers representing the order of the separated coefficient data strings. In FIG. 3A, even-numbered data strings and (B) are shown.
Is an odd numbered data string.

Of these, the even numbered data strings are supplied to the data addition switch 66, where the 33rd to 64th data are added.
Next, the data of the coefficient value "0" is added as shown in FIG. Similarly, the odd numbered data sequence is supplied to the data addition switch 68, and the data of the coefficient value "0" is added to the 33rd to 64th positions as shown in FIG.

Here, if the values of the plurality of coefficient data from the 1st to 64th, that is, the 64 pieces of transform coefficient data by the DCT circuit 60 are values other than "0", the 1st to the 32nd Indicates that there is data other than "0", and that two sets of coefficient data in which the number of data other than "0" is stochastically ½ that before the separation processing are obtained. In reality, this is not always the case, because "0" also exists in the 1st to 32nd positions. Since this separation processing only rearranges coefficient data and adds "0" data, the total amount of information does not change.

The even-numbered and odd-numbered coefficient data strings thus separated are respectively variable length coding circuits 16A, 1A.
6B is supplied. Then, first, the quantizers 70A, 70
In B, the quantization processing that approximates at a discrete level is performed. The roughness of the quantization level at this time is controlled by the code amount control circuits 72A and 72B, and so-called non-linear quantization is performed.

Next, the quantized coefficient data string is supplied to the two-dimensional Huffman coding circuits 74A and 74B, respectively. Then, a variable length coding process is performed in which a short code is assigned to a high frequency level according to the appearance frequency of each quantization level. Specifically, two-dimensional Huffman coding is performed in which the zero run length and the value of the quantized coefficient data are combined to perform two-dimensional code assignment.

For example, when the two-dimensional Huffman coding is performed on the data string as shown in FIG. 4, it becomes as follows. The first “005” has a number of consecutive 0s of “2”, and the value of the second non-zero coefficient is “5”, so that the pair C thereof is used.
A code is assigned with a length corresponding to the appearance frequency of (2, 5). The next “01” has a length corresponding to the frequency of appearance of the pair C (1,1), because the number of consecutive 0s is “1” and the value of the next non-zero coefficient is “1”. Code assignment is performed. The next "000004" has a number of consecutive 0s of "5", and the value of the next non-zero coefficient is "4". Therefore, the length corresponding to the frequency of appearance of the pair C (5,4). Code assignment is performed. The same applies hereinafter.

Next, for the encoded signal,
The coding for error correction by the error correction coding circuits 18A and 18B and the coding for recording by the recording coding circuits 20A and 20B are respectively performed in the same manner as in the conventional example. The final encoded data is the amplifier 22
After amplification by A and 22B, recording is performed on the video tape 26 by the recording heads 24A and 24B.

Next, the operation of the high efficiency coding circuit 50 will be further described. As described above, the variable length coding circuit 1
As described above, the processing circuits from 6A and 16B to the recording heads 24A and 24B are ICs for consumer digital VTRs.
By performing signal processing in parallel, it is basically possible to handle double the code amount. In other words, either one can handle only the same amount of information as the conventional one. Therefore, it is desirable that the separation circuit 54 ideally separates the information amount into 1/2. For example, if they are separated at a ratio of 6: 4, the one having a large amount of information will exceed the processing capacity and the information will be lost.

However, in this embodiment, the coefficient data string after the orthogonal transformation is separated into two data strings in the separation circuit 54, the data is collected in the low frequency part and "0" is recorded in the high frequency part. Will be added. As a result, the data string is separated into two data strings each having an information amount of about ½, and the following processing such as two-dimensional Huffman coding is performed on these data strings. Therefore, the above-mentioned inconvenience due to the imbalance of the separation of the information amount does not occur.

Considering these points, the amount of information lost by compression will be examined. First, it is assumed that the information amount on the output side of the orthogonal transformation circuit 14 of the conventional example in FIG. 5 is DA and the information amount after compression on the output side of the variable length coding circuit 16 is DB. That is, the maximum amount of information that can be handled by the variable length coding circuit 16 is DB. Then, the amount of information in DA-DB is lost.

On the other hand, in the present embodiment shown in FIGS. 1 and 2, it is as follows. First, it is assumed that the amount of information on the output side of the orthogonal transformation circuit 52 is the same DA as in the conventional example.
Since the separation circuit 54 only separates the data, there is no loss of information amount. Next, the variable length coding circuit 1
The processing capacities of 6A and 16B are DBs as in the conventional example. In the separation circuit 54, the amount of information is separated into approximately DA / 2 as described above. Therefore, the amount of information lost in the variable length coding circuits 16A and 16B is approximately DA / 2.
-DB, and DA-2DB as a whole. That is, the loss of information is reduced by the amount of DB, and data can be recorded on the video tape 26 with the amount of information including this amount, and a high quality VTR can be realized.

For example, assuming that the amount of information is proportional to the data rate, the data length of the video signal of about 160 Mbps is set to about 25 Mbps by the variable length coding circuits 16A and 16B.
Consumer digital VT that outputs compressed data to ps
Assume that an IC for R is used. According to the present embodiment, the variable length coding circuits 16A and 16B respectively output about 2
Since the data of 5 Mbps is output, the data of about 50 Mbps can be obtained as a whole, and the high image quality digital VTR having the information amount about twice can be constructed.

The reproducing side will be described next. The data reproduced from the video tape 26 by the reproducing heads 28A and 28B is amplified by the amplifiers 30A and 30B and then supplied to the data detecting circuits 32A and 32B, where the synchronizing signal is generated. The data related to the image excluding the control signal and the like is detected. Error detection and correction by the error correction circuits 34A and 34B, and variable length code decoding circuits 36A and 3B
After the decoding by 6B is sequentially performed, the mixing process by the mixing circuit 56, that is, the process opposite to the separation by the separation circuit 54 is performed. The mixed data string is the orthogonal inverse transform circuit 3
8 performs an inverse orthogonal transform process that is the inverse of DCT, and the data is decoded. Further, the decoded digital video signal is converted into an analog video signal by the D / A converter 40. In this way, the data is decoded and the video signal is reproduced.

As described above, according to the present embodiment, since the DCT coefficient data string after orthogonal transformation is separated into two data strings by the separation circuit, the amount of information is approximately 1/2.
Is separated into Therefore, even if the subsequent processing such as variable length coding is performed using the IC used in the video signal recording / reproducing apparatus such as a consumer digital VTR, the high image quality video signal recording / reproducing processing can be performed. The advantage is that the cost of high-quality video equipment can be reduced, and it is very practical.

<Other Embodiments> The present invention is not limited to the above embodiments, and includes, for example, the following. (1) In the above embodiments, the DCT in which 8 × 8 pixels are used as the orthogonal transform is used, but the number of pixels may be set appropriately, or another transform method may be used. The same applies to the variable length coding method. Further, the method of zigzag scanning is not limited to the one shown in FIG. 6, and any order may be used as long as the data can be serialized. However, the mixing circuit 56 on the reproducing side performs mixing in the reverse order of the zigzag scanning order. (2) In the above-described embodiment, the two data strings having almost the same number of data are separated, but they may be separated into a larger number if necessary.

(3) For example, if the output side of the orthogonal transformation circuit 52 of FIG. 1 is directly connected to the input side of the variable length coding circuit 16A, the configuration is the same as that of the conventional device of FIG.
If such a connection and the connection of FIG. 1 are switched by a switch, a plurality of operation modes such as a standard mode and a high image quality mode are provided, and one VTR changes the information amount of the recording / reproducing data. Is also possible. (4) In the above embodiment, the variable length coding is performed after the data "0" is added by the separation circuit 54, but it is the same as when the data "0" is added on the variable length encoder side. If the encoding process can be performed on the above, it is not necessary to add data at the time of separation.

(5) In the above-described embodiment, the processing after the coding by the variable length coding circuit is also carried out in different channels to record the signal on the video tape. However, after the coding, the time division is carried out. The circuit may be configured to combine the data of both channels into one channel, such as frequency division. The same applies to the reproducing side. (6) In the above embodiment, the present invention is applied to a digital VTR, but the present invention is also applicable to other video recording / reproducing devices such as a disc recorder.

[0046]

As described above, according to the encoding circuit and the decoding circuit of the digital video signal according to the present invention, the data after the orthogonal transformation is separated into at least two data strings. There is an effect that high-quality video signal recording / reproducing processing can be performed using an IC used in a video signal recording / reproducing apparatus such as a digital VTR, and the cost of high-quality video equipment can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of an encoding circuit and a decoding circuit for a digital video signal according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a high efficiency coding circuit in the above embodiment.

FIG. 3 is an explanatory diagram showing a data string after separation in the embodiment.

FIG. 4 is an explanatory diagram showing a state of two-dimensional Huffman coding.

FIG. 5 is a circuit block diagram showing an example of a conventional signal processing circuit.

FIG. 6 is an explanatory diagram showing a method of zigzag scanning.

[Explanation of symbols]

10 ... A / D converter, 16A, 16B ... Variable length coding circuit, 18A, 18B ... Error correction coding circuit, 20A, 2
0B ... Recording coding circuit, 22A, 22B, 30A, 30
B ... Amplifier, 24A, 24B ... Recording head, 26 ... Video tape, 28A, 28B ... Playback head, 32A, 32
B ... Data detection circuit, 34A, 34B ... Error correction circuit,
36A, 36B ... Variable length code decoding circuit (decoding means), 38 ... Orthogonal inverse conversion circuit, 40 ... D / A converter, 5
0 ... High efficiency coding circuit, 52 ... Orthogonal transformation circuit, 54 ... Separation circuit (separation means), 56 ... Mixing circuit (mixing means), 6
0 ... DCT circuit (orthogonal transform means), 62 ... Zigzag scan circuit (scan means), 64 ... Separation switch (separation means), 66, 68 ... Data addition switch, 70
A, 70B ... Quantizer, 72A, 72B ... Code amount control circuit, 74A, 74B ... Two-dimensional Huffman coding circuit (encoding means).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hironori Akasaka 3-12 Moriya-cho, Kanagawa-ku, Yokohama, Kanagawa Japan Victor Company of Japan, Ltd. (72) Masami Mori 3--12 Moriya-cho, Kanagawa-ku, Yokohama Address inside Victor Company of Japan, Ltd.

Claims (2)

[Claims] 1. An orthogonal transform means for performing a two-dimensional orthogonal transform on a digitized video signal, and a scan for scanning the two-dimensional transformed data obtained by this in a predetermined order to obtain a data string. Means, separating means for separating the data string obtained by this into at least two data strings, and two-dimensional variable length combining zero run length and data value for each data string separated by this means A digital video signal encoding circuit, comprising: an encoding unit that assigns a code by an encoding method. 2. A decoding means for reproducing a video signal coded by the digital video signal coding circuit according to claim 1 from a recording medium and decoding the video signal, and a coded data string obtained by the decoding means. A digital video signal decoding circuit, comprising: a mixing means for mixing by a separating means by a separating means and a mixing means for mixing by a reverse method.