JPH06334918A - Digital frame phase correcting circuit - Google Patents

Abstract

PURPOSE:To reduce the reduction of a sense of quality due to the way of observing a frame part by additionally inserting frame data whose level is reduced into the outside of conventional frame data. CONSTITUTION:This digital frame phase correcting circuit is constituted of a coefficient multiplier 10 for multiplying frame data by a coefficient a 1st switch 11 for inputting a digitized video signal and the output of the multiplier 10 and switching these inputs by a frame insertion pulse (b), a 2nd switch 12 for inputting the output of the 1st switch 11 and frame data and switching these inputs by a frame insertion pulse (a), a phase shifter 13 for inputting the output signal of the 2nd switch 12 and phase shift data and adjusting the phase shift value of the output signal from the 2nd switch 12 in accordance with the phase shift data, and a 3rd switch 14 for inputting an external video signal and the output signal of the phase shifter 13 and selecting one of these inputs by a switching signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital frame phase correction circuit in a digital color television receiver.

[0002]

2. Description of the Related Art In recent years, the trend toward digitalization in the signal processing of televisions has been increasing with the improvement in image quality and multifunctionality of television receivers. A digital frame phase correction circuit is required when inserting the frame at the boundary to be switched.

A conventional digital frame phase correction circuit will be described below with reference to FIG. FIG. 3 shows a configuration of a conventional digital frame phase correction circuit. In FIG. 3, 20
Is a first switch which receives the digitized video signal and frame data and switches the input by a frame insertion pulse. Reference numeral 21 is a phase shifter which receives the output signal of the first switch 20 and the phase shift data as input and adjusts the phase shift amount of the output signal of the first switch 20 according to the value of the phase shift data. The input signal 22 is an output signal of the phase shifter 21 and an external video signal, and the input is switched by a switching signal and output.

The phase shifter 22 will be described below with reference to FIG. FIG. 4 shows a circuit configuration of the phase shifter.
In FIG. 4, reference numeral 31 is a flip-flop that receives the input data a, delays the data by one clock, and outputs the delayed data b. 32 is input data a and delay data b
Is input, the delay data b is subtracted from the input data a, and the difference data c is output. Reference numeral 33 is a multiplier which inputs the correction data d and the difference data c and outputs the multiplication result e. A coefficient unit 34 receives the multiplication result e, multiplies it by 1/16, and outputs the correction data f. Reference numeral 35 is an adder that inputs the correction data f and the delay data b, adds them, and outputs a phase shifter output g.

The operation of the phase shifter 22 configured as described above will be described below with reference to FIGS. 4 and 5. The relationship from a to g shown in FIG. 4 will be described with reference to FIG. First, when the delay data b and the input data a are points at the time indicated by the rising edge of the clock, the point g interpolated by the phase shifter 22 is advanced from the point of the delay data b by the phase shift data d. It becomes a point. In order to realize this correction,
In the circuit shown in FIG. 4, the delay data b is subtracted from the input data a by the subtractor 32 to first obtain the difference data c. The difference data c is input to the multiplier 33 and is multiplied by the phase shift data d to obtain the multiplication result e. Here, the correction data d
Is 0 to 1 to make the interpolation accuracy 1/16 of the clock.
Any value of 5 is given. Next, in order to obtain the correction data f from the multiplication result e, in order to normalize the value of the phase shift data f, the multiplication result e is multiplied by 1/16 in the coefficient unit 34. Finally, the correction data f and the delay data b thus obtained are added up by the adder 35 to calculate the phase shifter output g.

The operation of the digital frame phase correction circuit configured as described above will be described below with reference to FIG.
First, as shown in FIG. 6, the digitized video signal is input to the first switch 20 so that the frame insertion pulse is L
When it is ow, the output of the first switch 20 is a video signal, and when the frame insertion pulse is High, frame data is an output. The phase shifter 21 inputs the output signal of the first switch 21 and shifts the phase of the video signal according to the value of the phase shift data. The second switch 22 inputs the output signal of the phase shifter 21 and the external video signal, selects the external video signal when the switching signal is Low, and selects and outputs the output signal of the phase shifter 21 when the switching signal is High. To do.

[0007]

However, in the above configuration, when the video signal whose phase shift data changes line by line is switched to an external video signal which divides the screen into two in the horizontal direction. However, since the amplitude level of the frame changes depending on the amount of phase shift of the signal, there is a problem in that the frame portion looks wavy and the texture of the entire screen deteriorates.

The present invention has been made in consideration of the above problems, and by additionally inserting frame data whose level is lowered outside the conventional frame data, the phase shift data is changed for each line. , Considering that it is possible to suppress the fluctuation amount of the frame amplitude level and reduce the deterioration of the texture due to the appearance of the frame portion even when switching to an external video signal that divides the screen horizontally into two. It is intended to provide a digital frame phase correction circuit.

[0009]

In order to solve the above-mentioned problems, a digital frame phase correction circuit according to the present invention uses a frame data as an input and a coefficient multiplier for multiplying a coefficient α, a digitized video signal and a coefficient multiplier. The first switch for switching the input by the first frame insertion pulse and the output for the first switch and the frame data as the input, and the second switch for switching the input by the second frame insertion pulse a. Switch, a phase shifter that receives the output signal of the second switch and the phase shift data as input, and adjusts the phase shift amount according to the value of the phase shift data, and an external image A signal and the output signal of the phase shifter are input, and the input is selected by the switching signal.
It consists of switches.

[0010]

According to the present invention, by the above structure, the frame data whose level is lowered is additionally inserted outside the conventional frame data to suppress the fluctuation amount of the frame amplitude level with respect to the change of the phase shift data for each line. Therefore, even when switching to an external video signal such that the screen is divided into two in the horizontal direction, it is possible to reduce deterioration in texture due to the appearance of the frame portion.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital frame phase correction circuit according to an embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the configuration of a digital frame phase correction circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a coefficient unit that inputs the frame data and multiplies the coefficient α having a value of ¼. A first switch 11 receives the digitized video signal and the output of the coefficient unit 10 and switches the input by the frame insertion pulse b. Reference numeral 12 is a second switch which receives the output of the first switch 11 and the frame data as input and switches the input by the frame insertion pulse a. Thirteen
Is the same as that shown in FIG. 4, in which the output signal of the second switch 12 and the phase shift data are input, and the output signal of the second switch 12 is adjusted in the amount of phase shift according to the value of the phase shift data. It is a phase shifter. 14 is an external video signal and a phase shifter 13
Is a third switch that receives the output signal of the input signal and selects the input according to the switching signal.

With respect to the digital frame phase correction circuit configured as described above, the operation of the digital frame phase correction circuit will be described below with reference to FIG. First, as shown in FIG. 2, the digitized video signal is transmitted to the first switch 11
When the frame insertion pulse a is Low, a video signal is output to the output of the first switch 11. When the frame insertion pulse a is High, a value of 1/4 of the frame data is output. The second switch 12 inputs the output signal of the first switch 11 and the frame data, outputs the video signal when the frame insertion pulse b is Low, and outputs the frame data when it is High. . The phase shifter 13 inputs the output signal of the second switch 12 and shifts the phase of the video signal according to the value of the phase shift data. The third switch 14 inputs the output signal of the phase shifter 13 and the external video signal, selects the external video signal when the switching signal is Low,
When Hi, the output signal of the phase shifter 13 is selected and output.

As described above, according to the present embodiment, the frame data whose level is lowered is additionally inserted outside the conventional frame data, so that the amplitude level of the frame changes with respect to the change of the phase shift data line by line. The amount can be suppressed and the screen can be moved horizontally 2
Even when switching to an external video signal for division is performed, it is possible to reduce deterioration in texture due to the appearance of the frame portion.

[0015]

As described above, according to the present invention, by additionally inserting the frame data whose level is lowered outside the conventional frame data, the amplitude level fluctuation of the frame with respect to the change of the phase shift data line by line. It is possible to reduce the amount and reduce the deterioration of the texture due to the appearance of the frame portion even when switching to an external video signal such that the screen is divided into two in the horizontal direction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital frame phase correction circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the digital frame phase correction circuit in the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional digital frame phase correction circuit.

FIG. 4 is a block diagram of a digital phase shifter in a digital frame correction circuit.

FIG. 5 is an operation explanatory diagram of a digital phase shifter in a digital frame correction circuit.

FIG. 6 is a timing chart showing the operation of a conventional digital frame phase correction circuit.

[Explanation of symbols]

 10 Coefficient device 11 First switch 12 Second switch 13 Phase shifter 14 Third switch

Claims (1)

[Claims] 1. A coefficient unit for inputting frame data and multiplying by a coefficient α, and a first switch for inputting a digitized video signal and an output of the coefficient unit and switching the input by a first frame insertion pulse. A second switch that receives the output of the first switch and the frame data as input and switches the input by a second frame insertion pulse, and outputs the output signal of the second switch and phase shift data as input, The output signal of the switch No. 2 is a phase shifter for adjusting the amount of phase shift according to the value of the phase shift data, the external video signal and the output signal of the phase shifter are input, and the input is selected by the switching signal. A digital frame phase correction circuit having a third switch.