JPH06334644A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To reduce the probability of synchronization error and to excellently reproduce a synchronizing signal by providing each circuit generating a synchronizing signal by respectively detecting the matching with a fixed data pattern for the output where each bit shift is performed for the output of a delay circuit according to the detection result of the phase matching with the fixed data pattern. CONSTITUTION:Digital data(Dd) delayed by a time interval unit by delay circuits 21 to 25 is delayed by a bit unit by a bit shift detection circuit 26. According to the result where the circuit 6 detects the phase which matches with a fixed data pattern(Dp), variable shift registers VSR 27 to 31 perform each bit for the output Dd of the circuits 21 to 25. As for these shift data SD 0 to 4, synchronizing/ID detection circuits 32 to 36 detect the matching with Dp. According to this result, comparators 37 to 40, a synchronizing location, bit shift correction circuits 41 and 42 and inertia mask circuits 13 and 14 form a synchronizing signal. Thus, the correct synchronizing signal is outputted, and excellently reproduced with low synchronization error rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal generator suitable for application to a sync signal generator for detecting sync signals of digital data.

[0002]

2. Description of the Related Art Digital data is composed of a sync pattern necessary for reproduction, ID0 (identification number given to each sync block described later), ID1 (indicating contents of data) and data. An example of a sync signal generation device that detects a sync pattern of such digital data and generates a sync signal is shown in FIG.

In FIG. 11, reference numeral 1 is an input terminal for supplying digital data supplied from a reproduction system of a digital VTR (not shown) to a delay circuit 2, a variable shift register 7 and a bit shift detection circuit 6 which will be described later, and 2 Is a delay circuit for delaying the digital data supplied through the input terminal 1 by a predetermined delay time L, 3 is a delay circuit for further delaying the delay output of the delay circuit 2 by 5 L, and 4 is an output Dx of the delay circuit 3. Is a variable shift register 5 for latching based on a control signal from a bit shift phase correction circuit 16 which will be described later. The variable shift register 5 is an output terminal for supplying the latch output of the variable shift register 4 to a VTR reproducing system (not shown). Where delay time L
Is the time corresponding to the length of one sync block described later.

A bit shift detection circuit 6 detects a bit shift amount of the digital data D0 supplied through the input terminal 1 on the basis of bit shift information included in a sync pattern, which will be described later, and detects the detected shift. Quantity data (hereinafter referred to as a signal) PH0 is supplied to the variable shift registers 7 and 10 and a bit shift phase correction circuit 16 described later, respectively.

The variable shift register 7 has an input terminal 1
The digital data D0 supplied via the bit shift signal is bit-shifted based on the shift amount data PH0 from the bit shift detection circuit 6. Further, the variable shift register 10 bit-shifts the digital data D1 delayed by the delay time L from the delay circuit 2 based on the shift amount data PH0 from the bit shift detection circuit 6.

These variable shift registers 7 and 1
The shift outputs SD0 and SD1 of 0 are supplied to the sync / ID detection circuits 8 and 11, respectively. These synchronization / ID detection circuits 8 and 11 are respectively shift outputs SD0 and SD1 from the variable shift registers 7 and 10, that is, the input terminal 1
The sync patterns and IDs (ID0 and ID1) of the digital data D0 supplied via the digital data D0 and the digital data D1 delayed by the delay time L, respectively, and the detected sync patterns,
The ID data is supplied to the comparator 9.

The comparator 9 compares the sync pattern and the ID data from the sync / ID detection circuits 8 and 11, respectively, and supplies a signal SY1 as the comparison result to the sync position correction circuit 12. The sync position correction circuit 12 supplies a correction signal for correcting the position of the sync signal to the bit shift phase correction circuit 16 based on the signal SY1 from the comparator 9 and the signal ID0 from the sync / ID detection circuit 8. , The signal SYx is supplied to the inertia circuit 13.

The bit shift phase correction circuit 16 generates a correction signal for performing a bit shift based on the signal SYx from the synchronous position correction circuit 12, and supplies this to the variable shift register 4. As a result, the variable shift register 4 latches the digital data Dx from the delay circuit 3 and supplies it to the reproducing system (not shown) such as a digital VTR via the output terminal 5.

On the other hand, the inertia circuit 13 generates a temporary synchronization signal SYi based on the signal SYx from the synchronization position correction circuit 12, and supplies the generated temporary synchronization signal SYi to the mask circuit 14. The mask circuit 14 does not output the temporary synchronization signal SYi from the inertia circuit 13 having a cycle shorter than the delay time L described above. Then, the other signal is supplied as a synchronizing signal SYm to a reproducing system such as a digital VTR (not shown) through the output terminal 15.

Next, referring to FIG. 12, the sync position correction circuit 12 and the bit shift phase correction circuit 16 shown in FIG.
The internal configuration of will be described.

In the figure, reference numeral 50 denotes an input terminal to which a signal SY1 as a comparison output from the comparator 9 shown in FIG. 11 is supplied, and the signal SY1 is supplied to the sync delay controller 55 via this input terminal 50. 54 is FIG.
I, which is the output from the synchronization / ID detection circuit 8 shown in FIG.
This is an input terminal to which D0 is supplied.

The sync delay controller 55 has an input terminal 5
11 based on the signal SY1 supplied from the comparator 9 shown in FIG. 11 and the signal ID0 supplied from the synchronization / ID detection circuit 8 shown in FIG. 11 via the input terminal 54, the signals LD0, LD1 and LD2. , LD3 and LD4 are output.

Now, the relationship between the signal SY1, the signal ID0, and the signals LD0, LD1, LD2, LD3, and LD4 will be described. First, when the signal SY1 is "0", the signals LD0, LD1, LD2, LD3 and LD4 are all "0". When the signal SY1 is "1", the signals LD0, LD1, LD2, LD3 and LD4 have values based on the value of the signal ID0. The sync delay controller 55 outputs signals LD0, LD1,
It has a table for determining the values of LD2 and LD3.

That is, when the signal SY1 is "1", ID0
The signals LD0, LD1, LD2 and LD3 are as follows according to the value of

ID0: LD0 LD1 LD2 LD3 LD4 1: 1 1 0 0 0 0 2: 1 1 0 0 0 3: 1 1 1 1 0 0 4: 1 1 1 1 1 0 5: 1 1 1 1 1 0: 0 0

The signal LD0 is supplied to the delay circuit 56 and the delay circuit 68 of the bit shift phase correction circuit 16 described later, respectively. The signal LD0 delayed by the delay circuit 56 is supplied to the adding circuit 57. The signal LD1 is supplied to the adder circuit 57 and the delay circuit 69 of the bit shift phase correction circuit 16, respectively. The adder circuit 57 adds the signal LD1 from the sync delay controller 55 and the output (a signal obtained by delaying the signal LD0) from the delay circuit 56, and supplies the signal SL1 as the addition result to the delay circuit 58.

The adder circuit 5 delayed by the delay circuit 58
The output of 7 is supplied to the adder circuit 59. The signal LD2 from the sync delay controller 55 is supplied to the adder circuit 59 and the bit shift phase correction circuit 16 described later, respectively. The adder circuit 59 outputs the signal LD2 from the sync delay controller 55 and the delay output (signal L from the delay circuit 58).
Signal obtained by adding the signal LD1 to the signal obtained by delaying D0) and adding the signal SL2
Are supplied to the delay circuit 60.

The delay circuit 60 delays the addition output of the addition circuit 59 and supplies it to the addition circuit 61. The signal LD3 from the sync delay controller 55 is supplied to the adder circuit 61 and the bit shift phase correction circuit 16 described later, respectively.
The adder circuit 61 outputs the signal LD3 from the sync delay controller 55 to the delayed output (signal LD0) from the delay circuit 60.
LD1 is added to the delayed signal, the signal LD2 is added to the delayed signal, the signal delayed from this signal is added, and the addition result signal SL3 is supplied to the delay circuit 62. .

The delay circuit 62 delays the addition output from the addition circuit 61 and supplies it to the addition circuit 63. The signal LD4 from the sync delay controller 55 is supplied to the adder circuit 63 and the bit shift phase correction circuit 16 described later, respectively. The adder circuit 63 adds the signal LD4 from the sync delay controller 55 and the delayed output from the delay circuit 62 (the signal LD1 is added to the delayed signal of the signal LD0, the signal LD2 is added to the delayed signal of this signal, and The signal LD3 is added to the delayed signal, the delayed signal is added, and the resulting signal SL4 is added to the delay circuit 64 and the bit shift phase correction circuit 16 described later.
Supply to each.

The delay circuit 64 receives the signal S from the adder circuit 63.
L4 is delayed to obtain the signal SYx, and this signal SYx is delayed by the delay circuit 66 and the bit shift phase correction circuit 16 described later.
Inertia circuit 1 shown in FIG. 11 via output terminal 65
Supply to 3 respectively.

On the other hand, the delay circuit 68 of the bit shift phase correction circuit 16 receives the signal SL0 from the sync delay controller 55 (the signal LD in FIG. 12) based on the shift amount data PH0 from the bit shift detection circuit 6 shown in FIG.
0)) to obtain the delayed signal PL0,
This signal PL0 is supplied to the delay circuit 69. Delay circuit 6
Reference numeral 9 indicates the shift amount data PH0 supplied via the input terminal 67 with the signal SL1 from the adder circuit 57 enabled.
Based on the above, the signal PL0 from the delay circuit 68 is delayed to obtain the signal PL1, and this signal PL1 is supplied to the delay circuit 70.

The delay circuit 70 receives the signal S from the adder circuit 59.
The signal PL1 from the delay circuit 69 is delayed to obtain the signal PL2 based on the shift amount data PH0 supplied via the input terminal 67 with L2 enabled, and this signal PL2 is supplied to the delay circuit 71. The delay circuit 71 is an adder circuit 61
Signal PL3 from delay circuit 70 is delayed based on shift amount data PH0 supplied through input terminal 67 to obtain signal PL3, and signal PL3 is supplied to delay circuit 72.

The delay circuit 72 receives the signal S from the adder circuit 63.
The signal PL3 from the delay circuit 71 is delayed based on the shift amount data PH0 supplied via the input terminal 67 with L4 enabled, and the signal PL4 is supplied to the delay circuit 73. The delay circuit 73 is the delay circuit 72
Signal PL4 from the delay circuit 6 of the synchronization position correction circuit 12
The signal SL5 from 4 is delayed as the enable signal P.
L5 is obtained and this signal PL5 is supplied to the delay circuit 74.
The delay circuit 74 enables the signal SL6 from the delay circuit 66 to delay the signal PL5 from the delay circuit 73 to obtain the signal PHL, and the signal PHL is sent to the variable shift register 4 shown in FIG. Supply.

Next, referring to FIGS. 13 and 14, FIG.
The delay circuits 69, 70, 71, 72, 73 and 7 shown in FIG.
4 and the inertia circuit 1 shown in FIG.
3. The internal structure of the mask circuit 14 will be sequentially described.

FIG. 13A shows the delay circuit 69 shown in FIG.
The internal structure of 70, 71, and 72 is shown, and in the figure, 1
00 is a signal LDIN (in FIG. 12, signals LD0, LD1, LD supplied from the sync delay controller 55)
2, LD3, LD4) are supplied, 101 is a signal SLIN (in FIG. 12, signals SL0, SL1, SL2, SL3, SL4 supplied from the sync delay controller 55 and adder circuits 57, 59, 61, 63). ) Is supplied, 102 is an input terminal to which the shift amount data PH0 (the shift amount data PH0 supplied via the input terminal 67 in FIG. 12) is supplied, and 103 is a signal P.
IN (in FIG. 12, signals PL0, PL1, PL2, P
L3 and PL4) are supplied, 107 is an input terminal to which a clock signal from a main circuit such as a VTR (not shown) is supplied, and 108 is signals PL0 to PL0 in FIG.
This is an output terminal for outputting PL4. The delay circuit 68 is assumed to be a flip-flop circuit.

In the delay circuits 69 to 72 shown in FIG. 13A, the input terminal 102 to which the shift amount data PH0 is supplied is connected to one fixed contact 104a of the switch 104, and the input terminal 103 is the other fixed contact 104 of the switch 104.
The movable contact 104c of the switch 104 connected to the switch b
Is connected to the other fixed contact 105b of the switch 105, and one fixed contact of this switch 105 is
It is connected to the non-inverting output terminal Q of the flop circuit 106, and the movable contact of the switch 105 is connected to the data input terminal D of the flip-flop circuit 106.
The input terminal 10 is connected to the clock input terminal of the flop circuit 106.
7 is connected, the non-inverting output terminal of the flip-flop circuit 106 is connected to the output terminal 108, and the signal LDIN (see FIG. 12) supplied through the input terminal 100.
, The signal LD from the sync delay controller 55
0, LD1, LD2, LD3 and LD4) to switch 1
The signal SLIN (signals SL0, SL1, SL2, SL3, and SL4 from the sync delay controller 55 and the adder circuits 57, 59, 61, and 63 in FIG. 12) for controlling the signal 04, which is supplied through the input terminal 101, It is configured for controlling the switch 105.

Here, the switch 104 has the input terminal 10
When the signal LDIN supplied via 0 is "1", the movable contact 104c is connected to one fixed contact 104a, and the shift amount data PH0 supplied via the input terminal 102 is selected. There is. Also, switch 1
05 is a signal SLI supplied through the input terminal 101
When N is "1", the movable contact 105c is connected to the other fixed contact 105b to select the signal supplied from the switch 104.

FIG. 13B shows an internal configuration example of the inertia circuit 13 shown in FIG. 11, and as shown in FIG. 13B,
The inertia circuit 13 includes an input terminal 110 to which the signal SYx from the synchronous position correction circuit 12 shown in FIGS. 11 and 12 is supplied, a counter 111 to be reset by the signal SYx supplied via the input terminal 110, and an input. Terminal 1
AND circuit 112 which takes the logical product of the signal SYx supplied via 10 and the output of the counter 111, and the mask circuit 14 shown in FIG.
And an output terminal 113 for supplying

The inertia circuit 13 has an input terminal 110.
When the signal SYx is supplied via the counter, the counter 111 is reset at that point to start counting, and the counter 1
The logical sum of the output of 11 and the signal SYx is obtained to obtain the temporary synchronization signal SYi having a predetermined cycle L.
i is supplied to the mask circuit 14 shown in FIG. 11 via the output terminal 113.

FIG. 14 shows an example of the internal structure of the mask circuit 14 shown in FIG. 11, and the mask circuit 14 shown in FIG.
Is an input terminal 115 to which the temporary synchronization signal SYi from the inertia circuit 13 shown in FIG. 11 is supplied, and a counter 116 which starts counting after being reset by the temporary synchronization signal SYi supplied via the input terminal 115. And a flip-flop circuit 117 that latches the output of the counter 116, a logical product of the output of the counter 116 and the output of the flip-flop circuit 119, and the logical product is supplied to the control terminal of the counter 116. It is composed of a flop circuit 119 and an output terminal 120 for outputting the output of the flip-flop circuit 117 (which becomes the output terminal 15 for outputting the synchronizing signal SYm in FIG. 11).

Here, the operation of the mask circuit 14 shown in FIG. 14 will be described with reference to FIG. 15, m1 is a provisional synchronization signal SYi supplied to the reset terminal reset of the counter 116 via the input terminal 115 shown in FIG. 14, m2 is a carry signal output from the counter 116, and m3 is a flip-flop circuit 117. Of the flip-flop circuit 119, m4 is a latch output of the flip-flop circuit 119, and m5 is a flip-flop circuit 1 of the flip-flop circuit 119.
The counter 116 outputs the signal from the inverting output terminal IQ of the counter 19.
Latch output supplied to the control terminal of the.

The counter 116 has its own reset terminal re
When the signal m1 supplied to the set becomes high level "1", it is reset, and when the signal m5 supplied to its own control terminal becomes low level "0", counting is stopped and the signal supplied to its own control terminal. When m5 becomes the high level "1", the count value is incremented and the L-1 cycle is counted.

When the signal m1 supplied to the reset terminal reset of the counter 116 via the input terminal 115 becomes high level "1", the counter 116 is reset.
The counter 116 counts for L−1 cycles when the signal m5 supplied to the control terminal becomes high level “1”,
When the count value reaches L-1 cycles, the carry signal m2 shown in FIG. 15 is output.

The carry signal m2 is supplied to the data input terminal D of the flip-flop circuit 117. The flip-flop circuit 117 latches the carry signal m2 from the counter 116 with a system clock (not shown). This latch output is the latch output m3 shown in FIG.
become. The latch output m3 is output as the signal Syi via the output terminal 120.

On the other hand, carry signal m2 from counter 116 is supplied to AND circuit 118, and AND circuit 1
In 18, the logical sum is obtained with the signal m4 output from the inverting output terminal IQ of the flip-flop circuit 119.
When the carry signal m2 is high level "1" and the signal m4 is low level "0", the output of the OR circuit 118 is high level "1". Therefore, in this case, the signal m1 is low level at the next clock. Flip to double the "0"
The output of the non-inverting output terminal Q of the flop circuit 119 is high level "1", the output of the inverting output terminal IQ is low level "0", and the operation of the counter 116 is stopped. However, when the signal m1 is input at the high level "1", the flip-flop circuit 119 is reset and the signal m5 becomes the high level "1", so that the counter 116 starts operating.

The counter 116 is reset at the time when the signal m1 becomes high level "1", and then counts up during the period when the signal m5 is high level "1", and (L-1) cycle. Is counted, the carry signal m2 described above is output.

In the example shown in FIG. 15, the fourth pulse from the left of the signal m1 is masked. That is,
The counter 116 starts counting after being reset by the third pulse from the left of the signal m1, but is reset by the fourth pulse from the left of the signal m1 before counting (L-1) cycles. Then, after this reset, the counting is started again, and when the L-1 cycle is counted, the carry signal m2 is output. By the above operation, the mask circuit 14 can mask the pulse that is less than the (L-1) cycle.

Here, an example of the format of the digital VTR will be described with reference to FIGS. 16 and 17.

In FIG. 16, SB is a digital VTR.
1 shows the format of one sync block. One sync block is SY0 and SY1 (sync pattern),
ID0 and ID1 (ID), D0, D1, ... D1
61 (data), P0, P1, ... P13 (inner parity), and all the components other than the sync form an inner code block.

FIG. 17 shows an example of the tape format of the digital VTR. As shown in FIG. 17, in this example, one field is composed of six recording tracks (segments), and each segment has four audio sectors A1 to A4 in the center and these audio sectors A1 to A4.
Servo tracking data S is arranged at both ends of A4, and video sectors V are arranged at both ends of these servo tracking data S, respectively. Also, audio sectors A1 to
As shown in this figure, the A4 array is changed every two segments. Each sector is composed of a plurality of sync blocks shown in FIG.

Now, returning to FIG. 16, the description will be continued. In FIG. 16, ID0 is shown in association with the sector array shown in FIG. ID0 is a sync block number, which includes a video sector V, audio sectors A1 to A4,
A continuous value is given to each sync block of the video sector V.

As shown in the figure, ID1 is V / A indicating a video sector or audio sector, TR indicating a track number, SG indicating a segment number, F indicating a color frame, and C / indicating a component or a composite.
Composed of C.

Next, the continuity of data when receiving data will be described with reference to FIG. In the following description, it is assumed that the ID in the digital data has a value that decreases by "1" for each sync pattern, and that the sectors have the same value in one block. Further, one sector is composed of video / audio data, track number data, two segment number data, two field number data, and option flag data. Further, since the data string is obtained by converting serial data into parallel data, it is necessary to bit shift to the correct phase.

In FIG. 18, the hatched portion is shown in FIG.
The sync pattern shown in A (for example, SYNC0, SYNC
1), ID0, ID1, and data. 18B, 18C, 18D and 18D, ID0 and the symbol L indicating the delay time are respectively attached.

FIG. 18B shows the case where the data is continuous at the time of reception, and FIG. 18C shows the case where the data next to the ID data ID + 3 is lost due to the tape extension or head jump and the data continuity is lost. FIG. 18D shows a case where data continuity is lost due to a discontinuity point due to an edit gap which is a boundary between VTR tracks and a boundary between video and audio recording areas.

On the other hand, in reproducing the synchronization signal, the probability of a synchronization error increases as the byte error rate deteriorates. Once the synchronization is lost, an error occurs for each synchronization block, further deteriorating the overall error rate. That is, if the byte error rate becomes worse than the synchronous detection capability, the number of errors increases avalanche. Therefore,
The correction capability of the entire system depends on the synchronization detection capability rather than the correction code capability. Therefore, considering the balance with the capability of the correction code, it is necessary to have a high synchronization detection capability even with respect to the deterioration of the byte error rate.

Next, the operation of the synchronizing signal generator shown in FIG. 11 will be described with reference to FIG. In FIG. 19A, “●” indicates that the sync pattern could be detected. Further, in FIG. 19H, “●” indicates a sync signal obtained by detecting a sync pattern twice in succession, and “◯”.
Indicates a sync signal generated by the inertia circuit 13 and the mask circuit 14 without the sync pattern being detected twice consecutively.

In the example shown in FIG. 19, ID0 is "2".
The case where the block corresponding to 9 "is missing is shown.

When digital data as shown in FIG. 19B is supplied, the sync pattern indicated by "●" in FIG. 19B is detected, and the detected sync pattern is shown in FIG.
As shown in C. Then, this sync pattern is delayed by the delay time L in the delay circuit 2 and becomes as shown in FIG. 19D. Further, the bit shift detection circuit 6 detects 5 bits of the digital data shown in FIG. 19B to obtain a shift amount, and outputs the shift amount data PH0 to the variable shift registers 7 and 10 and the bit shift phase correction circuit 1.
Supply to 6 respectively.

On the other hand, the variable shift register 7 is supplied with the digital data in which the sync pattern shown in FIG. 19C is detected, and the variable shift register 10 is supplied with the digital data in which the sync pattern shown in FIG. 19D is detected.

The variable shift registers 7 and 10 bit-shift the digital data based on the shift amount data PH0 from the bit-shift detection circuit 6, and supply the bit-shifted digital data to the synchronization / ID detection circuits 8 and 11, respectively. In the sync / ID detection circuits 8 and 11,
The sync patterns ID0 and ID1 are detected from the digital data supplied from the variable shift registers 7 and 10, respectively, and the detected sync patterns and IDs are detected.
0 and ID1 are supplied to the comparator 9, respectively.

The comparator 9 receives the sync patterns ID0 and ID supplied from the sync / ID detection circuits 8 and 11.
1 are compared, and the comparison result SY1 is used as the synchronization position correction circuit 1
Supply to 2. That is, the logical product of the sync pattern shown in FIG. 19C and the sync pattern shown in FIG.
Obtain the output shown at 9E. The sync patterns surrounded by broken lines in FIGS. 19C and 19D are obtained at the same time point. In other words, by comparing the sync pattern ID0 and ID1 supplied from the synchronization / ID detection circuits 8 and 10 with the comparator 9, the sync pattern 2 is obtained.
It is assumed that the sync pattern can be detected if it can be taken continuously.

The synchronous position correction circuit 12 shifts the bits of the digital data from the delay circuit 3 based on the comparison result shown in FIG. 19E. Further, the synchronization position correction circuit 12
It is determined from the value of ID0 that it is the beginning of the block, and if a sync pattern can be detected from the beginning of the block to 6 syncs, the sync pattern SYx is delayed. The delayed sync pattern SYx is as shown in FIG. 19F.

Now, the necessity of delaying the sync pattern SYx will be described. The sync position correction circuit 12 delays the sync pattern SYx based on the comparison result shown in FIG. 19E because the sync pattern SYx is delayed by 6 L through the delay circuits 2 and 3 for the sync pattern of the block having the digital data output. This is because the sync pattern of the block that is supplied later than the block in time is used.

The following is a description of another method using FIG. That is, in the example shown in FIG. 19A, ID0
Since the block of "29" is missing, ID
In order to surely reproduce the data from the block of which "0" is "28", the ID0 shown in FIG. 19A is "27".
The sync pattern SYx is delayed by L based on the comparison result SY1 when the sync pattern can be detected in the block.

The sync pattern SYx shown in FIG. 19F
Is supplied to the inertia circuit 13. Inertia circuit 1
3 is locked to the sync pattern SYx shown in FIG. 19F and generates a temporary synchronization signal SYi as shown in FIG. 19G. The temporary synchronization signal SYi is supplied to the mask circuit 14. The mask circuit 14 uses the temporary synchronization signal S from the inertia circuit 13.
Of Yi, the temporary synchronization signal at an interval shorter than the delay time L is masked. This state is shown in FIG. 19H. In FIG. 19H, “” indicates a sync signal obtained from a sync pattern which can be detected, and “◯” indicates a sync pattern which cannot be detected, and indicates a temporary sync signal generated by the inertia circuit 13. As can be seen from FIG. 19H, the mask circuit 14 does not output a temporary synchronization signal whose interval surrounded by a broken line in FIG. 19G is shorter than the delay time L. The sync signal from the mask circuit 14 is supplied to a reproducing system of a digital VTR (not shown) or the like via an output terminal 15.

On the other hand, the digital data is output after being delayed by the delay circuit 3 by a delay time of 5 L, for example, and supplied to the variable shift register 4. Then, the bit shift is performed by the correction signal from the bit shift phase correction circuit 16 to correct the phase, whereby the break of the data (the missing ID “29” corresponding portion) is shifted and returned to the equivalent. After that, it is supplied to a reproduction system such as a digital VTR (not shown) through the output terminal 5. Therefore, in a digital VTR reproduction system (not shown),
The digital data is reproduced based on the digital data supplied through the output terminal 5 and the synchronization signal SYm supplied through the output terminal 15.

That is, in the synchronizing signal generator shown in FIG. 11, paying attention to the adjacent sync patterns, the second
The two sync patterns are both determined values, the relationship of ID0 indicating the synchronization number is +1, and
When the ID1 indicating the content of the data of the synchronization block is the same, it is determined that the sync pattern has been detected, and the inertia circuit 13 is locked.

Next, the operation of the sync signal detection circuit shown in FIG. 11 when two sync patterns have consecutive errors will be described with reference to FIG.

20A shows the value of ID0 as in FIG. 19A, and FIGS. 20B, C and D show the case where the sync pattern of the block having the value of ID0 of "27" cannot be detected.
0E, F, and G, if the sync patterns of the blocks with ID0 values of “27” and “26” cannot be detected, FIGS. 20H, I, and J have ID data values of “27” and “2”.
The case where the 6 "and" 25 "blocks and the sync pattern cannot be detected is shown.

First, as shown in FIG. 20B, when the sync pattern of the block having the ID0 value of "27" cannot be detected, the comparator 9 determines the block corresponding to the ID0 value of "28" and this block. The sync pattern, ID0, and ID1 of the block adjacent to, that is, the block having the value "27" of ID0 do not match. Therefore, the comparison output output from the comparator 9 is shown in FIG.
20D, the temporary synchronization signal SYi output from the inertia circuit 13 becomes as shown in FIG. 20D. In FIG. 20D, “●” is a sync pattern that can be detected,
“O” indicates a sync signal obtained from the sync pattern generated by the inertia circuit 13, and “x” indicates an error, that is, the sync signal is not output.

Next, as shown in FIG. 20E, when neither of the sync patterns of the blocks whose ID0 values are "27" and "26" can be detected, the comparator 9 outputs the ID0 value "28". The sync pattern of the block corresponding to and the two blocks adjacent to this block, that is, the blocks of ID0 values "27" and "26", I
D0 and ID1 do not match. Therefore, the comparison output output from the comparator 9 is as shown in FIG. 20F, and the synchronization signal output from the inertia circuit 13 is shown in FIG.
As shown in 0G. In this FIG. 20G, "●"
Is a sync signal obtained from the detected sync pattern, “○”
Indicates a sync signal generated by the inertia circuit 13, and "x" indicates an error, that is, the sync signal is not output.

Next, as shown in FIG. 20H, when none of the sync patterns of the blocks with ID0 values of "27", "26" and "25" can be detected, the comparator 9 outputs the ID0 The block corresponding to the value “28” and the three blocks adjacent to this block, that is,
The sync patterns of blocks of ID0 values "27", "26", and "25" do not match the ID0 and ID1.
Therefore, the comparison output output from the comparator 9 is as shown in FIG.
0J, and the temporary synchronization signal SYi output from the inertia circuit 13 becomes as shown in FIG. 20J. In FIG. 20J, “●” indicates a sync signal obtained from the detected sync pattern, “◯” indicates a sync signal generated by the inertia circuit 13, and “x” indicates an error, that is, the sync signal is not output. .

That is, when two or more sync patterns continuously generate an error, all data in the out-of-synchronization section will result in an error. “D” in FIGS. 20D, G and J
As shown in, once the synchronization is achieved, the inertia circuit 13
It is possible to generate a synchronizing signal. The problem that is out of synchronization is the block boundary as shown in FIG. 18D.

The applicant has made it possible to obtain a synchronous output signal on the condition that the timing signals of the synchronizing signals of the video signal portions which successively come in first and the contents of the address data coincide with each other. Therefore, even if a data portion having the same pattern as the sync signal data occurs during the time when the sync signal data arrives, the probability of erroneously determining this as a sync signal can be made sufficiently small in practical use. There has been proposed a sync signal extraction device capable of effectively reducing the risk of malfunction even if the data length of data is shortened (see Japanese Patent Laid-Open No. 60-137150).

Further, the applicant of the present invention converts serial data input in advance into parallel data, and detects the phase which seems to contain the data pattern of the synchronization signal from the data converted into parallel data, and detects the phase. Based on this, the data converted in parallel is shifted, and the synchronization signal is detected for the shifted data, so that the synchronization signal can be detected at a lower speed, which simplifies the circuit configuration. There is proposed a synchronization signal detecting device that can be used (see Japanese Patent Laid-Open No. 1-188132).

[0067]

By the way, since the above-mentioned conventional sync signal generator handles only the adjacent sync patterns, the probability that the sync signal cannot be detected (sync error probability) is very large, and the error correction capability is high. There was an inconvenience that it couldn't handle.

Explaining the sync error probability, the probability that 4 bytes of the sync pattern (SYNC2, ID1, SEC1) will cause an error (byte error rate Psyn)
c) can be expressed as the following equation (1).

Psync = 4 × Pbyte (1)

Here, Pbyte is a byte error rate.

Therefore, when detecting up to 6 syncs at the beginning of the block, if a synchronization error occurs at the beginning,
That is, the probability Pse that the sync signal cannot be detected can be expressed by the following equation (2).

Pse = (Psync) 6+ (Psync) 5 × (1-Psync) × 6 + (Psync) 4 × (1-Psync) 2 × 10 + (Psync) 3 × (1-Psync) 3 × 4 ... (2)

Here, the byte error rate Pbyte =
3 × 10 −3, and assuming that the boundary of the block occurs 1800 times per second, the number Nb of times when the sync cannot be obtained at the boundary of the block is as follows.

Nb = 1/1800 / Pse = 1.3 (min) (3)

This value is a level that is very problematic in practical use. Therefore, the method of handling only the adjacent sync patterns as in the conventional sync signal generation device has a disadvantage that the probability of a sync error is very high.

The present invention has been made in order to solve such a problem, and an object thereof is to propose a synchronization signal generation apparatus capable of suppressing the probability that a sync pattern cannot be detected (sync error probability) to be low.

[0077]

A first aspect of the present invention is a synchronization signal for generating a synchronization signal from digital data in which a synchronization signal having a fixed data pattern having a predetermined number of bits is inserted at a predetermined time interval L. In the generation device, delay means 21, 22, 23, 24, 25 for delaying digital data in units of time interval L to obtain a plurality of digital data having a delay time of n times L (n is a positive integer).
And bit shift detecting means 26 for delaying the digital data bit by bit to detect a phase matching the fixed data pattern, and delay means 21, 22, 23, 24, depending on the detection result of the bit shift detecting means 26. A plurality of bit shift means 27, 28, 29, 30, 3 for bit-shifting a plurality of digital data output from 25, respectively.
1 and a plurality of bit shift means 27, 28, 29, 3
A plurality of sync detecting means 32, 33, 34, 35, 36 for respectively detecting a match between a plurality of digital data bit-shifted by 0, 31 and a fixed data pattern,
A synchronization signal generating means 3 for generating a synchronization signal in accordance with the output signals of the synchronization detecting means 32, 33, 34, 35, 36 which have detected the coincidence between the digital data and the fixed data pattern.
7, 38, 39, 40, 41, 42, 13, and 14.

In a second aspect of the invention, the sync signal generating means is reset by the output signal of the sync detecting means, and an inertia circuit 13 for generating a pulse signal at every time interval L from the reset time and a continuation from the inertia circuit 13. When the interval of the pulse signals supplied in advance is less than or equal to the time interval L, the pulse signal supplied in advance is masked out of the pair of pulse signals with the time interval less than or equal to L for synchronization. The mask circuit 14 outputs as a signal.

In a third aspect of the present invention, a synchronization signal composed of a fixed data pattern having a predetermined number of bits has a predetermined time interval L.
In the synchronizing signal generating device for generating the synchronizing signal from the digital data which has been inserted at the same time and the identification number whose value changes at each predetermined time interval L, the digital data is delayed by the time interval L unit. And delay means 21, 22, 23, 24, 25 for obtaining a plurality of digital data having a delay time of n times L (n is a positive integer).
And bit shift detecting means 26 for delaying the digital data bit by bit to detect a phase matching the fixed data pattern, and delay means 21, 22, 23, 24, depending on the detection result of the bit shift detecting means 26. Bit shift means 27, 28, 29, 30, 31 for respectively bit shifting a plurality of digital data output from 25,
Bit shift means 27, 28, 29, 30, 31
A plurality of synchronization detecting means 32, 33, 34 for detecting the coincidence between a plurality of bit-shifted digital data and the fixed data pattern and the coincidence of the identification number in consideration of the change of the value according to the time interval L. , 35, 36
And the matching of digital data and fixed data pattern,
And the synchronization detecting means 32, 3 which have detected the coincidence of the identification numbers.
Sync signal generating means 37, 38, 39, 40, 4 for generating sync signals in accordance with the output signals of 3, 34, 35, 36.
It is composed of 1, 42, 13, and 14.

In a fourth aspect of the invention, the synchronizing signal generating means is reset by the output signal of the synchronizing detecting means, and an inertia circuit 13 for generating a pulse signal at every time interval L from the reset time, and a continuation from the inertia circuit 13. When the interval of the pulse signals supplied in advance is less than or equal to the time interval L, the pulse signal supplied in advance is masked out of the pair of pulse signals with the time interval less than or equal to L for synchronization. The mask circuit 14 outputs as a signal.

In a fifth aspect of the present invention, a synchronization signal composed of a fixed data pattern having a predetermined number of bits has a predetermined time interval L.
, And the first identification number whose value changes at each predetermined time interval L is inserted, and at the predetermined time interval L, the same value is set in the data unit of the same content. In a synchronization signal generation device for generating a synchronization signal from digital data into which the second identification number is inserted, the digital data is delayed by a time interval L unit, and the delay time is n times L (n is a positive integer). Delay means 21, 22, 23, 24, 25 for obtaining a plurality of digital data having
And bit shift detecting means 26 for delaying the digital data bit by bit to detect a phase matching the fixed data pattern, and delay means 21, 22, 23, 24, depending on the detection result of the bit shift detecting means 26. A plurality of bit shift means 27, 28, 29, 30, 3 for bit-shifting a plurality of digital data output from 25, respectively.
1 and a plurality of bit shift means 27, 28, 29, 3
A plurality of bit shift means 2 connected to 0 and 31 respectively
7, 28, 29, 30, 31 match a plurality of digital data bit-shifted with a fixed data pattern, match a first identification number in consideration of a change in a value according to a time interval L, a second A plurality of synchronization detecting means 32, 33, 34, 35, 36 for respectively detecting the coincidence of the identification numbers of
Matching of digital data and fixed data pattern, first
Synchronization number generation means 37, 38 for generating a synchronization signal in accordance with the output signals of the synchronization detection means 32, 33, 34, 35, 36 which have detected all the coincidence of the identification numbers and the coincidence of the second identification numbers. 39, 40, 41, 42, 13, and 14.

In a sixth aspect of the invention, the synchronizing signal generating means is reset by the output signal of the synchronizing detecting means, and an inertia circuit 13 for generating a pulse signal at every time interval L from the reset time, and a continuation from the inertia circuit 13 When the interval of the pulse signals supplied in advance is less than or equal to the time interval L, the pulse signal supplied in advance is masked out of the pair of pulse signals with the time interval less than or equal to L for synchronization. The mask circuit 14 outputs as a signal.

[0083]

According to the first aspect of the invention described above, the digital data is delayed by the delay means 21, 22, 23, 24 and 25 in units of time interval L, and the delay time is n times L (n is a positive integer). A plurality of digital data having the following are obtained, the bit shift detecting means 26 delays the digital data bit by bit, the phase matching the fixed data pattern is detected, and the plurality of bit shift means 27, 28, 29, 30, 31 are used. In accordance with the detection result of the bit shift detection means 26, a plurality of digital data output from the delay means 21, 22, 23, 24, 25 are bit-shifted respectively, and a plurality of bit shift means 27, 28, 29, 30, A plurality of sync detecting means 32, 33, 34 for respectively detecting the coincidence between a plurality of digital data bit-shifted by 31 and a fixed data pattern. And 35 and 36, the synchronization detecting means detects a match between the digital data and the fixed data pattern 3
2, 33, 34, 35, 36, the synchronizing signal is generated by the synchronizing signal generating means 37, 38, 39, 40, 4
1, 42, 13, and 14 are formed. As a result, even when the sync pattern cannot be taken due to a missing block or an edit gap, the delay means 21,
A correct sync signal can be output when the phase and coincidence of adjacent data among a plurality of digital data having a delay time n times L of 22, 23, 24 and 25 are confirmed.

According to the second aspect of the invention described above, the inertia circuit 13 is reset by the output signal of the synchronization detecting means, generates a pulse signal at every time interval L from the reset time, and continuously outputs from the inertia circuit 13. When the interval of the pulse signals supplied as the time interval is less than or equal to the time interval L, the mask circuit 14 masks the pulse signal supplied earlier from the pair of pulse signals having the time interval less than or equal to L. And outputs as a synchronization signal. Thereby, when the interval of the pulse signals continuously supplied from the inertia circuit 13 is the time interval L or less, the mask circuit 14 is supplied first among the pair of pulse signals having the time interval L or less. The pulse signal can be masked so that it cannot be output as a synchronization signal.

According to the third invention described above, the delay means 2
1, 22, 23, 24, 25 delay the digital data by the time interval L unit to obtain a plurality of digital data having a delay time of n times L (n is a positive integer),
The digital data is delayed bit by bit, the phase that matches the fixed data pattern is detected by the bit shift detection means 26, and the delay means 21, 22, 23, 24, 25 are selected according to the detection result of the bit shift detection means 26. Bit shift means 27 for outputting a plurality of digital data,
28, 29, 30, 31 are bit-shifted, and a plurality of bit-shifting means 27, 28, 29, 30, 31 match a plurality of digital data with a fixed data pattern, and have a time interval L. A plurality of synchronization detecting means 32, each of which is made to match the identification number in consideration of the change of the corresponding value.
33, 34, 35, 36, the sync signals are output in accordance with the output signals of the sync detecting means 32, 33, 34, 35, 36 which detect the coincidence of the digital data and the fixed data pattern and the coincidence of the identification number. The synchronizing signal generating means 37, 3
8, 39, 40, 41, 42, 13, 14 are generated.
As a result, even if the sync pattern cannot be taken due to a block loss, an edit gap, or the like, the delay means 21, 22, 23, 24, and 25 are adjacent to each other among a plurality of digital data having a delay time n times L. A correct sync signal can be output when the phase and matching of matching data are confirmed.

According to the fourth aspect of the invention described above, the inertia circuit 13 is reset by the output signal of the synchronization detecting means, generates a pulse signal at every time interval L from the reset time, and continuously outputs from the inertia circuit 13. When the interval of the pulse signals supplied is less than the time interval L,
The mask circuit 14 masks the pulse signal that is supplied in advance from the pair of pulse signals whose time interval is L or less, and outputs it as a synchronization signal. As a result, when the interval between the pulse signals continuously supplied from the inertia circuit 13 is equal to or less than the time interval L, the mask circuit 14 causes the time interval to be L.
Of the pair of pulse signals below, the pulse signal previously supplied can be masked so that it cannot be output as a synchronization signal.

According to the fifth invention described above, the delay means 2
1, 22, 23, 24, 25 delay the digital data by the time interval L unit to obtain a plurality of digital data having a delay time of n times L (n is a positive integer),
The digital data is delayed bit by bit, the phase that matches the fixed data pattern is detected by the bit shift detection means 26, and the delay means 21, 22, 23, 24, 25 are selected according to the detection result of the bit shift detection means 26. The plurality of digital data output are bit-shifted by a plurality of bit shifters 27, 28, 29, 30, 31 respectively.
Bit shift means 27, 28, 29, 30, 31
A plurality of bit shift means 27, 28,
Matching of a plurality of digital data bit-shifted by 29, 30, 31 with a fixed data pattern, matching of a first identification number in consideration of a change in value according to a time interval L, and matching of a second identification number. Matches are respectively detected by a plurality of synchronization detecting means 32, 33, 34, 35, 36 to detect all of the match between the digital data and the fixed data pattern, the match of the first identification number and the match of the second identification number. In accordance with the output signals of the synchronization detection means 32, 33, 34, 35, 36, the synchronization signals are generated by the synchronization signal generation means 37, 38, 39, 4
0, 41, 42, 13, 14 are generated. As a result, even if the sync pattern cannot be taken due to a block loss, an edit gap, or the like, the delay means 21, 22, 23, 24, and 25 are adjacent to each other among a plurality of digital data having a delay time n times L. When it is confirmed that the phases of the matched data match, that is, the digital data matches the fixed data pattern, the first identification numbers match, and the second identification numbers match, a correct sync signal can be output.

According to the sixth aspect of the invention described above, the inertia circuit 13 is reset by the output signal of the synchronization detecting means, generates a pulse signal at every time interval L from the reset time, and continuously outputs from the inertia circuit 13. When the interval of the pulse signals supplied is less than the time interval L,
The mask circuit 14 masks the pulse signal that is supplied in advance from the pair of pulse signals whose time interval is L or less, and outputs it as a synchronization signal. As a result, when the interval between the pulse signals continuously supplied from the inertia circuit 13 is equal to or less than the time interval L, the mask circuit 14 causes the time interval to be L.
Of the pair of pulse signals below, the pulse signal previously supplied can be masked so that it cannot be output as a synchronization signal.

[0089]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the synchronizing signal generating apparatus of the present invention will be described in detail below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 11 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral 20 is an input terminal to which digital data D0 from a reproduction system of a digital VTR (not shown) is supplied, and reference numerals 21, 22, 23 and 24 are delay circuits for delaying the input data by L, for example. , 25
Is a delay circuit which delays input data by L and outputs it. As shown in the figure, these delay circuits 21, 22, 2
3, 24 and 25 are connected in series, and the delay circuit 2 at the final stage
The output end of 5 is connected to the input end of the variable shift register 48.

Variable shift registers (VSR) 27, 28, 29, 30 and 31 are shift amount data P indicating the shift amount supplied from the bit shift detection circuit 26.
Based on H0, digital data D0 supplied via the input terminal 20 and delay circuits 21, 22, 23 and 2 respectively.
4 latches the signals D1, D2, D3 and D4 supplied from the D4, and signals SD0, SD1, SD2, SD3 and SD4
To get These variable shift registers 27, 28,
29, 30 and 31 output signals SD0, SD1 and SD
2, SD3 and SD4 are synchronization / ID detection circuits 32, 3
3, 34, 35 and 36 respectively.

Now, the relationship between the sync pattern and the bit shift phase and the detection of the bit shift phase by the bit shift detection circuit 26 shown in FIG. 1 will be described with reference to FIG. Of the sync patterns, SYNC1 is "2".
The case where E "and SYNC2 are" D3 "will be described as an example.

"2E" means "0111010" in binary.
0 "and" D3 "are" 11001011 "in binary. In this example, the bit shift detection circuit 26 looks at the first 5 bits of the sync pattern. Therefore, as shown by the arrow N1 in the figure. When the phase is shifted by 1 bit, the first 5 bits of the sync pattern become "11101", and at this time, the bit shift phase becomes 1 bit as shown in the upper right end.

In the figure, the phase is 2 as indicated by the arrow N2.
When there is a bit shift, the first 5 bits of the sync pattern become "11010", and at this time, the bit shift phase becomes 2 bits as shown in the second stage at the right end.

In the figure, the phase is 3 as indicated by arrow N3.
When the bits are deviated, the first 5 bits of the sync pattern become "10100", and at this time, the bit shift phase becomes 3 bits as shown in the third stage at the right end.

In the figure, the phase is 4 as indicated by the arrow N4.
When the bits are deviated, the first 5 bits of the sync pattern become "01001", and at this time, the bit shift phase becomes 4 bits as shown in the rightmost fourth stage.

In the figure, the phase is 5 as indicated by the arrow N5.
When the bits are deviated, the first 5 bits of the sync pattern are "10011", and at this time, the bit shift phase is 5 bits as shown in the fifth rightmost stage.

When the phase is shifted by 6 bits as shown by arrow N6 in the figure, the first 5 bits of the sync pattern are "00110", and at this time, the bit shift phase is 6 bits as shown in the rightmost sixth stage. .

In the figure, the phase is 7 as indicated by arrow N7.
When there is a bit shift, the first 5 bits of the sync pattern become "01100", and at this time, the bit shift phase becomes 7 bits as shown in the rightmost seventh stage.

That is, here, the bit shift detection circuit 26 detects how many bits the shift amount is and the shift amount data PH0 indicating the shift amount is generated.

Next, with reference to FIG. 4, a case of cutting out data corresponding to the bit shift phase will be described.

Variable shift register 2 shown in FIG.
7, 28, 29, 30 and 31 perform a so-called variable shift operation of changing the data cutting position based on the shift amount data PH0 from the bit shift detection circuit 26 described above.

In FIG. 4, the arrow N0 indicates the shift amount "0", the arrow N1 indicates the shift amount "1", the arrow N2 indicates the shift amount "2", the arrow N3 indicates the shift amount "3", and the arrow N4 indicates the shift amount "4". , Arrow N5 indicates shift amount "5", arrow N6 indicates shift amount "6", and arrow N7 indicates shift amount "7".

That is, the arrow N0 indicates the shift amount data PH indicating the shift amount from the bit shift detection circuit 26 described above.
When 0 indicates the shift amount “0”, the data is cut out. As indicated by the arrow N0, the input data D0 to d7 are input.
Is output without being shifted, that is, the input data D0 to
Use d7 as is.

An arrow N1 indicates the cutout of the data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "1", and the input data D0 is indicated as indicated by the arrow N1. The input data D1 to d0 are cut out and used by shifting .about.d7 by 1 bit.

The arrow N2 indicates the cutout of the data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "2", and the input data D0 is indicated as indicated by the arrow N2. The input data D2 to d1 are cut out for use by shifting .about.d7 by 2 bits.

An arrow N3 indicates the cutout of the data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "3". As shown by the arrow N3, the input data D0 .About.d7 are shifted by 3 bits, and input data D3 to d2 are cut out and used.

An arrow N4 indicates the cutout of data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "4", and the input data D0 is indicated as indicated by the arrow N4. The input data D4 to d3 are cut out for use by shifting .about.d7 by 4 bits.

An arrow N5 indicates the cutout of data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "5", and the input data D0 is indicated as indicated by the arrow N5. .About.d7 are shifted by 5 bits and the input data D5 to d4 are cut out and used.

An arrow N6 indicates the cutout of the data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "6", and the input data D0 is indicated as indicated by the arrow N6. The input data D6 to d5 are cut out for use by shifting .about.d7 by 6 bits.

The arrow N7 indicates the cutout of the data when the shift amount data PH0 indicating the shift amount from the above-mentioned bit shift detection circuit 26 indicates the shift amount "7", and as shown by the arrow N7, the input data D0 .About.d7 are shifted by 7 bits and input data D7 to d6 are cut out and used.

The sync / ID detection circuits 32 and 33 detect the sync pattern, ID data and sector data of the signals SD0 and SD1 from the variable shift registers 27 and 28, and compare the detected sync pattern, ID data and sector data respectively. 37, 38, 39, and 40, and the synchronous position correction circuit 4 outputs ID0 and ID1.
Supply to 1.

The sync / ID detection circuits 34, 35, and 36 detect the sync patterns and IDs of the signals SD2, SD3, and SD4 from the variable shift registers 29, 30 and 31, respectively.
0, ID1 detected, detected sync pattern, ID
0 and ID1 are supplied to the comparators 38, 39 and 40, respectively.

The comparator 37 is the synchronization / ID detection circuit 3
Sync pattern from 2, sync ID0 and ID1 / I
Sync pattern from D detection circuit 33, ID0 and ID
A signal SY1 as a comparison result is obtained by comparison with 1, and this signal SY1 is supplied to the synchronization position correction circuit 41.

The comparators 38, 39 and 40 compare the sync patterns, ID0 and ID1, supplied from the sync / ID detection circuits 38, 39 and 40, respectively, with the sync patterns, ID0 and ID1, from the sync / ID detection circuit 32. Then, the signals SY2, SY3 and S as the comparison results are obtained.
Y4 is obtained, and these signals SY2, SY3 and SY4 are supplied to the synchronous position correction circuit 41.

That is, the comparator 38 has a high level "1" when the sync patterns from the sync / ID detection circuits 38 and 39 are coincident with each other, the difference between ID0 is "1", and the ID1 is coincident with each other. The signal of is output.

Further, the comparator 39 outputs a high level "1" when the sync patterns from the synchronization / ID detection circuits 34 and 35 are coincident with each other, the difference between ID0 is "1", and the ID1 is coincident with each other. The signal of is output.

Further, the comparator 40 has a high level "1" when the sync patterns from the sync / ID detection circuits 35 and 36 are coincident with each other, the difference between ID0 is "1", and the ID1 is coincident with each other. The signal of is output.

The sync position correction circuit 41 uses the ID0 and ID1 from the sync / ID detection circuit 32, the comparators 37,
Signals SY1, SY2, SY3 from 38, 39 and 40
And SY4, the synchronous position correction processing is performed, and the result is supplied to the bit shift phase correction circuit 42.

The bit shift phase correction circuit 42 corrects the bit shift phase based on the shift amount data PH0 indicating the shift amount from the bit shift detection circuit 26 and the output from the synchronous position correction circuit 41, and outputs the signal PHL. Then, the signal PHL is supplied to the variable shift register 48.

The variable shift register 48 latches the output of the delay circuit 25 based on the signal PHL from the bit shift phase correction circuit 42, and then supplies it to another circuit such as a VTR (not shown) via the output terminal 49. Since the inertia circuit 13 and the mask circuit 14 are the same as those of the conventional synchronizing signal generating device shown in FIG. 11, their description will be omitted. The internal configurations of the inertia circuit 13 and the mask circuit 14 are the same as those shown in FIGS. 13 and 14.

Next, referring to FIG. 2, the internal structure of the synchronization position correction circuit 41 and the bit shift phase correction circuit 42 shown in FIG. 1 will be described. 2, parts corresponding to those in FIG. 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, 50 is an input terminal to which the signal SY1 which is the comparison result of the comparator 37 shown in FIG. 1 is supplied, and 51 is an input which is supplied with the signal SY2 which is the comparison result of the comparator 38 shown in FIG. Terminals 52 are input terminals to which the signal SY3 which is the comparison result of the comparator 39 shown in FIG. 1 is supplied, and 53 are input terminals which are supplied to the signal SY4 which is the comparison result of the comparator 40 shown in FIG.

The input terminals 50 to 53 are different from the synchronous position correction circuit 9 and the bit shift phase correction circuit 13 shown in FIG. As is clear from FIG. 11 and FIG. 12, in this example, the sync pattern intervals are L to
It detects about 4L. That is, the intervals between the two detected sync patterns are L, 2L,
When 3L and 4L, it is determined that the correct sync pattern has been obtained, and the inertia circuit 13 is initialized. In addition, where the sync pattern cannot be obtained, the signal from the inertia circuit 13 is used to compensate.

Now, the operations of the synchronization position correction circuit 41 and the bit shift phase correction circuit 42 will be described with reference to FIG.

First, the signal SY1 from the comparator 37 supplied to the input terminal 50 shown in FIG. 2 is at the high level "1".
In this case, the result is as shown in FIG. 5A. That is, the input terminal 54
Signal I supplied from the synchronization / ID detection circuit 32 via
When D0 is "1", the signal LD0 is "1", and the signal LD
1 to LD4 are respectively "0", and when the signal ID0 is "2", the signals LD0 and LD1 are respectively "1" and the signal LD
2 to LD4 are respectively "0", and when the signal ID0 is "3", the signals LD0 to LD2 are respectively "1" and the signal LD3.
And LD4 are respectively "0", and when the signal ID0 is "4", the signals LD0 to LD3 are respectively "1" and the signal LD4.
Becomes "0", and when the signal ID0 is "5", the signal L
All of D0 to LD4 are "1". When the signal ID0 is "x", the signal LD0 is "1" and the signals LD1 to L are
D4 becomes "0", respectively.

Next, when the signal SY2 from the comparator 38 supplied to the input terminal 51 shown in FIG. 2 is at the high level "1", it becomes as shown in FIG. 5B. That is, when the signal ID0 supplied from the synchronization / ID detection circuit 32 through the input terminal 54 is "1", the signals LD0 and LD1 are "1", the signals LD2 to LD4 are "0", and the signal ID0 is "1". When the signal ID0 is "3", the signals LD0 to LD2 are "1" and the signals LD3 and LD4 are "0". When the signal ID0 is "3", the signals LD0 to LD3 are "1" and the signal LD4 is "0". , The signals LD0 to LD4 are all "1" when the signal ID0 is "4", and the signals LD0 to LD when the signal ID0 is "5".
4 are all "1", and when the signal ID0 is "x", the signals LD0 and LD1 are "1" and the signals LD2 to LD4.
Becomes "0" respectively.

Next, when the signal SY3 from the comparator 39 supplied to the input terminal 52 shown in FIG. 2 is at the high level "1", it becomes as shown in FIG. 5C. That is, when the signal ID0 supplied from the synchronization / ID detection circuit 32 through the input terminal 54 is "1", the signals LD0 to LD2 are "1", the signals LD3 and LD4 are "0", and the signal ID0 is "1". When the signal ID0 is "3", the signals LD0 to LD3 are "1" and the signal LD4 is "0". When the signal ID0 is "3", the signals LD0 to LD4 are all "1". LD0 to LD
4 are all "1", and when the signal ID0 is "5", all the signals LD0 to LD4 are "1", and the signal ID
When 0 is "x", the signals LD0 to LD2 are "1" and the signals LD3 and LD4 are "0".

Next, when the signal SY4 from the comparator 39 supplied to the input terminal 52 shown in FIG. 2 is at the high level "1", it becomes as shown in FIG. 5D. That is, when the signal ID0 supplied from the synchronization / ID detection circuit 32 via the input terminal 54 is "1", the signals LD0 to LD3 are "1", the signal LD4 is "0", and the signal ID0 is "2". Sometimes the signals LD0 to LD4 are all "1", and when the signal ID0 is "3", the signals LD0 to LD are
When the signal ID0 is "4", all of the signals LD0 to LD4 become "1" when the signal ID0 is "4".
When 0 is "5", signals LD0 to LD4 are all "1", and when signal ID0 is "x", signal LD
0 to LD3 are "1" and the signal LD4 is "0".

It is assumed that "x" has an ID0 other than "1" to "5". When all the signals SY1 to SY4 are "0", the signals LD0 to LD4 are all "0".

Here, the flow of operation of the synchronizing signal generator described with reference to FIGS. 1 and 2 will be described. That is, the input digital data D0 is delayed by the delay time L to obtain the delayed digital data D1, D2, D3 and D4, and further the signal Dx delayed by the delay time 2L by the digital data D4 is obtained.

Next, the bit shift information contained in the sync pattern of the digital data D0 is detected by the bit shift detecting means 26 to obtain shift amount data PH0 indicating the bit shift amount, and the shift amount indicated by this shift amount data PH0. Only variable shift registers 27, 2
Signals SD0, S shifted by 8, 29, 30 and 31
Obtain D1, SD2, SD3 and SD4. And sync /
In the ID detection circuits 32, 33, 34, 35 and 36, the sync patterns of the signals SD0, SD1, SD2, SD3 and SD4 and the data corresponding to the positions of ID0 and ID1 are {SYNC0, ID0_0, ID1_0} and {S0, respectively.
YNC1, ID0_1, ID1_1), ... (SY
NC4, ID0_4, ID1_4), and digital data SD0 and SDm (m = 1, 2, 3, 4) are compared.

This comparison is expressed by the following equation.

SYNC0 = SYNCm = 2EDC (value of determined sync pattern) ID0 = ID0_m + m ID1 = ID1_m (5)

When the equation (5) is satisfied, it is assumed that the sync pattern at the interval of mL is detected, and the synchronization signal SYm output from the mask circuit 14 is made active "1". Then, the synchronization position correction circuit 41 controls the delay amount according to the value of m to obtain the signal SYx. At this time, when a plurality of synchronization signals SYm are detected, the delay amount is determined from the smallest m.

Next, when the inertia circuit 13 for generating the pulse of the period L is reset by the signal SYx, the temporary synchronization signal SYi is obtained.
Therefore, the mask circuit 14 resets with the temporary synchronization signal SYi, delays the temporary synchronization signal SYi by the time L (L clock), and then outputs the synchronization signal SYm. , Temporary sync signal S
The synchronization signal SYm is obtained by masking the portion of the interval shorter than Yi.
To get

At the same time, the bit shift phase correction circuit 4
2, the bit shift amount PH0 when the synchronization signal SYm is detected is also delayed in accordance with the delay amount of the signal SY to obtain the signal PHx, and the signal PHx is supplied to the variable shift register 48, whereby the delay circuit The signal Dx from 25 is bit-shifted to form data with the correct phase.

Next, the operation of the synchronizing signal generator shown in FIGS. 1 and 2 will be described with reference to the flowchart of FIG.

First, in step S1, it is determined whether the pattern of the input signal matches the sync pattern,
If “YES”, the process proceeds to step S2.

In step S2, nL bytes (n = 1, 2, 3, ...) Are used by using the position information of the detected sync pattern.
・) Subsequent data is bit-shifted by the same amount. Then, it is checked whether the data obtained by bit-shifting is a sync pattern, and the continuity of ID0 of the sync block in which the sync pattern is detected and the sync block after nL bytes and I
Check D1 match. Then, the process proceeds to step S3.
That is, the delay circuits 21 to 25 shown in FIG. 1 delay the data by the delay time L to nL (n = 1, 2, 3, ...
...). Then, the synchronization / ID detection circuits 32 to 36 check whether or not it is a sync pattern, whether or not ID0 is continuous, and whether or not ID1 has the same value.

In step S3, it is determined whether or not it is OK, that is, whether ID0 is continuous and ID1 has the same value in the sync pattern. If "YES", the process proceeds to step S4, and "NO". If so, the process proceeds to step S1 again.

In step S4, it is determined whether or not high speed reproduction is performed. If "YES", the process proceeds to step S5 and "N
If "O", the process proceeds to step S6.

In step S5, the delay amount D is set to (1-n) L
To Then, the process proceeds to step S7.

In step S6, when the value of ID0 is the first value of ID0 of the sector -2, the delay amount D is set to (5-n) L.
Similarly, the value of ID0 is the first ID0 value of the sector −
When it is 3, the delay amount D is set to (4-n) L, and ID0 is similarly set.
When the value of is the first ID0-4 of the sector, the delay amount D is set to (3-n) L. Similarly, when the value of ID0 is the value of the first ID0 of the sector-5, the delay amount D is set to (2- n) L,
In other cases, the delay amount D is set to (1-n) L. Then, the process proceeds to step S7.

In step S7, when the delay amount D <L, the delay amount D = L is set. Then, the process proceeds to step S8.

In step S8, the inertia circuit 13 applies L inertia to the synchronizing pulse. Then, the position information is delayed by L, and the data delayed by 6L is bit-shifted and output. Then, the process proceeds to step S1 again.
That is, the output Dx from the delay circuit 25 shown in FIG. 1 is latched and output in the variable shift register 48 based on the signal PHx which is the correction output from the bit shift phase correction circuit 42.

Next, the operation of the sync signal generator will be described in more detail with reference to the timing charts of FIGS.

In FIG. 7A, “” indicates that the sync pattern could be detected. Also, in FIG. 7N,
“●” indicates a sync signal obtained by detecting the sync pattern twice in succession, and “◯” indicates that the sync pattern is not detected twice in succession, and the inertia circuit 13 and the mask circuit 14
Shows the sync signal generated by the.

When digital data as shown in FIG. 7A is supplied from a reproducing system such as a VTR or a digital signal input system not shown, a sync pattern indicated by "●" in FIG. 7A is detected as shown in FIG. 7B. . This signal D
0 is delayed by the delay circuit 21 to become the signal D1 delayed by the time L as shown in FIG. 7C. This signal D1 is delayed by the delay circuit 22 and the signal D2 delayed by the time L as shown in FIG. 7D. And the signal D2 becomes the delay circuit 23.
Becomes the signal D3 delayed by the time L, and this signal D3
Becomes the signal D4 delayed by the time L in the delay circuit 24.

The signal D0 and the signals D1 to D4 obtained by being delayed by the delay circuits 21 to 24 are supplied to the variable shift registers 27, 28, 29, 30 and 31, respectively, and as described above, the variable shift registers 27, 28, 29, 30 and 31, respectively. Register 2
Shift amount data PH0 indicating the shift amount from the bit shift detection circuit 26 at 7, 28, 29, 30 and 31.
Are shifted according to the signals SD0, SD1, SD
2, SD3 and SD4 (all are not shown) are output.

The signals SD0, SD1, SD2, SD3 and SD4 are supplied to the sync / ID detection circuits 32, 33, 34, 35 and 36, respectively, and the sync pattern, ID0 and I
D1 is detected and thereafter comparators 37, 38, 39
And 40, and as described above, it is compared whether or not it is a sync pattern, whether the values of ID0 have continuity, and whether the values of ID1 are the same.

Each comparator 37, 38, 39 and 40
The signals SY1, SY2, SY3 and SY4 as the comparison result from FIG. 7 are shown in FIGS. 7G, H, I and J, respectively. That is, as shown in FIGS. 7B and C, the signal SY1 shown in FIG. 7G becomes a high level “1” when a sync pattern is obtained with both the signal D0 and the signal D1 (enclosed by a broken line in the figure). , Signal SY2 shown in FIG.
When a sync pattern is obtained with both of the signals D0 and D2 shown in FIG. 7 (enclosed by a broken line in the figure), the signal becomes high level “1”, and the signal SY3 shown in FIG. 7I is the signal D0 shown in FIGS. 7B and 7E. And a signal D3 produces a sync pattern (enclosed by a broken line in the figure), the level becomes high "1", and the signal SY4 shown in FIG.
In the case where a sync pattern is obtained with both the signals B0 and D4 shown in FIG. 7B and FIG. 7F (enclosed by a broken line in the figure)
High level becomes "1".

Then, in the synchronous position correction circuit 41, when the bit is raised by the signal SY1 shown in FIG. 7G (when it becomes the high level "1"), the signal SY1 is delayed by 4 L as shown in FIG. 7K, When a bit rises in the signal SY2 shown in FIG. 7H, the signal SY2 is set to 3 as shown in FIG. 7K.
When the signal SY3 shown in FIG. 7I has a bit rising, the signal SY3 is delayed by 2L as shown in FIG. 7K.
7K when a bit is raised by the signal SY4 shown in FIG. 7J.
The signal SY4 is delayed by L as shown in FIG. 7B,
Signals SY1, SY2, SY3 and S shown at C, D and E
When all bits are set to Y4 (FIGS. 7B, C, D and E)
In (7th part counted from the left in the area surrounded by a broken line), it is assumed that bits are set in both the signal D0 and the signal D1.

The signal SYx obtained by such processing in the synchronization position correction circuit 41 is supplied to the inertia circuit 13. In the inertia circuit 13, as shown in FIG. 7L, the temporary synchronization signal SYi is generated at a cycle based on the signal SYx from the synchronization position correction circuit 41, and the temporary synchronization signal SY is generated.
i is supplied to the mask circuit 14. The mask circuit 14 is shown in FIG.
For example, the temporary synchronization signal SYi shown in FIG. 7L is masked with a temporary synchronization signal having a cycle shorter than the other cycles surrounded by a broken line in FIG. 7L to obtain the synchronization signal SYm shown in FIG. 7M, and this synchronization signal SYm is output terminal. A signal STP is supplied via 46 to a main circuit such as a VTR (not shown). Then, as a result of such processing, the sync signal is correctly detected as shown in FIG. 7N, whereby the data can be reproduced well.

Next, with reference to FIG. 8, the operation of the synchronizing signal generator when changing the delay amount based on the ID data will be described. Note that, for the sake of conceptual explanation, the description will be made without adding the symbols as shown in FIGS. 1 and 7 to the signals. Further, in this figure, it is assumed that only the sync signal at the interval of L is detected.

FIG. 8A shows the value of ID0 as an example, and FIG. 8B shows the input data. A sync pattern is detected as shown in FIG. 8C, and delay circuits 21 to 21 are provided as shown in FIG. 8D.
Then, the signal delayed by 25 is obtained, and as shown in FIG. 8E, a signal which becomes a high level "1" only when a bit is raised is obtained in both the signals shown in FIGS. 8B and C, and this signal is delayed. At this time, as indicated by "5" in FIG. 8E, the value of ID0 when the sync pattern can be detected ("9" in the figure
4 ") and the ID when the sync pattern cannot be detected
Since the difference between the values of 0 (“99” in the figure) is “5”, the delay amount is set to “5” (“5L”).

The delayed signal is as shown in FIG. 8F. Based on this signal, the inertia circuit 13 generates the synchronizing pulse as shown in FIG. 8G, and the mask circuit 14 as shown in FIG. 8H masks it. I do. By performing such processing, the sync pattern can be correctly detected as shown in FIG. 8I, and good reproduction can be performed.

Next, with reference to FIG. 9, the operation of the sync signal generator when the sync pattern cannot be detected over the periods L, 2L, 3L will be described.

In FIG. 9, FIG. 9A shows I as an example.
9B, C, and D show the values of D0, FIGS. 9B, C, and D show the case where the sync pattern cannot be detected for the period of L, FIGS. 9E, F, and G show the case where the sync pattern cannot be detected for the period of 2L, and FIGS. The case where a pattern cannot be detected over a 3L period is shown. The shaded area indicates the data-missing portion.

First, with reference to FIGS. 9B, 9C and 9D, the case where the sync pattern cannot be detected over the period L will be described. When the sync pattern cannot be detected over the period L as shown in FIG. 9B, the sync pattern is detected as shown in FIG. 9C, and as shown in FIG. 9D, the cycle based on the sync pattern detected by the inertia circuit 14 is detected. Since the sync signal is generated, the sync signal can be accurately obtained as shown in FIG. 9D. In FIG. 9D, “●” indicates a portion where the sync pattern could be detected, and “◯” indicates a portion where the sync pattern could not be detected.

Similarly, with reference to FIGS. 9E, 9F, 9G, and 9G, the case where the sync pattern cannot be detected over the 2L period will be described. When the sync pattern cannot be detected for a period of 2L as shown in FIG. 9E, the sync pattern is detected as shown in FIG. 9E, and as shown in FIG. 9F, the period based on the sync pattern detected by the inertia circuit 13 is detected. Since the sync pulse is generated, the sync pattern can be accurately obtained as shown in FIG. 9G.

Similarly, a case where the sync pattern cannot be detected for a period of 3L will be described with reference to FIGS. When the sync pattern cannot be detected for a period of 3L as shown in FIG. 9H, the sync pattern is detected as shown in FIG. 9H, and as shown in FIG. 9I, the period based on the sync pattern detected in the inertia circuit 13 is detected. Since the sync signal of FIG.
As shown in J, the synchronization signal can be obtained accurately.

Although the description overlaps with FIG. 7, the case where the sync pattern cannot be detected during the 4L period, the 2L period, and the L period will be described with reference to FIG.

FIG. 10A shows the value of ID data as an example, and FIG. 10B shows the input data. When there is input data as shown in FIG. 10B, the signal D from the input terminal 20
0, output signal D of each delay circuit 21, 22, 23 and 24
1, D2, D3 and D4 are as shown in FIGS. 10C, D, E, F and G, respectively.

At this time, the comparators 37, 38, 3
The signals SY1 to SY4 from 9 and 40 are, as shown in FIG. 10H, the signal D0 and the signal D1 or D2 or D3.
Alternatively, when the sync pattern is taken with D4, the high level becomes "1" (SY1 to SY4 are shown individually in FIG. 7, but are collectively shown in this figure).

Each bit shown in FIG. 10H corresponds to that in FIG.
0I is delayed as shown as signal SYx. That is, as shown in FIG. 10I, the bits set when the sync pattern is taken by both signals D0 and D1 (ID data “31” and “30”, ID data “21”, “20”, Bits (corresponding to "19" respectively) set when "1", that is, L respectively, are delayed as shown in FIG. 10I, and a sync pattern is taken by both signals D0 and D2 (in FIG. 10A). The ID data "corresponding to" 22 ") is delayed by" 2 ", that is, 2L as shown in FIG. 10I, and the bit set when the sync pattern is taken by both signals D0 and D4 (in FIG. 10A). ID data "corresponding to" 24 ") is delayed by" 4 ", that is, 4L, as shown in FIG. 10I.

Therefore, when the signal SYx shown in FIG. 10I is supplied from the synchronization position correction circuit 41 to the inertia circuit 13, the inertia circuit 13 uses the signal SYx shown in FIG. 10I as a reference to generate the temporary synchronization signal SYi shown in FIG. 10J. Occur. Although not shown, a pulse (sixth pulse from the left in the figure) shorter than the interval of other pulses in FIG. 10J is masked by the mask circuit 14. Finally, as shown in FIG. 10K, it is possible to output the synchronization signal to the places where the sync pattern indicated by "○" cannot be obtained, other than the places where the sync pattern indicated by "●" is obtained.

Next, the probability Pse (sync error probability) that the sync signal cannot be detected in the processing of the sync signal generating apparatus described above will be explained.

Sync pattern {SYNC (2 bytes),
The probability Psync in which 4 bytes of ID0 (1 byte), ID1 (1 byte)} cause an error can be obtained in the same manner as in the above equations (1) and (2).

Here, assuming that the byte error rate Pbyte is Pbyte = 3 × 10 −3 and that a block boundary occurs 1800 times per second, for example, a cycle N in which a sync pattern cannot be taken at the block boundary.
b is as follows.

Nb = 1/1800 / Pse = 7.48 (h) (6)

As is clear from this equation (6),
The sync signal generator of this example described with reference to FIG. 10 is significantly improved compared to the conventional sync signal generator, and it can be seen that there is no problem in practical use. By the way, in the conventional synchronizing signal generator, it is 1.3 (minutes) as shown by the equation (3).

As described above, in this example, the intervals of the sync patterns included in the data are L, 2L, 3L, 4L ,.
The probability that the sync pattern cannot be detected because the sync pattern is detected when the phase of the bits of the two sync patterns of nL (n is a positive integer), the ID data, and the like are correct. (Synchronization error rate) can be kept low.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the scope of the present invention.

[0175]

According to the first aspect of the invention described above, a plurality of digital data having a delay time of n times L (where n is a positive integer) are delayed by delaying the digital data by a delay means by a delay unit. Then, the bit shift detection means delays the digital data bit by bit, detects a phase that matches the fixed data pattern, and the plurality of bit shift means outputs the digital data from the delay means according to the detection result of the bit shift detection means. A plurality of synchronization detecting means for respectively bit-shifting a plurality of digital data and detecting a match between the plurality of digital data bit-shifted by the plurality of bit-shifting means and the fixed data pattern; the digital data and the fixed data pattern; The sync signal is formed by the sync signal generating means in accordance with the output signal of the sync detecting means that has detected the coincidence. Therefore, even when the sync pattern cannot be taken due to a block loss, an edit gap, or the like, the phase and coincidence of adjacent data among a plurality of digital data having a delay time n times L of the delay means are confirmed. Sometimes you can output the correct sync signal,
As a result, the probability that the sync pattern cannot be detected is suppressed to a low level, and good reproduction can be performed.

According to the second invention described above, the inertia circuit is reset by the output signal of the synchronization detecting means,
A pulse signal is generated at every time interval L from the reset time, and when the interval of pulse signals continuously supplied from this inertia circuit is less than the time interval L, the mask circuit causes the time interval to be less than L. Of the pair of pulse signals that have been described above, the pulse signal that was supplied in advance is masked and output as a synchronization signal. As a result, when the interval of the pulse signals continuously supplied from the inertia circuit is less than or equal to the time interval L, of the pair of pulse signals with the time interval less than or equal to L, the pulse signal supplied earlier. Can be masked so as not to be output as a sync signal, and thus, a highly accurate sync signal can be obtained, and good reproduction can be performed.

According to the third invention described above, the delay means delays the digital data in units of time interval L,
A plurality of digital data having a delay time of n times L (n is a positive integer) are obtained, the digital data is delayed bit by bit, and the phase matching the fixed data pattern is detected by the bit shift detection means, and the bit shift is performed. In accordance with the detection result of the detection means, a plurality of bit shift means bit-shift a plurality of digital data output from the delay means,
The plurality of synchronization detecting means detect the coincidence between the plurality of digital data bit-shifted by the plurality of bit shift means and the fixed data pattern and the coincidence of the identification number in consideration of the change of the value according to the time interval L. However, since the synchronization signal is generated by the synchronization signal generation means in accordance with the output signal of the synchronization detection means that has detected the coincidence of the digital data and the fixed data pattern and the coincidence of the identification number, the block loss or Even when the sync pattern cannot be taken due to the edit gap or the like, a correct sync signal can be output when the phase and the match of adjacent data among a plurality of digital data having a delay time of n times the delay means are confirmed. , This has the effect that the probability of not being able to detect the sync pattern is kept low, and good playback can be performed.

According to the fourth invention described above, the inertia circuit is reset by the output signal of the synchronization detecting means,
When the pulse signal is generated at every time interval L from the reset time and the interval of the pulse signals continuously supplied from the inertia circuit is less than the time interval L, the mask circuit determines that the time interval is less than L. Of the pair of pulse signals that existed,
Since the pulse signal supplied in advance is masked and output as the synchronizing signal, when the interval of the pulse signals continuously supplied from the inertia circuit is less than the time interval L, the mask circuit changes the time interval. It is possible to mask the pulse signal that was supplied in advance from the pair of pulse signals that were L or less so that it cannot be output as a synchronization signal, and thus a highly accurate synchronization signal can be obtained. There is an effect that good reproduction can be performed.

According to the fifth invention described above, the delay means delays the digital data in units of time interval L,
A plurality of digital data having a delay time of n times L (n is a positive integer) are obtained, the digital data is delayed bit by bit, and the phase matching the fixed data pattern is detected by the bit shift detection means, and the bit shift is performed. Depending on the detection result of the detection means, the plurality of digital data output from the delay means are bit-shifted by the plurality of bit-shifting means, respectively connected to the plurality of bit-shifting means, and bit-shifted by the plurality of bit-shifting means. The plurality of sync detecting means respectively match the plurality of digital data and the fixed data pattern, the first identification number in consideration of the change of the value according to the time interval L, and the second identification number. Detected, and all of the coincidence between the digital data and the fixed data pattern, the coincidence of the first identification number and the coincidence of the second identification number are detected. In accordance with the output signal of the detecting means. Thus generated by synchronizing signal generating means for synchronizing signal, missing blocks, or even when it is not possible to sync pattern by editing gaps, etc., of the delay means L
Of a plurality of digital data having a delay time of n times the same, that is, matching of adjacent data, that is, matching of digital data and fixed data pattern, matching of first identification number, matching of second identification number When it is confirmed that the correct sync signal can be output, the probability that the sync pattern cannot be detected can be kept low, and good reproduction can be performed.

According to the sixth invention described above, the inertia circuit is reset by the output signal of the synchronization detecting means,
When the pulse signal is generated at every time interval L from the reset time and the interval of the pulse signals continuously supplied from the inertia circuit is less than the time interval L, the mask circuit determines that the time interval is less than L. Of the pair of pulse signals that existed,
Since the pulse signal supplied in advance is masked and output as the synchronizing signal, when the interval of the pulse signals continuously supplied from the inertia circuit is less than the time interval L, the mask circuit changes the time interval. It is possible to mask the pulse signal that was supplied in advance from the pair of pulse signals that were L or less so that it cannot be output as a synchronization signal, and thus a highly accurate synchronization signal can be obtained. There is an effect that good reproduction can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a synchronization signal generation device of the present invention.

FIG. 2 is a configuration diagram showing a main part of an embodiment of a synchronization signal generation device of the present invention.

FIG. 3 is an explanatory diagram showing a sync pattern used for describing an embodiment of the synchronization signal generation device of the present invention.

FIG. 4 is an explanatory diagram showing a position of cutting out data in accordance with a phase, which is used for explaining an embodiment of the synchronization signal generation device of the present invention.

FIG. 5 is a graph for explaining an operation of a main part of one embodiment of the synchronization signal generation device of the present invention.

FIG. 6 is a flow chart for explaining a synchronization detection operation of an embodiment of the synchronization signal generation device of the present invention.

FIG. 7 is a timing chart for explaining an operation for explaining one embodiment of the synchronization signal generation device of the present invention.

FIG. 8 is a timing chart for explaining an operation for explaining one embodiment of the synchronization signal generation device of the present invention.

FIG. 9 is a timing chart for explaining the operation for explaining one embodiment of the synchronization signal generation device of the present invention.

FIG. 10 is a timing chart for explaining an operation for explaining one embodiment of the synchronization signal generation device of the present invention.

FIG. 11 is a configuration diagram showing an example of a conventional synchronization signal generation device.

FIG. 12 is a configuration diagram showing an example of a main part of a conventional synchronization signal generation device.

FIG. 13 is a configuration diagram showing an example of a main part of a conventional synchronization signal generation device.

FIG. 14 is a configuration diagram showing an example of a main part of a conventional synchronization signal generation device.

FIG. 15 is a timing chart for explaining the operation of the mask circuit used for explaining the example of the conventional synchronization signal generation device.

FIG. 16 is an explanatory diagram showing an example of a format of a digital VTR for explaining an example of a conventional synchronization signal generation device.

FIG. 17 is an explanatory diagram showing an example of a tape format of a digital VTR for explaining an example of a conventional synchronization signal generation device.

FIG. 18 is an explanatory diagram for explaining a format of digital data used for explaining an example of a conventional synchronization signal generating device and a defect during reproduction.

FIG. 19 is a timing chart for explaining an operation for explaining an example of a conventional synchronization signal generation device.

FIG. 20 is a timing chart for explaining an operation for explaining an example of a conventional synchronization signal generation device.

[Explanation of symbols]

13 inertia circuit 14 mask circuit 21, 22, 23, 24 and 25 delay circuit 26 bit shift detection circuit 27, 28, 29, 30, 31, 48 variable shift register 32, 33, 34, 35 and 36 synchronization / ID detection circuit 37, 38, 39 and 40 Comparator 41 Synchronous position correction circuit 42 Bit shift phase correction circuit 55 Sync delay controller 56, 58, 60, 62, 64 and 66 Delay circuit 57, 59, 61 and 63 Adder circuit 68, 69, 70 , 71, 72 and 73 delay circuits

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 30, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

FIG. 14 shows an example of the internal structure of the mask circuit 14 shown in FIG. 11, and the mask circuit 14 shown in FIG.
Is an input terminal 115 to which the temporary synchronization signal SYi from the inertia circuit 13 shown in FIG. 11 is supplied, and a counter 116 which starts counting after being reset by the temporary synchronization signal SYi supplied via the input terminal 115. And a flip-flop circuit 117 for latching the output of the counter 116, the logical sum of the output of the counter 116 and the output of the non-inverting output terminal Q of the flip-flop circuit 119, and the logical sum thereof. Day of
Input to the input terminal D, and the OR circuit 118
Latch the output from path 118 and output the non-inverting output terminal Q
Force is fed back to the OR circuit 118, and the inverting output terminal
A circuit for supplying the IQ output to the control terminal of the counter 116.
The output terminal 120 for outputting the outputs of the flip- flop circuit 119 and the flip-flop circuit 117 (see FIG. 11).
The output terminal 15 outputs the synchronizing signal SYm.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

On the other hand, the carry signal m2 from the counter 116 are supplied to an OR circuit 118, the OR circuit 118
In, the logical sum is obtained with the signal m4 output from the inverting output terminal IQ of the flip-flop circuit 119. When the carry signal m2 is at high level "1" and the signal m4 is at low level "0 " , the output of the OR circuit 118 is at high level "1". So in this case, at the next clock,
When the signal m1 is in the low level "0", the non-inverting output output terminal Q the high level "1" of the flip-flop circuit 119, the inverting output terminal IQ of the output low level "0"
Then, the operation of the counter 116 is stopped. However, when the signal m1 is input at the high level “1”, the flip-flop circuit 119 is reset and the signal m5 becomes the high level “1”, so that the counter 116 is
Starts to work.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0072

[Correction method] Change

[Correction content]

Pse = (Psync) ⁶ + (Psync) ⁵ × (1-Psync) × 6 + (Psync) ⁴ × (1-Psync) ² × 10 + (Psync) ³ × (1-Psync) ³ × 4 ... (2)

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0137

[Correction method] Change

[Correction content]

At the same time, the bit shift phase correction circuit 4
In 2, also the bit shift amount PH0 when synchronizing signal SYm is detected in accordance with the delay amount of the signal SYx by delaying obtain a signal PHL by, by supplying the signal PHL to the variable shift register 48, the delay circuit The signal Dx from 25 is bit-shifted to form data with the correct phase.

Claims (6)

[Claims] 1. A synchronization signal generation device for generating the synchronization signal from digital data in which a synchronization signal having a fixed data pattern having a predetermined number of bits is inserted at a predetermined time interval L. A delay means for delaying the time interval L unit to obtain a plurality of digital data having a delay time of n times L (n is a positive integer), and delaying the digital data bit by bit to match the fixed data pattern. Bit shift detecting means for detecting the phase, a plurality of bit shift means for respectively bit-shifting the plurality of digital data output from the delay means in accordance with the detection result of the bit shift detecting means, and the plurality of bits. A plurality of digital data bit-shifted by the shift means, and the fixed data pattern A synchronization signal composed of a plurality of synchronization detection means for respectively detecting a coincidence and a synchronization signal generation means for generating a synchronization signal in accordance with an output signal of the synchronization detection means detecting a coincidence between the digital data and the fixed data pattern. Generator. 2. The synchronization signal generating means is reset by the output signal of the synchronization detecting means, and an inertia circuit for generating a pulse signal at every time interval L from the reset time, and a continuation from the inertia circuit. When the interval of the pulse signals supplied by the above is less than or equal to the time interval L, the pulse signal that is supplied in advance is masked from the pair of pulse signals whose time interval is less than or equal to L. The synchronization signal generation device according to claim 1, comprising a mask circuit which outputs the synchronization signal. 3. A synchronization signal composed of a fixed data pattern having a predetermined number of bits is inserted at a predetermined time interval L, and an identification number whose value changes at each of the predetermined time intervals L is inserted. A synchronizing signal generating device for generating the synchronizing signal from the existing digital data, wherein the digital data is delayed by the time interval L unit and has a delay time of n times L (n is a positive integer). And a bit shift detecting means for delaying the digital data bit by bit to detect a phase matching the fixed data pattern, and an output from the delay means according to the detection result of the bit shift detecting means. A plurality of bit shift means for respectively bit shifting a plurality of digital data to be generated, and the plurality of bit shift means. A plurality of sync detecting means for respectively detecting the coincidence of a plurality of digital data that has been shifted and the fixed data pattern, and the coincidence of the identification number in consideration of the change of the value according to the time interval L; and the digital data. And a fixed data pattern, and a sync signal generating device for generating a sync signal in accordance with an output signal of the sync detecting means that detects the matching of the identification numbers. 4. The inertia signal is reset by the output signal of the synchronization detecting means, and an inertia circuit for generating a pulse signal at each time interval L from the reset time is connected to the inertia circuit. When the interval of the pulse signals supplied by the above is less than or equal to the time interval L, the pulse signal that is supplied in advance is masked from the pair of pulse signals whose time interval is less than or equal to L. The synchronization signal generation device according to claim 3, comprising a mask circuit which outputs the synchronization signal. 5. A synchronization signal composed of a fixed data pattern having a predetermined number of bits is inserted at a predetermined time interval L, and a first identification number whose value changes at each of the predetermined time intervals L is set. A synchronization signal generation device that generates the synchronization signal from digital data that is inserted and that has the second identification number that has the same value in the data unit of the same content inserted every predetermined time interval L. A delay means for delaying the digital data by the time interval L unit to obtain a plurality of digital data having a delay time n times L (n is a positive integer); and delaying the digital data bit by bit. , A bit shift detection means for detecting a phase that matches the fixed data pattern, and a composite output from the delay means according to the detection result of the bit shift detection means. A plurality of bit shift means for respectively bit-shifting a number of digital data, and a plurality of digital data bit-shifted by the plurality of bit shift means, respectively connected to the plurality of bit shift means, and the fixed data pattern And a plurality of synchronization detecting means for respectively detecting the coincidence of the first identification number and the coincidence of the second identification number in consideration of the change of the value according to the time interval L, the digital data and the fixed data. Synchronization consisting of synchronization signal generation means for generating a synchronization signal in response to the output signal of the synchronization detection means which has detected all of the coincidence with the pattern, the coincidence of the first identification number and the coincidence of the second identification number. Signal generator. 6. The inertia signal is reset by the output signal of the synchronization detection means, and an inertia circuit for generating a pulse signal at each time interval L from the reset time is connected to the inertia circuit. When the interval of the pulse signals supplied by the above is less than or equal to the time interval L, the pulse signal that is supplied in advance is masked from the pair of pulse signals whose time interval is less than or equal to L. The sync signal generator according to claim 5, comprising a mask circuit for outputting the sync signal.