JPH06334127A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which prevents a latch-up phenomenon in a MOS transistor which is formed near a scribing region. CONSTITUTION:A P-well region 4 is formed in an N-type epitaxial growth layer 2 which is formed on an element region near a scribing region in a P-type semiconductor substrate 1. An NMOS transistor which is composed of a source region 6, a drain region 7 and a gate electrode 9 is formed in the P-well region 4. The source region 6 is connected to a VSS terminal 11, the P-well region 4 is connected to a VBB terminal 18, and the N-type epitaxial growth layer 2 is connected to a VCC terminal 15. The P-type semiconductor substrate 1 is connected to the VSS terminal 11 by a P-well region 5 which is formed in the scribing region at the end of the element region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit, and more particularly to a CMOS integrated circuit formed near a scribe region.

[0002]

2. Description of the Related Art As the operating speed of LSIs increases and the integration density increases, the power consumption per chip increases, and the demand for CMOS devices with low power consumption increases. While miniaturization and large capacity of the device improve the operating speed, latch-up causes the device to malfunction and break down.

By the way, a large number of elements formed on a wafer are separated into individual pellets by a scribing process. A region for this separation is called a scribe region, and no LSI functional element is formed in this scribe region.
However, as the capacity of the device increases, the scribe region becomes narrower, and many devices are formed at the edge of the device region near the scribe region.

CMOS formed near the scribe region
The circuit will be described with reference to FIG. The CMOS circuit is provided with an N-type epitaxial growth layer 22 on a P-type semiconductor substrate 21.
In this case, the NMOS transistor is formed on the P well region 23 provided in the epitaxial growth layer 22. The NMOS transistor comprises an N ⁺ type source region 24 and a drain region 25 formed in the P well region 23.
And a gate electrode 27 formed via the insulating film 26.

Here, the source region 24 is connected to the source contact 28 and the V _SS terminal 29, and the drain region 25 is connected to the drain contact 30. The epitaxial growth layer 22 is connected to the N well contact 32 and the V _CC terminal 33 in the N ⁺ type region 31, and the P well region 23 is connected to the V _BB terminal 36 in the P ⁺ type region 34.
(Negative potential generated by self substrate bias generation circuit)
Connected to.

As described above, the functional element is formed in the element region but not in the scribe region. By the way, due to mechanical cutting in the scribing process, crystal defects exist in the scribing region. Therefore, the semiconductor substrate 21 and the epitaxial growth layer 22 are not electrically separated and have the same potential. As a result, as shown in FIG. 2B, the parasitic thyristor composed of the P-type semiconductor substrate 21, the N-type epitaxial growth layer 22, the P-well region 23, and the N ⁺ -type source region 24 is in a conductive state, that is, latch-up. The structure is likely to occur.

For example, immediately after the power is turned on, the P-well region 23 connected to the self-substrate bias generating circuit is in a state close to floating until the self-substrate bias generating circuit operates. Therefore, due to the capacitive coupling between the P well region 23 and the N-type epitaxial growth layer 22, the potential of the P well region 23 temporarily rises in the positive direction. At this time, when the P well region 23 becomes higher than the V _SS potential, the N ⁺ type source region 24 and the P well region 2 are formed.
3 and the NPN parasitic bipolar transistor composed of the N-type epitaxial growth layer 22 become conductive. Further, since the P-type semiconductor substrate 21 has the same potential as the V _CC potential, the PNPN parasitic thyristor including the P-type semiconductor substrate 21, the N-type epitaxial growth layer 22, the P-well region 23 and the N ⁺ -type source region 24 is formed. Is conductive, that is, a latch-up phenomenon occurs.

[0008]

As described above, in the MOS transistor formed in the vicinity of the scribe region, latch-up is likely to occur due to crystal defects generated in the scribe region. The scribe region is narrowed as the integration density is improved, and the influence of the crystal defects is serious. The current flowing between the V _CC voltage and the V _SS voltage due to latch-up cannot be blocked unless the power supply voltage is lowered.

Therefore, it is an object of the present invention to provide a semiconductor device which prevents a latch-up phenomenon from occurring in a MOS transistor formed near a scribe region.

[0010]

A semiconductor device according to the present invention comprises a P-type semiconductor substrate connected to a V _SS voltage and a self-substrate bias circuit provided in an N-type epitaxial growth layer on the P-type semiconductor substrate. It is composed of a connected P well region and an NMOS transistor formed in the P well region and having an N-type source region connected to the V _SS voltage.

The P-type semiconductor substrate is provided with another P-well region connected to the V _SS voltage on the P-type semiconductor substrate at the end of the scribe region and the device region, thereby providing V _SS.
Connected to the voltage.

[0012]

According to the above construction, even if a crystal defect occurs in the scribe region, the other P well region is formed at the scribe region and the end of the element region.
The P-type semiconductor substrate and the N-type epitaxial growth layer are electrically separated. Even when the parasitic bipolar transistor composed of the N-type source region, the P-well region and the N-type epitaxial layer is conductive, the P-type semiconductor substrate, the N-type epitaxial growth layer and the P-well region are also provided. In the parasitic thyristor consisting of the N type source region and the N type source region, the P type semiconductor substrate corresponding to the cathode and the N type source region corresponding to the anode have the same potential. Therefore, it is possible to prevent the latch-up phenomenon due to the conduction of the parasitic thyristor.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. After acceptor ions are implanted into the element region end and the scribe region on the P-type semiconductor substrate 1, the N-type epitaxial growth layer 2 is formed on the semiconductor substrate 1. At this time, since the acceptor ions implanted at the end of the element region diffuse into the N-type epitaxial growth layer 2, the P-type region 3 electrically connected to the P-type semiconductor substrate 1 in the N-type epitaxial growth layer 2 at the end of the element region. Is formed. A P well region 4 is formed on the N type epitaxial growth layer 2, and a P well region 5 is formed on the P type region 3. NM on the P-well region 4
The OS transistor is formed, and the NMOS transistor is composed of the N ⁺ type source region 6 and the drain region 7 formed in the P well region 4, and the gate electrode 9 formed through the insulating film 8.

Here, the source region 6 is connected to the source contact 10 and the V _SS terminal 11, and the drain region 7 is connected.
Is connected to the drain contact 12. The epitaxial growth layer 2 is connected to the N well contact 14 and the V _CC terminal 15 in the N ⁺ type region 13, and the P well region 4 is connected to the P well contact 17 in the P ⁺ type region 16.
And V _BB terminals (negative potential generated by the self-substrate bias generating circuit) 18. On the other hand, P well region 5
Is connected to P well contact 20 and V _SS terminal 11 in P ⁺ type region 19.

With such a structure, the P-type semiconductor substrate 1, the N-type epitaxial growth layer 2, the P-well region 4, and the source region 6 of the NMOS transistor, which corresponds to the node P in the PNPN parasitic thyristor.
The type semiconductor substrate 1 and the source region 6 corresponding to the cathode are both connected to the V _SS terminal 11, and the latch-up phenomenon including the P type semiconductor substrate 1 is unlikely to occur.

For example, after the power is turned on and before the self-substrate bias generating circuit operates, the potential of the P well region 4 becomes higher than the V _SS potential because of the capacitive coupling of the P well region 4 with the N type epitaxial growth layer. , N type source region 6, P well region 4 and N type epitaxial growth layer 2
It is assumed that the NPN parasitic bipolar transistor composed of is turned on. Even in that case, the P-type semiconductor substrate 1 is V
_Since it is the _SS potential, the PNPN parasitic thyristor will not be in a conductive state. After that, when the self-substrate bias generating circuit operates and the P well region 4 becomes a negative potential, the NPN parasitic bipolar transistor is turned off, and the through current between the V _CC voltage and the V _SS voltage stops flowing.

[0017]

In the semiconductor device according to the present invention, since the P well region connected to the V _SS terminal is provided on the P type semiconductor substrate at the end of the scribe region and the element region, the P type semiconductor substrate becomes the V _SS terminal. It is electrically connected. for that reason,
A parasitic thyristor consisting of a P-type semiconductor substrate, an N-type epitaxial growth layer, a P-well region connected to the self-substrate bias generation circuit, and a source region connected to the V _SS terminal is conducted on the element region near the scribe region. By doing so, it is possible to prevent the occurrence of the latch-up phenomenon.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device of an embodiment according to the present invention.

FIG. 2 is a sectional view (a) showing a conventional semiconductor device and a circuit diagram (b) of a parasitic thyristor.

[Explanation of symbols]

1 ... P-type semiconductor substrate, 2 ... N-type epitaxial growth layer,
3 ... P-type region 4, 5 ... P-well region, 6 ... Source region, 7 ... Drain region, 8 ... Insulating film 9 ... Gate electrode, 10 ... Source contact, 11 ... V _SS
Terminal 12 ... Drain contact, 13 ... N ⁺ type region, 14 ...
N-well contact 15 ... V _CC terminal, 16 ... P ⁺ type region, 17 ... P well contact 18 ... V _BB terminal, 19 ... P ⁺ type region, 20 ... P well contact

Claims (2)

[Claims] 1. A P-type semiconductor substrate, an N-type epitaxial growth layer formed on the P-type semiconductor substrate, a P-well region formed in the N-type epitaxial growth layer and connected to a self-substrate bias generating circuit, An NMOS transistor formed on the P well region,
A semiconductor device, wherein the source region of the semiconductor substrate and the source region of the NMOS transistor have the same potential. 2. The semiconductor according to claim 1, wherein the P-type semiconductor substrate has the N-type epitaxial layer in an element region on the P-type semiconductor substrate and has a P-well region at an end of the element region. apparatus.